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A current conveyor based field programmable analog array

analog INTEGRATED CIRCUITS AND SIGNAL PROCESSING 1998年第1-2期17卷 105-124页

作者： Premont, C Grisel, R Abouchi, N Chante, JP Inst Natl Sci Appl Lyon CIMIRLY F-69621 Villeurbanne France EP CNRS 0092 LISA CPE F-69616 Villeurbanne France Inst Natl Sci Appl Lyon CEGELY F-69621 Villeurbanne France

An approach for designing a field programmable analog array (FPAA) is described. The analog array is based on current conveyors and benefits from two major interests: a large bandwidth and a low number of discrete components needed for the implementation of analog functions. An analog Elementary Cell (AEC), based on current conveyors has been developed, and it is associated with programmable resistors and capacitors. analog functions can be performed programming several AECs as current-mode amplifiers, analog multipliers, etc. The main purpose of this paper is to introduce current conveyor based analog blocks which are very-well suited for the implementation of FPAA. A particular interconnection architecture is addressed using current conveyors as switches. The major key feature of the proposed approach is that current conveyors are used as active elements and switching elements. A new topology based on the developed AEC is proposed and should be shortly validated.

关键词： field programmable analog array current conveyor

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LOW VOLTAGE CURRENT CONVEYOR-BASED field programmable analog array

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2011年第8期20卷 1677-1701页

作者： Mahmoud, Soliman A. Soliman, Eman A. Sharjah Univ Elect & Comp Engn Dept Sharjah Univ City 27272 Sharjah U Arab Emirates Fayoum Univ Dept Elect Engn Al Fayyum Egypt German Univ Cairo Elect & Elect Engn Dept Cairo 11835 Egypt

In this paper a low voltage low power field programmable analog array (FPAA) is realized. The FPAA configurable analog block (CAB) design is based on three-bit digitally controlled fully differential current conveyor. The FPAA consists of seven CABs. The CABs are directly connected together without adding extra hardware by placing them in a hexagonal lattice arrangement. A variable gain amplifier, tunable second-order low-pass filter, and a tunable second-order band-pass filter are realized as an application for the FPAA. The FPAA total power consumption is 105.12 mW at 1V supply. The FPAA is realized using IBM 90 nm CMOS technology model from MOSIS under voltage supply of +/- 0.5 V.

关键词： Configurable analog block current division network digitally controlled fully differential current conveyor field programmable analog array tunable band-pass filter tunable low-pass filter variable gain amplifier

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High-Bandwidth,Low-Power CMOS Transistor Based CAB for field programmable analog array

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Computers, Materials & Continua 2023年第3期74卷 5885-5900页

作者： Ameen Bin Obadi Alaa El-Din Hussein Samir Salem Al-Bawri Kabir Hossain Abdullah Abdulhameed Muzammil Jusoh Thennarasan Sabapathy Ahmed Jamal Abdullah Al-Gburi Mahmoud A.Albreem Advanced Communication Engineering(ACE) Centre of ExcellenceUniversiti Malaysia Perlis(UniMAP)Faculty of Electronic Engineering TechnologyKangar01000Malaysia Electrical Engineering King Fahd University of Petroleum and MineralsDhahranEastern31261Saudi Arabia Space Science Centre Climate Change InstituteUniversiti Kebangsaan MalaysiaBangi43600Malaysia Department of Electronics&Communication Engineering Faculty of Engineering&PetroleumHadhramout UniversityAl-MukallaHadhramout50512Yemen Faculty of Engineering Norwegian University of Science and Technology(NTNU)GjovikN-2815Norway Faculty of Electronic Engineering Technology Universiti Malaysia Perlis(UniMAP)Kampus Alam UniMAP Pauh PutraArau02600Malaysia Department of General Educational Development Faculty of Science and Information Technology(FSIT)Daffodil International UniversityDhaka1207Bangladesh Department of Electronics and Computer Engineering(FKEKK) Center for Telecommunication Research and Innovation(CeTRI)Universiti Teknikal Malaysia Melaka(UTeM)Durian Tungal76100Malaysia Department of Electrical Engineering University of SharjahSharjah27272United Arab Emirates

This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are *** proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass *** functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface *** architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six ***,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional ***,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed *** of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS *** design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 *** demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this ***,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.

关键词： CMOS field programmable analog array configurable analog block current mode circuit

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Implementation of Various Chaotic Spiking Oscillators Based on field programmable analog array

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2023年第11期E106A卷 1432-1435页

作者： Matsuoka, Yusuke Natl Inst Technol NIT Yonago Coll Dept Integrated Engn Electr & Elect Div Yonago 6838502 Japan

In this paper, a circuit based on a field programmable analog array (FPAA) is proposed for three types of chaotic spiking oscillator (CSO). The input/output conversion characteristics of a specific element in the FPAA can be defined by the user. By selecting the proper characteristics, three types of CSO are realized without changing the structure of the circuit itself. Chaotic attractors are observed in a hardware experiment. It is confirmed that the dynamics of the CSOs are consistent with numerical simulations.

关键词： programmable device field programmable analog array chaos oscillator

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Hybrid QRS Detection Circuit Based on Dynamic Reconfigurable field programmable analog array

Hybrid QRS Detection Circuit Based on Dynamic Reconfigurable...

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10th IFAC Workshop on programmable Devices and Embedded Systems (PDeS)

作者： Malcher, Andrzej Pietraszek, Stanislaw Przybyla, Tomasz Silesian Tech Univ Inst Elect Gliwice Poland

ISBN: (纸本)9783902661951

In many medical applications it is important to detect the QRS complex in the electrocardiogram (ECG) waveform with possibly low time delay. Traditional software detectors of the QRS complex implement algorithms usually based on cascades of digital filters introduce delays up to parts of a second. Hardware QRS detectors fulfill the low delay requirements, but have worse adaptive features for the changing ECG shape. In this paper a new approach to QRS detection is presented. The proposed detector is based on a field programmable analog array (FPAA). The most interesting feature of the FPAA is the dynamic reconfigurability. This solution makes it possible to modify the parameters of particular blocks of the detector or even the whole structure during runtime, without any changes in hardware and disturbance of the system functionality. The prototype QRS detector was built using AN221E04 circuit from the Anadigm company. The reconfiguration data are calculated by the AD7020 microcontroller and downloaded to the FPAA after each QRS detection.

关键词： QRS detector field programmable analog array baseline drift cardiac assist device artificial stimulator pacemaker

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Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a field programmable analog array and a General Purpose Genetic Algorithm IP Core

Self-Reconfigurable Mixed-Signal Integrated Circuits Archite...

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8th International Conference on Evolvable Systems

作者： Keymeulen, Didier Stoica, Adrian Zebulum, Ricardo Katkoori, Srinivas Fernando, Pradeep Sankaran, Hariharan Mojarradi, Mohammad Daud, Taher CALTECH Jet Prop Lab 4800 Oak Grove Dr Pasadena CA 91109 USA Univ S Florida Tampa FL 33620 USA

ISBN: (纸本)9783540858560

Development of analog electronics solutions for space avionics is expensive and time-consuming. Lack of flexible analog devices, counterparts to digital field programmable Gate arrays (FPGA), prevents analog designers from the benefits of rapid prototyping. This forces them to expensive and lengthy custom design, fabrication, and qualification of application specific integrated circuits (ASIC). This paper describes a recent FPAA design, the Self-Reconfigurable analog array (SRAA) that was developed at JPL. It has a large variety of analog building block components in the cells of the array and allows to operate over it wide range of temperature using a built in general purpose genetic algorithm (GA) engine as an intellectual property (IP) core.

关键词： field programmable analog array Self-reconfigurable Self-Healing and Compensation

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Novel CCII-based field programmable analog array and its Application to a Sixth-Order Butterworth LPF

Novel CCII-based Field Programmable Analog Array and its App...

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作者： Mahmoud, S. A. Brno University of Technology

In this paper, a field programmable analog array (FPAA) is proposed. The proposed FPAA consists of seven configurable analog blocks (CABs) arranged in a hexagonal lattice such that the CABs are directly connected to each other. This structure improves the overall frequency response of the chip by decreasing the parasitic capacitances in the signal path. The CABS of the FPAA is based on a novel fully differential digitally programmable current conveyor (DPCCII). The programmability of the DPCCII is achieved using digitally controlled three-bit MOS ladder current division network. No extra biasing circuit is required to generate specific analog control voltage signals. The DPCCII has constant standby power consumption, offset voltage, bandwidth and harmonic distortions over all its programming range. A sixth-order Butterworth tunable LPF suitable for WLAN/WiMAX receivers is realized on the proposed FPAA. The filter power consumption is 5.4mW from 1V supply; it’s cutoff frequency is tuned from 5.2 MHz to 16.9 MHz. All the circuits are realized using 90nm CMOS technology from TSMC. All simulations are carried out using Cadence.

关键词： Current division network digitally programmable current conveyor field programmable analog array tunable WLAN/WiMAX receivers

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Hybrid QRS Detection Circuit Based on Dynamic Reconfigurable field programmable analog array

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IFAC Proceedings Volumes 2010年第24期43卷 48-53页

作者： Andrzej MALCHER Stanislaw PIETRASZEK Tomasz PRZYBYłA Silesian University of Technology Institute of Electronics Gliwice Poland

关键词： QRS detector field programmable analog array baseline drift cardiac assist device artificial stimulator pacemaker

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analog IMPLEMENTATION OF NON INTEGER ORDER INTEGRATOR VIA field programmable analog array

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IFAC Proceedings Volumes 2006年第11期39卷 107-111页

作者： Riccardo Caponetto Domenico Porto I.E.E.S University of Catania Eng. Faculty Viale A. Doria 6 95125 Catania Italy Automotive Group STMicroelectronics Contrada Blocco Torrazze C.P. 421 95121 Catania Italy

Recently a renewed interest has been devoted to non integer, or fractional, order systems. This is due to the fact that they well model a lot of physical systems and can be usefully applied in the area of automatic control. On drawback, mainly faced in the area of control systems, is related to their practical realization, essentially due to their infinite dimension nature. In this paper it is proposed an analog implementation of a non integer order integrator by using field programmable analog array. The reported example shows the feasibility and reliability of the proposed approach.

关键词： Non integer order system analog implementation field programmable analog array

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Implementation and Behavior of Basic Filters Involving the Delay Element e-τs

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2025年第5期44卷 3659-3671页

作者： Nako, Julia Elwakil, Ahmed S. Psychalinos, Costas Univ Patras Dept Phys Elect Lab Rion 26504 Greece Univ Sharjah Dept Elect Engn POB 27272 Sharjah U Arab Emirates Univ Calgary Dept Elect & Software Engn Calgary AB Canada Nile Univ Nanoelect Integrated Syst Ctr NISC Giza Egypt

The gain and phase responses of the delay element e-tau s are related through a non-linear relation, unlike the conventional e-tau s delay element where the gain is constant over the entire frequency range. This makes this fractional-order element attractive for describing the dynamics of systems with dead-time zone. In this work, the transfer function of this element is approximated through a rational integer-order function resulting from a curve-fitting based method. The performed comparison with the literature shows that the curve-fitting based approximation method achieves errors in gain and phase less than 0.3dB and 2o, respectively, while the available method in the literature achieves 3.7dB and 8o, respectively. The behavior of some filters involving this delay element is evaluated and it is demonstrated that the implementation of these filters can be performed by the same circuit core, simply by adjusting the coefficients of the approximation transfer function. The findings of this work are supported by MATLAB simulation results and, also, by experimental results obtained through the utilization of a field programmable analog array device.

关键词： analog signal processing analog filters Fractional-order filters Time-delay filters field programmable analog array

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