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IEEE Potentials 1999年第4期18卷 34-36页

作者： Verma, Himanshu Washington State University Pullman WA United States

Reconfigurable computing via field programmable gate arrays (FPGAs) is a remarkable technology with tremendous growth potential, as proven by the proliferating application areas to which it is being applied. This article shows that by a small change in perspective, the programming methods of both instruction set processors and FPGAs are analogous, though they may initially not seem so.

关键词： field programmable gate arrays

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Novel Physical Unclonable Function Implementation for Microcontrollers and field programmable gate arrays

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IEEE ACCESS 2025年 13卷 55970-55983页

作者： Grossi, Marco Omana, Martin Metra, Cecilia Acquaviva, Andrea Univ Bologna Dept Elect Energy & Informat Engn Guglielmo Marcon I-40136 Bologna Italy

Physical Unclonable Functions (PUFs) are frequently exploited for security purposes. In particular, they are adopted to generate unique authentication passwords and cryptographic keys, with no need to store any secret information in non-volatile memories that can be easily attacked. In this paper, we present a novel PUF based structure, that can be implemented at low costs in microcontrollers and FPGAs, by exploiting the circuitry that is already present in their General Purpose Input-Output (GPIO) interface. The proposed PUF based scheme has been implemented on five different FPGA devices, in order to experimentally verify their correct operation under various realistic operating conditions. We will show that our proposed PUF based structure features a good uniqueness (of the 49.75%), a uniformity close to the ideal value of the 50%, an average steadiness of the 99.33%, and a maximum reliability of the 99.61%, for a temperature ranging from 5 degrees C to 65 degrees C.

关键词： field programmable gate arrays Physical unclonable function Microcontrollers Oscillators Pins Cryptography Reliability Internet of Things Authentication Switches Physical unclonable functions microcontroller FPGA security

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field programmable gate arrays based overcurrent relays

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ELECTRIC POWER COMPONENTS AND SYSTEMS 2004年第3期32卷 247-255页

作者： Ahuja, S Kothari, L Vishwakarma, DN Balasubramanian, SK Banaras Hindu Univ Inst Technol Dept Elect Engn Varanasi 22105 Uttar Pradesh India

This paper presents a novel technique of implementing overcurrent relays on field programmable gate arrays (FPGA), which can be used for the protection of distribution lines, large industrial motors and many equipments of the power system. Due to its reconfigurability, it gives an idea to implement many types of relays on the single FPGA board. In case of microprocessor based relays, many peripheral devices are required making the operation slower;but in the case of FPGA, the same can be realized with less number of peripherals, thus making the operation faster. The proposed overcurrent relay gives satisfactory results when simulated on the Xilinx FPGA, thus providing the best solution in the existing technologies.

关键词： overcurrent relay relay protection field programmable gate arrays

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field programmable gate arrays-based differential evolution coprocessor: a case study of spectrum allocation in cognitive radio network

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IET COMPUTERS AND DIGITAL TECHNIQUES 2013年第5期7卷 221-234页

作者： Anumandla, Kiran Kumar Peesapati, Rangababu Sabat, Samrat L. Udgata, Siba K. Abraham, Ajith Univ Hyderabad Sch Phys Hyderabad 500046 Andhra Pradesh India Univ Hyderabad Sch Comp & Informat Sci Hyderabad 500046 Andhra Pradesh India Sci Network Innovat & Res Excellence Machine Intelligence Res Labs Auburn WA 98071 USA

In this study, a scalable coprocessor for accelerating the Differential Evolution (DE) algorithm is presented. The coprocessor is interfaced with PowerPC embedded processor of Xilinx Virtex-5 FX70T field programmable gate Array. In the proposed design, the DE algorithm module is tightly coupled with fitness function module to reduce communication and control overhead. The fixed point DE algorithm is implemented in the coprocessor whereas both fixed and floating point DE are implemented in the embedded processor. Performance of the coprocessor is evaluated by optimising benchmark functions of different complexities. The implementation results show that the coprocessor is 73.14-160.2x and 2.19-27.63x faster compared to the software execution time of the floating and fixed point algorithm respectively. As a case study, spectrum allocation problem of cognitive radio network is evaluated with the coprocessor. Results show an acceleration of 76.79-105x and 5.19-6.91x with respect to floating and fixed point DE in embedded processor. It is also observed that the application occupies 56% of BRAM, 54% of DSP48E, 16% of slice LUTs and maximum frequency of operation as 63.55 MHz in a Virtex-5 FPGA. This type of coprocessor is suitable for embedded applications where the fitness function remains unchanged.

关键词： cognitive radio coprocessors embedded systems field programmable gate arrays floating point arithmetic coprocessor development spectrum allocation problem floating point algorithm fixed point algorithm direct software execution embedded processor fitness function evaluation module Xilinx Virtex 5 field programmable gate array hardcore PowerPC embedded processor DE algorithm scalable coprocessor cognitive radio network spectrum allocation differential evolution coprocessor field programmable gate arrays

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field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decoders

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IET COMMUNICATIONS 2012年第12期6卷 1670-1675页

作者： Arnone, L. J. Castineira Moreira, J. Farrell, P. G. Univ Mar del Plata Sch Engn Dept Elect Mar Del Plata Buenos Aires Argentina Univ Lancaster Sch Comp & Commun Lancaster England

Low-density parity-check (LDPC) codes are very efficient error control codes that are being considered for use in many next-generation communication systems. In this study low complexity soft-input, soft-output (SISO) field programmable gate arrays (FPGA) implementations of a novel logarithmic sum-product (LogSP) iterative LDPC decoder and a recently proposed simplified soft Euclidean distance (SSD) iterative LDPC decoder are presented, and their complexities and performance are compared. These implementations operate over any choice of parity check matrix (including those randomly generated, structurally generated and either systematic or non-systematic) and can be parametrically adapted for any code rate. The proposed implementations are both of very low complexity, because they operate using only sums, subtractions, comparisons and look-up tables, which makes them particularly suitable for FPGA realisation. The SSD decoder has a lower implementation complexity than the LogSP LDPC decoder and it also offers the advantage of not requiring knowledge of the channel signal-to-noise ratio, unlike most other LDPC decoders.

关键词： parity check matrix parity check codes soft-input soft-output field programmable gate arrays implementations table lookup SISO FPGA implementations Linear algebra (numerical analysis) simplified soft Euclidean distance iterative LDPC decoder Logic circuits low complexity soft-input soft-output low-density parity-check decoders next-generation communication systems Codes LogSP iterative LDPC decoder look-up tables matrix algebra LDPC codes field programmable gate arrays error correction codes channel signal-to-noise ratio logarithmic sum-product iterative LDPC decoder SSD iterative LDPC decoder Interpolation and function approximation (numerical analysis) next generation networks Radio links and equipment iterative decoding error control codes MIMO communication

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field programmable gate arrays in space

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IEEE INSTRUMENTATION & MEASUREMENT MAGAZINE 2003年第4期6卷 42-48页

作者： Fernández-León, A Universidad Complutense of Madrid North Carolina State University

The use of field programmable gate arrays (FPGAs) in satellite and other spacecraft is on the rise. They are increasingly competitive when compared to traditional application-specific integrated circuits (ASICs). However, exposure to space radiation produces the same physical effects on both FPGAs and ASICs. How these radiation effects can translate to circuit malfunctions and how these problems can be prevented or mitigated is a complex, multifaceted issue that depends on the specific technology and the device's internal architecture. First and foremost, designers should implement a reliable ASIC/FPGA development methodology for the definition, design, verification, physical implementation and validation phases of any ASIC/FPGA to be flown as part of the spacecraft platform or critical payload. This should be contractually enforced. The European Space Agency (ESA) will continue to make available its own internal standard or any other equivalent methodology proposed by the contractor. As soon as the new ECSS standard on this subject is available, ESA will start using it as an applicable document in all projects where ASICs or FPGAs are to be developed.

关键词： field programmable gate arrays Aerospace electronics Leakage current Integrated circuit technology Protons Electron traps Application specific integrated circuits Space technology Radiation effects Design methodology

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field programmable gate arrays Based Real Time Robot Arm Inverse Kinematic Calculations and Visual Servoing

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ELECTRICA 2018年第2期18卷 143-150页

作者： Celik, Baris Ak, Ayca Topuz, Vedat Marmara Univ Sch Engn Dept Elect Elect Engn Istanbul Turkey Marmara Univ Vocat Sch Tech Sci Istanbul Turkey

Reliability and precision are very important in space, medical, and industrial robot control applications. Recently, researchers have tried to increase the reliability and precision of the robot control implementations. High precision calculation of inverse kinematic color based object recognition, and parallel robot control based on field programmable gate arrays (FPGA) are combined in the proposed system. The precision of the inverse kinematic solution is improved using the coordinate rotation digital computer (CORDIC) algorithm based on double precision floating point number format. Red, green, and blue (RGB) color space is converted to hue saturation value (HSV) color space, which is more convenient for recognizing the object in different illuminations. Moreover, to realize a smooth operation of the robot arm, a parallel pulse width modulation (PWM) generator is designed. All applications are simulated, synthesized, and loaded in a single FPGA chip, so that the reliability requirement is met. The proposed method was tested with different objects, and the results prove that the proposed inverse kinematic calculations have high precision and the color based object recognition is quite successful in finding coordinates of the objects.

关键词： Video processing robot arm control inverse kinematic CORDIC Algorithm field programmable gate arrays

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field programmable gate arrays Implementation of Dual Tree Complex Wavelet Transform 37

Field Programmable Gate Arrays Implementation of Dual Tree C...

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37th Annual International Conference of the IEEE-Engineering-in-Medicine-and-Biology-Society (EMBC)

作者： Canbay, Ferhat Levent, Vecdi Emre Serbes, Gorkem Goren, Sezer Aydin, Nizamettin Yildiz Tech Univ Dept Comp Engn Istanbul Turkey Ozyegin Univ Dept Comp Sci Istanbul Turkey Yildiz Tech Univ Dept Biomed Engn Istanbul Turkey Yeditepe Univ Dept Comp Engn Istanbul Turkey

ISBN: (纸本)9781424492701

Due to the inherent time-varying characteristics of physiological systems, most biomedical signals (BSs) are expected to have non-stationary character. Therefore, any appropriate analysis method for dealing with BSs should exhibit adjustable time-frequency (TF) resolution. The wavelet transform (WT) provides a TF representation of signals, which has good frequency resolution at low frequencies and good time resolution at high frequencies, resulting in an optimized TF resolution. Discrete wavelet transform (DWT), which is used in various medical signal processing applications such as denoising and feature extraction, is a fast and discretized algorithm for classical WT. However, the DWT has some very important drawbacks such as aliasing, lack of directionality, and shift-variance. To overcome these drawbacks, a new improved discrete transform named as Dual Tree Complex Wavelet Transform (DTCWT) can be used. Nowadays, with the improvements in embedded system technology, portable real-time medical devices are frequently used for rapid diagnosis in patients. In this study, in order to implement DTCWT algorithm in FPGAs, which can be used as real-time feature extraction or denoising operator for biomedical signals, a novel hardware architecture is proposed. In proposed architecture, DTCWT is implemented with only one adder and one multiplier. Additionally, considering the multi-channel outputs of biomedical data acquisition systems, this architecture is capable of running N channels in parallel.

关键词： adders data acquisition discrete wavelet transforms embedded systems feature extraction field programmable gate arrays medical signal processing multiplying circuits signal denoising signal resolution time-frequency analysis trees (mathematics) DTCWT algorithm biomedical data acquisition systems biomedical signals denoising operator discrete wavelet transform dual tree complex wavelet transform embedded system technology medical signal processing applications multichannel outputs physiological systems portable real-time medical devices real-time feature extraction time-frequency resolution

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field programmable gate arrays and analog implementation of BRIN for optimization problems

Field programmable gate arrays and analog implementation of ...

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IEEE International Symposium on Circuits and Systems

作者： Ng, HS Mak, ST Lam, KP Chinese Univ Hong Kong Dept Syst Engn & Engn Management Shatin Hong Kong Peoples R China

ISBN: (纸本)0780377613

The Binary Relation Inference Network (BRIN) emerges as a powerful topological network to solve various constrained optimization problems. In this paper, the BRIN solution is reviewed for the sake of reference. The analog and digital realization of BRIN is presented. For the analog implementation, we studied the BRIN solution for transitive closure problem. We used the common available integrated circuits and general minimum and maximum building blocks. The network response was discussed. The worst solution time for a general path problem was estimated. For digital implementation, field programmable gates arrays (FPGA) with million gates for BRIN solution was studied with Xilinx's System Generator. The detailed implementation is presented. The network response and the solution time are analyzed. The comparisons between both platforms are discussed.

关键词： field programmable gate arrays

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field programmable gate arrays: A cheaper way of customizing product prototypes

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IEEE Potentials 1994年第1期13卷 16-19页

作者： Bhatia, Dinesh Department of Electrical and Computer Engineering Design Automation Laboratory University of Cincinnati

Advances in VLSI technology have brought very complex digital systems onto a very small area of silicon. However, the design cycle times associated with the conventional VLSI designs have called for a technology that will support very rapid system prototyping. Also, the non-recurring engineering (NRE) costs associated with existing VLSI technologies are very high. An ideal design style should support rapid prototyping at almost no or very nominal NRE costs. FPGA is an attempt in this direction. FPGAs have a potential for matching both speed and density of mask programmed gate arrays (MPGAs). It is expected that more and more digital designs will be built on FPGAs, and FPGA based designs will outnumber the MPGA based designs in the near future. The author begins by discussing the nature of FPGAs and their architecture (with design tools). The author goes on to discuss custom computing. © 1994 IEEE.

关键词： field programmable gate arrays Prototypes Switches programmable logic arrays Logic devices Wires Costs Application specific integrated circuits Very large scale integration Integrated circuit interconnections

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