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Radiation-hardened configuration context realization for field programmable gate arrays

APPLIED OPTICS 2020年第19期59卷 5680-5686页

作者： Shinba, Hiroki Watanabe, Minoru Shizuoka Univ Grad Sch Integrated Sci & Technol 3-5-1 Johoku Hamamatsu Shizuoka 4328561 Japan

In space environments and at nuclear power plants, data can be destroyed by radiation, even data recorded on flash memories. To realize a radiation-hardened configuration context for field programmable gate arrays (FPGAs) under such radiation environments, this paper presents a proposal of a method to increase the radiation tolerance of configuration contexts used for FPGAs by introducing a holographic memory technology and a new FPGA architecture. When reading a configuration context from holographic memory, the context robustness depends on the number of bright bits on the configuration context. Our proposed method exploits that holographic memory property and uses a new FPGA architecture to fit the property to increase the radiation tolerance of configuration contexts from holographic memory. This paper presents simulation results and an experimental demonstration result. (C) 2020 Optical Society of America

关键词： field programmable gate arrays Holographic memory Holographic recording Holographic techniques Laser beams Liquid crystal modulators

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ANTIFUSE field-programmable gate arrays

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PROCEEDINGS OF THE IEEE 1993年第7期81卷 1042-1056页

作者： GREENE, J HAMDY, E BEAL, S ACTEL CORP SUNNYVALECA 94086

An antifuse is an electrically programmable two-terminal device with small area and low parasitic resistance and capacitance. field programmable gate arrays (FPGA's) using antifuses in a segmented channel routing architecture now offer the digital logic capabilities of an 8000-gate conventional gate array and system speeds of 40-60 MHz, A brief survey of antifuse technologies is provided. The antifuse technology, routing architecture, logic module, design automation, programming, testing and use of ACT(TM) antifuse FPGA's are described. Some inherent tradeoffs involving the antifuse characteristics, routing architecture and logic module are illustrated.

关键词： 40 to 60 MHz ACT PLD programming antifuse FPGAs application specific integrated circuits circuit layout CAD design automation electrically programmable two-terminal device field programmable gate arrays integrated circuit testing logic CAD logic arrays logic module logic testing network routing programming segmented channel routing architecture testing

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Low-precision DSP-based floating-point multiply-add fused for field programmable gate arrays

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IET COMPUTERS AND DIGITAL TECHNIQUES 2014年第4期8卷 187-197页

作者： Amaricai, Alexandru Boncalo, Oana Gavriliu, Constantina-Elena Univ Politehn Timisoara Dept Comp Engn Timisoara Romania

Floating-point (FP) multiply-add fused (F-1*F-2 +/- F-3) and multiply-accumulate represent the most common arithmetic operation in a wide range of applications, such as graphic processing, multimedia or FP digital signal processing (DSP). This study proposes FP multiply-add fused units for low-precision formats (IEEE 16-bit half precision or the 32-bit single precision) which rely on modern field programmable gate Array (FPGA) features such as the available integer multiply-accumulate-based support built-in the FPGA DSP blocks. These are employed as building-blocks within the mantissa data-path processing for the multiplication and the add/subtract operations. In order to use the DSP block for these operations, the alignment right shifts are performed before the multiply-add stage: a right shift on the addend, and, a right shift for one of the multiplicands. This results in efficient DSP usage;thus both cost savings and higher performance (high working frequencies and low latencies) are obtained for the multiply-add fused operation.

关键词： cost analysis SDHA gene field programmable gate arrays Building blocks shift to the right Fission products Addend PTGFR gene FLOATING POINTS Multiplication

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An efficient field programmable gate arrays based real-time implementation of smooth variable structure filter to estimate the state of charge of Li-ion battery in electric vehicle application

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IET ELECTRICAL SYSTEMS IN TRANSPORTATION 2022年第4期12卷 298-314页

作者： Jemmali, Sabeur Hamouda, Mahmoud Manai, Bilal Univ Sousse Ecole Natl Ingenieurs Sousse LATIS Lab Adv Technol & Intelligent Syst BP 264 Sousse Ernadh Sousse 4023 Tunisia

The computational efficiency is a challenging task in the real-time implementation of battery State of Charge (SoC) estimation algorithms in Electric Vehicle (EV) application. This study proposes for the first time a pure hardware architecture of a Smooth Variable Structure Filter (SVSF) to estimate the SoC of a lithium-ion battery in an EV. The proposed embedded architecture is implemented on a Xilinx Zynq-7000 field programmable gate arrays board without using any soft-core, and validated with real-time tests carried out on a 20 Ah NMC battery with nominal voltage about 3.65 V. The whole embedded architecture of the SVSF needs a reduced execution time in the range of 921 ns, and it consumes only 466 mW. The average estimation errors of the SoC and battery voltage at different temperatures are kept within 4.95% and 2.35% respectively. The successful convergence of the algorithm and the accurate results obtained in different circumstances, prove the practicability and computational efficiency of the proposed hardware architecture.

关键词： lithium-ion battery SVSF manganese compounds battery state of charge estimation algorithm NMC battery voltage power filters lithium compounds embedded architecture nickel compounds hardware architecture cobalt compounds smooth variable structure filter field programmable gate arrays electric vehicle application battery powered vehicles

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Look-up table-based digital predistorter implementation for field programmable gate arrays using long-term evolution signals with 60 MHz bandwidth

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IET SCIENCE MEASUREMENT & TECHNOLOGY 2012年第3期6卷 181-188页

作者： Kwan, A. Ghannouchi, F. M. Hammi, O. Helaoui, M. Smith, M. R. Univ Calgary Schulich Sch Engn Dept Elect & Comp Engn iRadio Lab Calgary AB T2N 1N4 Canada King Fahd Univ Petr & Minerals Dept Elect Engn Dhahran 31261 Saudi Arabia Univ Calgary Dept Radiol Calgary AB T2N 1N4 Canada

This study discusses the implementation of a digital predistorter to linearise radiofrequency (RF) power amplifiers, using input signals 60 MHz in bandwidth. The digital predistorter characterisation procedure is performed on a digital signal processor, using a memory polynomial modelling technique with QR-based recursive least squares (QR-RLS) as the extraction procedure. A multiple look-up table design for the memory polynomial predistorter is introduced, and by using fixed-point operations, reduces the processing latency considerably when compared with a floating-point-based predistorter implementation on a field programmable gate array (FPGA). Linearisation results are shown for a laterally diffused metal oxide semi-conductor (LDMOS)-based power amplifier (PA) biased in class AB operation with a three-carrier long-term evolution-time division duplex (LTE-TDD) input signal. Combining both the optimised predistortion coefficient extraction and predistorter implementation gives up to 20 dBc improvement in the adjacent channel and meets the wireless communication standard requirements.

关键词： wireless communication standard Communication switching FPGA table lookup Logic circuits Signal processing and detection long-term evolution-time division duplex memory polynomial predistorter Mobile radio systems laterally diffused metal oxide semiconductor QR-based recursive least squares bandwidth 60 MHz radiofrequency power amplifiers LTE-TDD input signal long-term evolution signals QR-RLS digital predistorter implementation field programmable gate arrays polynomials power amplifiers least squares approximations LDMOS digital signal processor look-up table Long Term Evolution Interpolation and function approximation (numerical analysis) signal processing time division multiplexing Amplifiers

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Built-in-self-test technique for diagnosis of delay faults in cluster-based field programmable gate arrays

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IET COMPUTERS AND DIGITAL TECHNIQUES 2013年第5期7卷 210-220页

作者： Das, Nachiketa Roy, Pranab Rahaman, Hafizur Bengal Engn & Sci Univ Sch VLSI Technol Sibpur India

The increased circuit complexity of field programmable gate array (FPGA) poses a major challenge in the testing of FPGAs. One of the test challenges is to detect the delay faults in high-speed circuits. Built-in-self-test (BIST) Technique is an ease solution compared with expensive automatic test equipment. In this work, a BIST structure is proposed to detect the delay faults in the various resources of the FPGA such as multiplier, digital signal processing (DSP) block, look-up tables etc. and interconnects of FPGA. The authors have also proposed a full-diagnosable BISTer structure that improves the testing efficiency of the logic BIST. The proposed BISTer structure can diagnose the faulty configurable logic block (CLB), when all the CLBs in the 2 x 3 BIST are faulty. The proposed scheme has been simulated in Xilinx Vertex FPGA, using ISE tool, Jbits3.0 API and XHWI (Xilinx HardWare Interface) and MATLAB7.0. The result shows significant improvement compared with earlier BIST methods.

关键词： built-in self test circuit complexity fault diagnosis field programmable gate arrays built-in-self-test technique delay fault diagnosis cluster-based field programmable gate arrays high-speed circuits BIST technique automatic test equipment BIST structure delay fault detection FPGA circuit complexity MATLAB7.0 Xilinx HardWare Interface XHWI Jbits3.0 API ISE tool Xilinx Vertex FPGA configurable logic block logic BIST testing efficiency full-diagnosable BISTer structure

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In-situ, real-time detector for faults in solder joint networks of operational, fully-programmed field programmable gate arrays (FPGAs)

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IEEE INSTRUMENTATION & MEASUREMENT MAGAZINE 2007年第4期10卷 32-37页

作者： Hofmeister, James P. Lall, Pradeep Graves, Russell Ridgetop Grp Inc Tucson AZ USA Auburn Univ NSF Ctr Adv Vehicle Elect Auburn AL 36849 USA Gen Dynam Corp Phoenix AZ USA

Not Available.

关键词： field programmable gate arrays Fault detection Detectors Soldering Sensor arrays Packaging Built-in self-test Testing Thermal stresses Temperature

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Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation

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IET CIRCUITS DEVICES & SYSTEMS 2013年第2期7卷 93-103页

作者： Zhai, Xiaojun Bensaali, Faycal Ramalingam, Soodamani Univ Hertfordshire Sch Engn & Technol Hatfield AL10 9AB Herts England

Number plate localisation is a very important stage in an automatic number plate recognition (ANPR) system and is computationally intensive. This study presents a low complexity with high-detection rate number plate localisation algorithm based on morphological operations together with an efficient multiplier-less architecture based on that algorithm. The proposed architecture has been successfully implemented and tested using a Mentor Graphics RC240 FPGA (field programmable gate arrays) development board equipped with a 4M-gate Xilinx Virtex-4 LX40. Two database sets sourced from the UK and Greece and including 1000 and 307 images, respectively, both with a resolution of 640 x 480, have been used for testing. Results achieved have shown that the proposed system can process an image in 4.7 ms, while achieving a 97.8% detection rate and consuming only 33% of the available area of the FPGA.

关键词： Image processing detection rate (DR) field programmable gate arrays License plates Clinical Test Result

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Using field programmable gate arrays to scale up the speed of holographic video computation

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JOURNAL OF ELECTRONIC IMAGING 2003年第3期12卷 558-566页

作者： Nwodoh, TA MIT Media Lab Cambridge MA 02139 USA

The generation of computer-generated holographic fringes for real-time holographic video (holovideo) display is very computation-intensive, requiring the development of such special systems as the Massachusetts Institute of Technology (MIT) Media Lab's "Holo-Chidi" system, which can generate and display holovideo at video rates. The Holo-Chidi system is made of two sets of cards-the set of processor cards and the set of video concentrator cards (VCCs). The processor cards are used for hologram computation, data archival/retrieval from a host system, and higher level control of the VCCs. The VCC formats compute holographic data from multiple hologram computing processor cards, converting the digital data to analog form to feed the acousto-optic modulators of the Media Lab's "MarkII" holographic display system. The generation of the holographic fringes from the 3-D numerical description of a scene takes place inside field-programmable gate arrays (FPGAs) resident in the processor card. These large FPGAs employ several superposition processing pipelines, all working in parallel to generate the fringes of the hologram frame. With nine processor boards, there are the equivalent of about 288 superposition ''processors'' generating the fringes simultaneously. A Holo-Chidi system with three VCCs has enough frame buffering capacity to hold up to 32 36-Mbyte hologram frames at a time. Precomputed holograms can also be loaded into the VCC from a host computer through the low-speed universal serial bus (USB) port. (C) 2003 SPIE and IST.

关键词： interference pattern PROCESSOR Host systems Cards digital data field programmable gate arrays Holography on line data service Videotapes

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An experimental survey of heavy ion induced dielectric rupture in Actel field programmable gate arrays (FPGAs)

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 1996年第3期43卷 967-972页

作者： Swift, G Katz, R NASA GODDARD SPACE FLIGHT CTRGREENBELTMD 20771

Irradiations and subsequent failure analyses were performed to investigate single event dielectric rupture (SEDR) in Actel FPGAs as a function of ion LET (linear energy transfer), angle, bias, temperature, feature siz... 详细信息

关键词： field programmable gate arrays Circuit testing Space technology Temperature Dielectric devices Propulsion Laboratories MOSFETs Frequency Conductors

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