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Design and implementation of digital controllers for smart structures using field programmable gate arrays

SMART MATERIALS AND STRUCTURES 1997年第5期6卷 559-572页

作者： Kelly, JS Rao, VS Pottinger, HJ Bowman, HC UNIV MISSOURI DEPT ELECT ENGN ROLLA MO 65409 USA UNIV MISSOURI INTELLIGENT SYST CTR ROLLA MO 65409 USA

Implementation issues represent an unfamiliar challenge to most control engineers, and many techniques for controller design ignore these issues outright. Consequently, the design of controllers for smart structural systems usually proceeds without regard for their eventual implementation, thus resulting either in serious performance degradation or in hardware requirements that squander power, complicate integration, and drive up cost. The level of integration assumed by the smart patch further exacerbates these difficulties, and any design inefficiency may render the realization of a single-package sensor-controller-actuator system infeasible. The goal of this research is to automate the controller implementation process and to relieve the design engineer of implementation concerns like quantization, computational efficiency, and device selection. field programmable gate arrays (FPGA) are specifically targeted as a hardware platform because these devices are highly flexible, power efficient, and reprogrammable. The current study develops an automated implementation sequence that minimizes hardware requirements while maintaining controller performance. Beginning with a state space representation of the controller, the sequence automatically generates a configuration bitstream for a suitable FPGA implementation. MATLAB functions optimize and simulate the control algorithm before translating it into the VHSIC hardware description language (VHDL). These functions improve power efficiency and simplify integration in the final implementation by performing a linear transformation that renders the controller computationally friendly. The transformation favors sparse matrices in order to reduce multiply operations and the hardware necessary to support them;simultaneously, the remaining matrix elements take on values that minimize limit cycles and parameter sensitivity. The proposed controller design methodology is implemented on a simple cantilever beam test structure using

关键词： SENSITIVITY SYSTEMS control engineering Controllers degradation of performance Hardware Platform State-space Representation field programmable gate arrays controller design Designers Computer hardware digital controller Computer algorithms Parameter sensitivity

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Low-level implementation and side-channel detection of stealthy hardware trojans on field programmable gate arrays

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IET COMPUTERS AND DIGITAL TECHNIQUES 2014年第6期8卷 246-255页

作者： Marchand, Cedric Francq, Julien Univ Lyon UMR CNRS 5516 Lab Hubert Curien St Etienne France Airbus Def & Space Cybersecur Elancourt France

Hardware Trojans (HTs) are an emerging threat for integrated circuits integrity and their applications. Trying to find efficient HT detection methods is necessary. However, before detecting them, HTs need to be created with an efficient method and their effects need to be understood. There are very few studies which describe HTs implementation methods and the methods used are not convenient for systematic study of HTs effects. The Trust-Hub website, known for hardware security in general, had published a full HT implementation tutorial, which is not completely satisfying. This study proposes a stealthy and reusable HT implementation method on field programmable gate arrays at the layout level adapted for the study of different HTs with the same non-infected circuit. Created for a systematic study of the effects brought by different HTs, the proposed approach allows designers to insert stealthy HTs inside the same circuit in order to create different realistic infected circuits. HTs implementation results on an advance encryption standard system and detection experiments based on side-channel are also presented in this study. The implementation method the authors propose can be used with scripts in order to accelerate the insertions of HTs variants.

关键词： cryptography field programmable gate arrays side-channel detection stealthy hardware trojans field programmable gate arrays integrated circuits integrity HT detection methods trust-hub Web site hardware security layout level noninfected circuit automated export system

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Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect

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IET CIRCUITS DEVICES & SYSTEMS 2009年第2期3卷 64-75页

作者： Eachempati, S. Vijaykrishnan, N. Nieuwoudt, A. Massoud, Y. Penn State Univ Dept Comp Sci & Engn University Pk PA 16802 USA Rice Univ Dept Elect & Comp Engn Houston TX 77005 USA

The authors investigate the performance and reliability of routing architectures in field programmable gate arrays (FPGA) that utilise bundles of single-walled carbon nanotubes (SWCNT) as wires in the FPGA interconnect fabric in future process technologies here. To leverage the performance advantages of nanotube-based interconnect, we explore several important aspects of the FPGA routing architecture including the wire length segmentation distribution and the switch/connection block configurations. The authors also investigate the impact of statistical variations in interconnect properties on FPGA timing yield. The results demonstrate that FPGAs utilising SWCNT bundle interconnect can achieve up to a 54% improvement in area-delay product over the best performing architecture with standard copper interconnect in 22 nm process technology. Furthermore, FPGAs implemented using SWCNT-based interconnect can provide a superior performance-yield trade-off of up to 43% over FPGAs implemented using traditional copper interconnect in future process technologies.

关键词： integrated circuit interconnections network routing single-walled carbon nanotubes nanotube devices carbon nanotube bundle interconnect FPGA timing yield C integrated circuit reliability switch-connection block configurations FPGA interconnect fabric carbon nanotubes wire length segmentation distribution field programmable gate arrays

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A system for real-time 2-D feature detection based on field programmable gate arrays

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INTEGRATED COMPUTER-AIDED ENGINEERING 2000年第3期7卷 181-191页

作者： Benedetti, A Perona, P CALTECH Div Engn & Appl Sci Pasadena CA 91125 USA

We have designed and implemented a system for real-time detection of 2-D image features on a reconfigurable computer based on field programmable gate arrays (FPGA's). We envision this device as the front-end of a system able to track image features in real-time vision applications like autonomous vehicle navigation and "structure from motion". The algorithm employed to select good features is inspired by the method of Tomasi and Kanade. Compared to the original method, the algorithm that we have devised does not require any floating point or transcendental operations, and maps efficiently into a highly pipelined architecture, well suited to be implemented in FPGA technology. We have implemented the algorithm on a low-cost reconfigurable computer equipped with video decoder and encoder interfaces. Reliable operation has been observed on an image stream generated by a standard NTSC commercial video camera at 30 Hz on different scenes and under different light conditions. This result compares favorably to the implementation of the same algorithm on a system based on the TI C80 DSP, able to process at most 5 frames/second.

关键词： REAL-time clocks (Computers) field programmable gate arrays COMPUTER algorithms

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Image and video processing platform for field programmable gate arrays using a high-level synthesis

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IET COMPUTERS AND DIGITAL TECHNIQUES 2012年第6期6卷 414-425页

作者： Desmouliers, C. Oruklu, E. Aslan, S. Saniie, J. Vallina, F. M. IIT Dept Elect & Comp Engn Chicago IL 60616 USA Texas State Univ Ingram Sch Engn San Marcos TX 78666 USA Xilinx Inc San Jose CA 95124 USA

In this study, an image and video processing platform (IVPP) based on field programmable gate array (FPGAs) is presented. This hardware/software co-design platform has been implemented on a Xilinx Virtex-5 FPGA using a high-level synthesis and can be used to realise and test complex algorithms for real-time image and video processing applications. The video interface blocks are done in Register Transfer Languages and can be configured using the MicroBlaze processor allowing the support of multiple video resolutions. The IVPP provides the required logic to easily plug-in the generated processing blocks without modifying the front-end (capturing video data) and the back-end (displaying processed output data). The IVPP can be a complete hardware solution for a broad range of real-time image/video processing applications including video encoding/decoding, surveillance, detection and recognition.

关键词： high level synthesis field programmable gate arrays Platform real image Videotapes video data Image

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A simulation tool for dynamically reconfigurable field programmable gate arrays

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1996年第3期4卷 381-390页

作者： Lysaght, P Stockwood, J Dept. of Electron. & Electr. Eng. Strathclyde Univ. Glasgow UK

The emergence of static memory-based field programmable gate arrays (FPGA's) that are capable of being dynamically reconfigured, i.e., partially reconfigured while active, has initiated research into new methods of digital systems synthesis, At present, however, there are virtually no specific CAD tools to support the design and investigation of digital systems using dynamic reconfiguration, This paper reports on an investigation of new CAD tools and the development of a new simulation technique, called dynamic circuit switching (DCS), for dynamically reconfigurable systems, The principles of DCS are presented and examples of its application are described.

关键词： Circuit Analysis Computing field programmable gate arrays Logic CAD VLSI Dynamically Reconfigurable FPGA field programmable gate arrays Simulation Tool Static Memory Based CAD Tools Dynamic Circuit Switching field programmable gate arrays Reconfigurable Logic Design Automation Circuit Simulation Distributed Control Digital Systems Circuit Synthesis Switching Circuits Digital Integrated Circuits High Level Synthesis

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Cone-based placement for field programmable gate arrays

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IET COMPUTERS AND DIGITAL TECHNIQUES 2011年第1期5卷 49-62页

作者： Banerjee, P. Saha, D. Sur-Kolay, S. Univ Calcutta Dept Comp Sci & Engn Kolkata 700009 India Indian Stat Inst Adv Comp & Microelect Unit Kolkata 700108 India

Deterministic greedy methods have been proposed to place the netlist of configurable logic blocks (CLBs) and primary input output blocks (IOBs) quickly on a two-dimensional (2D) island-style field programmable gate array (FPGA) consisting of either one or multiple 2D island-style arrays of CLBs and IOBs. The first method, 'ConeCLBPlace', starts with a random placement of the primary output blocks along the periphery of the 2D array of CLBs, then places the CLBs and primary input blocks in a greedy deterministic way. In the second method, 'ConeIOBPlace', the IOBs are first placed on the periphery of the FPGA chip using a deterministic heuristic, and then the CLBs are placed within the 2D array using a typical simulated annealing (SA) flow. The third method, 'ConePlace', combines the above two deterministic approaches by first placing the IOBs only using ConeIOBPlace, and then the CLBs using ConeCLBPlace deterministically. Finally, a low-temperature SA is executed in order to obtain a high-quality final placement. ConeCLBPlace and ConePlace produce placements 2.34x and 1.83x faster than the placement step of popular FPGA place-and-route tool VPR (versatile place and route) on the average. The bounding box costs of placement produced by ConeCLBPlace and ConePlace, after execution of the iterative SA steps, are 1.05x and 1.14x of VPR, respectively, on the average, whereas the critical path delay obtained after routing is 1.03x of VPR for both methods on the average, implying almost the same quality of VPR. This justifies the utility of the methods proposed.

关键词： multiple 2D island-style arrays primary input output blocks Logic circuits Logic and switching circuits field programmable gate arrays two-dimensional island-style field programmable gate array simulated annealing ConeIOBPlace deterministic algorithms deterministic greedy methods greedy algorithms bounding box placement costs cone-based placement configurable logic blocks

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Design and evaluation of a memristor-based look-up table for non-volatile field programmable gate arrays

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IET CIRCUITS DEVICES & SYSTEMS 2016年第4期10卷 292-300页

作者： Almurib, Haider Abbas F. Kumar, Thulasiraman Nandha Lombardi, Fabrizio Univ Nottingham Malaysia Campus Fac Engn Semenyih Selangor Malaysia Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA

This study presents the detailed design and analysis of a new memristor-based look-up table (LUT) for field programmable gate arrays (FPGAs). The proposed memory utilises memristors as storage elements with N-type metal-oxide-semiconductor transistors for row access. New WRITE and READ operations are proposed;the proposed LUT requires no additional circuit to handle the WRITE 1 (0) operation. The proposed method requires a RESTORE pulse only for the READ 0 operation. Moreover, the WRITE operation of the proposed method requires three power lines and a RESTORE pulse only for the READ 0 operation, thus saving 25% READ time when compared with previous methods. In addition, the proposed method does not require the REFRESH pulse and does not dissipate power during stand-by mode. Extensive simulation results are presented with respect to different operational features such as normalised state parameter, pulse width and LUT size. In addition to a circuit-level evaluation, the proposed LUT scheme has also been assessed with respect to FPGA implementation. Simulation results using sequential benchmarks mapped on Spartan 4 and 5 FPGAs show that the proposed non-volatile LUT outperforms existing static random access memory cell-based LUTs in terms of performance.

关键词： field programmable gate arrays memristors table lookup MOSFET sequential circuits nonvolatile field programmable gate arrays FPGA memristor-based look-up table storage elements n-type metal-oxide-semiconductor transistors WRITE operations READ operations word lines bit lines RESTORE pulse READ 0 operation circuit-level evaluation sequential benchmarks Spartan 4 nonvolatile LUT

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SEU HARDENING OF field-programmable gate arrays (FPGAS) FOR SPACE APPLICATIONS AND DEVICE CHARACTERIZATION

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 1994年第6期41卷 2179-2186页

作者： KATZ, R BARTO, R MCKERRACHER, P KOGA, R INTELSAT PALO ALTO CA 94303 USA JOHNS HOPKINS UNIV APPL PHYS LAB LAUREL MD 20723 USA AEROSP CORP EL SEGUNDO CA 90245 USA

field programmable gate arrays (FPGAs) are being used in space applications because of attractive attributes: good density, moderate speed, low cost, and quick turn-around time. However, these devices are susceptible to Single Event Upsets (SEUs). An approach using triple modular redundancy (TMR) and feedback was developed for flip-flop hardening in these devices. Test data showed excellent results for this circuit topology. Total dose and Single Event Effect (SEE) testing have been performed on recently released technologies. Failures are analyzed and test methodology is discussed.

关键词： field programmable gate arrays Costs Circuit testing Instruments Flip-flops Performance evaluation Space technology Single event upset Laboratories Failure analysis

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The impact of software and CAE tools on SEU in field programmable gate arrays

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 1999年第6期46卷 1461-1468页

作者： Katz, R Wang, J McCollum, J Cronquist, B NASA Goddard Space Flight Ctr Greenbelt MD 20771 USA Actel Corp Sunnyvale CA 94086 USA

field programmable gate array (FPGA) devices, heavily used in spacecraft electronics, have grown substantially in size over the past few years, causing designers to work at a higher conceptual level, with computer aided engineering (CAE) tools synthesizing and optimizing the logic from a description. It is shown that the use of commercial-off-the-shelf (COTS) CAE tools can produce unreliable circuit designs when the device is used in a radiation environment and a flip-flop is upset. At a lower level, software can be used to improve the SEU performance of a flip-flop, exploiting the configurable nature of FPGA technology and on-chip delay, parasitic resistive, and capacitive circuit elements.

关键词： Software tools Computer aided engineering field programmable gate arrays programmable logic arrays Circuit synthesis Flip-flops Space vehicles Aerospace electronics Design optimization Logic devices

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