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检索条件"主题词=Field programmable gate arrays"

共 41416 条记录，以下是51-60 订阅

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Multiple curve presentation and zooming processor using field programmable gate arrays

Multiple curve presentation and zooming processor using Fiel...

引用

IEEE SoutheastCon 2011 - Building Global Engineers

作者： Venkatesan, Dhushyanth Elkeelany, Omar Tennessee Technol Univ Dept Elect & Comp Engn Cookeville TN 38505 USA

ISBN: (纸本)9781612847382

This paper presents the design and implementation of a hardware graphical display custom processor for generating and manipulating plots based on a given set of time varying input signals. The paper primarily focuses on the design to generate plots of two sampled sine waves of 5 KHz and 10 KHz respectively, along with horizontal and vertical axes with proper scaling. This was achieved by designing the custom processor in Verilog HDL. A provision is made such that the plots can be zoomed horizontally and vertically, independent of each other. There are two levels of zooming provided for each signal plot, both horizontal and vertical zooming. A legend box at the top right corner of the screen was included to provide the scale details of both horizontal and vertical axes, at any level of zooming. The display of the signal plots and the different levels of zooming are controlled by switches of the field programmable gate Array (FPGA) DE2 development board. The proposed design gives a compromise solution for flexibility and reconfigurability at the hardware level.

关键词： field programmable gate arrays Zooming Horizon PLOTS hardware level PROCESSOR

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Single event effects test results for advanced field programmable gate arrays

Single event effects test results for advanced field program...

引用

IEEE Radiation Effects Data Workshop

作者： Allen, Gregory R. Swift, Gary M. CALTECH Jet Prop Lab 4800 Oak Grove Dr Pasadena CA 91109 USA

ISBN: (纸本)9781424406388

Reconfigurable field programmable gate arrays (FPGAs) from Altera and Actel and an FPGA-based quick-turn Application Specific Integrated Circuit (ASIC) from Altera were subjected to single-event testing using heavy ions. Both Altera devices (Stratix II and HardCopy II) exhibited a low latchup threshold (below an LET of 3 MeV-cm(2)/mg) and thus are not recommended for applications in the space radiation environment. The flash-based Actel ProASIC Plus device did not exhibit latchup to an effective LET of 75 MeV-cm(2)/mg at room temperature. In addition, these tests did not show flash cell charge loss (upset) or retention damage. Upset characterization of the design-level flip-flops yielded an LET threshold below 10 MeV-cm(2)/mg and a high LET cross section of about 1x10(-6) cm(2)/bit for storing ones and about 1x10(-7) cm(2)/bit for storing zeros. Thus, the ProASIC device may be suitable for critical flight applications with appropriate triple modular redundancy mitigation techniques.

关键词： field programmable gate arrays ASICs single event latchup single event upset

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Gauss-Seidel accelerated: Implementing flow solvers on field programmable gate arrays

Gauss-Seidel accelerated: Implementing flow solvers on field...

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General Meeting of the Power-Engineering-Society

作者： Chassin, David P. Armstrong, Peter R. Chavarria-Miranda, Daniel G. Guttromson, Ross T. Pacific NW Natl Lab Richland WA 99352 USA

ISBN: (纸本)9781424404926

Non-linear steady-state power flow solvers have typically relied on the Newton-Raphson method to efficiently compute solutions on today's computer systems. field programmable gate array (FPGA) devices, which have recently been integrated into high-performance computers by major computer system vendors, offer an opportunity to significantly increase the performance of power flow solvers. However, only some algorithms are suitable for an FPGA implementation. The Gauss-Seidel (GS) method of solving the AC power flow problem is an excellent example of such an opportunity. In this paper we discuss algorithmic design considerations, optimization, implementation, and performance results of the implementation of the Gauss-Seidel method running on a Silicon Graphics Inc. Altix-350 computer equipped with a Xilinx Virtex II 6000 FPGA.

关键词： power flow Gauss-Seidel method field programmable gate arrays

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Design and implementation of digital controllers for smart structures using field programmable gate arrays

Design and implementation of digital controllers for smart s...

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Conference on Smart Electronics and MEMS - Smart Structures and Materials 1997

作者： Kelly, JS Bowman, HC Rao, VS Pottinger, HJ Univ. of Missouri/Rolla (United States)

ISBN: (纸本)0819424595

Implementation issues represent an unfamiliar challenge to most control engineers, and many techniques for controller design ignore these issues outright. Consequently, the design of controllers for smart structural systems usually proceeds without regard for their eventual implementation, thus resulting either in serious performance degradation or in hardware requirements that squander power, complicate integration, and drive up cost. The level of integration assumed by the Smart Patch further exacerbates these difficulties, and any design inefficiency may render the realization of a single-package sensor-controller-actuator system infeasible. The goal of this research is to automate the controller implementation process and to relieve the design engineer of implementation concerns like quantization, computational efficiency, and device selection. We specifically target field programmable gate arrays (FPGAs) as our hardware platform because these devices are highly flexible, power efficient, and reprogrammable. The current study develops an automated implementation sequence that minimizes hardware requirements while maintaining controller performance. Beginning with a state space representation of the controller, the sequence automatically generates a configuration bitstream for a suitable FPGA implementation, MATLAB functions optimize and simulate the control algorithm before translating it into the VHSIC hardware description language (VHDL). These functions improve power efficiency and simplify integration in the final implementation by performing a linear transformation that renders the controller computationally friendly. The transformation favors sparse matrices in order to reduce multiply operations and the hardware necessary to support them;simultaneously, the remaining matrix elements take on values that minimize limit cycles and parameter sensitivity. The proposed controller design methodology is implemented on a simple cantilever beam test structure using

关键词： field programmable gate arrays Transform theory Quantization Matrices Sensors Digital signal processing Digital filtering Actuators Binary data Device simulation

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A New Coupled Metric Learning for Real-time Anomalies Detection with High-Frequency field programmable gate arrays 14

A New Coupled Metric Learning for Real-time Anomalies Detect...

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14th IEEE International Conference on Data Mining (IEEE ICDM)

作者： Jiang, Frank Luo, Dan Univ Technol Sydney Fac Engn & IT Sydney NSW 2007 Australia

ISBN: (纸本)9781479942749

Billions of internet end-users and device to device connections contribute to the significant data growth in recent years, large scale, unstructured, heterogeneous data and the corresponding complexity present challenges to the conventional real-time online fraud detection system security. With the advent of big data era, it is expected the data analytic techniques to be much faster and more efficient than ever before. Moreover, one of the challenges with many modern algorithms is that they run too slowly in software to have any practical value. This paper proposes a field programmable gate Array (FPGA) -based intrusion detection system (IDS), driven by a new coupled metric learning to discover the inter-and intra-coupling relationships against the growth of data volumes and item relationship to provide a new approach for efficient anomaly detections. This work is experimented on our previously published NetFlow-based IDS dataset, which is further processed into the categorical data for coupled metric learning purpose. The overall performance of the new hardware system has been further compared with the presence of conventional Bayesian classifier and Support Vector Machines classifier. The experimental results show the very promising performance by considering the coupled metric learning scheme in the FPGA implementation. The false alarm rate is successfully reduced down to 5% while the high detection rate (= 99.9%) is maintained.

关键词： Metric Learning field programmable gate arrays Netflow Intrusion Detection Systems

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A Handel-C implementation of the back-propagation algorithm on field programmable gate arrays

A Handel-C implementation of the back-propagation algorithm ...

引用

International Conference on Reconfigurable Computing and FPGAs

作者： Pandya, V Areibi, S Moussa, M Univ Guelph Sch Engn Guelph ON N1G 2W1 Canada

ISBN: (纸本)0769524567

General Purpose Processors (GPPs) and ASICs have traditionally been the common means for building and implementing Artificial Neural Network's (ANNs). However Such computing paradigms suffer from the constant need of establishing a trade-off between flexibility and performance Due to the technological advance in the development of progammable logic devices, field programmable gate arrays (FPGAs) have become attractive for realizing ANNs. FPGAs have shown to exhibit excellent flexibility in terms of reprogramming the same hardware and at the same time achieving good performance by enabling parallel computation. In this paper various implementations of ANNs on FPGAs are investigated and compared. The research described in this paper proposes three partially parallel architectures and a fully parallel architecture to realize the Back- Propagation algorithm on an FPGA. The proposed designs are coded in Handel-C and functionally, verified by synthesizing them on a Virtex2000e FPGA chip. The partially parallel architectures and the fully parallel architecture are found to be 2.25 and 4 times faster than the software implementation rcspectively for different benchmarks.

关键词： backpropagation field programmable gate arrays neural nets parallel architectures FPGA chip Handel-C Virtex2000e artificial neural networks back-propagation algorithm field programmable gate arrays Parallel architectures back propagation Neural network

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Clock buffer circuit soft errors in antifuse-based field programmable gate arrays

Clock buffer circuit soft errors in antifuse-based field pro...

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IEEE Nuclear and Space Radiation Effects Conference (NSREC)

作者： Wang, JJ Katz, RB Dhaoui, F McCollum, JL Wong, W Cronquist, BE Lambertson, RT Hamdy, E Kleyner, I Parker, W Actel Corp Sunnyvale CA 94086 USA NASA Goddard Space Flight Ctr Greenbelt MD 20771 USA Orbital Sci Corp Greenbelt MD 20771 USA

Three-dimensional mixed-mode device simulation is used to investigate the dock upset in an antifuse FPGA device. Two versions of the clock circuit were simulated, the original and the redesigned,vith improved SEU hardness, The threshold LET of each version was simulated both at static and during transition. Compared to the test data, the simulated results consistently underestimate the LETth. The difference between LETth at static and during transition is relatively small. This disagrees with the previous speculation that the clock upset is due to heavy-ion strikes very close to the clock edge. Efforts were also made to optimize the simulation methodology to reduce the simulation time for practicality.

关键词： field programmable gate arrays

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Supply Chain Attacks: Basic Input Output Systems (BIOS), Mux Multiplexers and field programmable gate arrays (FPGA)

Supply Chain Attacks: Basic Input Output Systems (BIOS), Mux...

引用

7th International Conference on Information Warfare and Security (ICIW)

作者： Rohret, David Willmann, Justin Computer Sciences Corporation Inc United States Dynetics Inc United States Information Operations Warfare Center/Vulnerability Assessment Team San Antonio TX United States

ISBN: (纸本)9781908272294

Cyber crimes and cyber warfare are problematic for commercial and government entities as new exploits and methods of system compromise emerge daily. Fortunately, hundreds of cyber security organizations collaborate to develop security patches and mitigations for most exploits as quickly as they are identified. One method of compromising and controlling victim machines, with little or no risk of being identified or mitigated, is the supply chain attack;specifically, altering the basic input and output system (BIOS) code to reprogram field programmable gate Array (FPGA) chips to run covert operating systems and provide undetectable communications for data exfiltration. Not only are the main board's BIOS and circuitry a target for malicious technology insertion, but more powerful graphics cards with independent processing and memory can also provide a safe haven for malicious logic. This paper identifies and demonstrates BIOS and FPGA attacks that can be implemented during the production process, allowing the developer (or attacker) to accomplish persistent covert communications and system control. The authors also discuss the results of a remote BIOS attack and the risks associated with attempting one. Lastly, efforts to identify and mitigate BIOS supply-chain attacks, are outlined to include the implementation of the Trusted Platform Module (TPM) standard, which supports hardware-based BIOS integrity checking, and changes required for production methods and processes that will enhance information assurance for critical assets.

关键词： BIOS POST supply chain attack field programmable gate arrays covert communications data exfiltration Trusted Platform Module (TPM)

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Design of Sobel Operator Using field programmable gate arrays

Design of Sobel Operator Using Field Programmable Gate Array...

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International Conference on Technological Advances in Electrical, Electronics and Computer Engineering (TAEECE)

作者： Alghurair, Dina Al-Rawi, Sefwan S. Specialist Trainer in Computer Department Higher Institute for Telecommunication and Navigation PAAET. Kuwait|c|

ISBN: (纸本)9781467356138;9781467356121

The last decade has a rapid development in the structure of a programmable processor called field programmable gate Array (FPGA), which is used to implement a hardware circuit to perform the functions for high speed application. Sobel edge detection is a method to find the edge pixels in an image. This method exploits the change in intensity with respect to neighboring pixels. This paper introduces the implementation of Sobel edge detection method in the FPGA processor [1,2]. The implementation is performed based on two FPGA families from Xilinx, Spartan and Virtex. The cost of these implementations using Spartan3 is 41.66%, Spartan6 is 70%, Virtex5 is 3.69% and Virtex6 is 3.61%. The frequency is 169.188 MHz for using Spartan3, 45.7 MHz for Spartan6, 85.060 MHz for Virtex5 and 65.8 MHz for Virtex6.

关键词： edge detection field programmable gate arrays

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field programmable gate arrays and analog implementation of BRIN for optimization problems

Field programmable gate arrays and analog implementation of ...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： H.S. Ng S.T. Mak K.P. Lam Department of Systems Engineering and Engineering Management Chinese University of Hong Kong New Territories Hong Kong China

The binary relation inference network (BRIN) emerges as a powerful topological network to solve various constrained optimization problems. In this paper, the BRIN solution is reviewed for the sake of reference. The analog and digital realization of BRIN is presented. For the analog implementation, we studied the BRIN solution for the transitive closure problem. We used commonly available integrated circuits and general minimum and maximum building blocks. The network response was discussed. The worst solution time for a general path problem was estimated. For a digital implementation of the BRIN solution, field programmable gates arrays (FPGA) with millions of gates, were studied with Xilinx's system generator. The detailed implementation is presented. The network response and the solution time are analyzed and the comparisons between both platforms are discussed.

关键词： field programmable analog arrays field programmable gate arrays Inference algorithms Parallel processing Operational amplifiers Circuits Minimax techniques Computer networks Concurrent computing DNA computing

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