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检索条件"主题词=Field programmable gate arrays"

共 41522 条记录，以下是71-80 订阅

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Evolutionary Digital Circuit Design with Fast Candidate Solution Establishment in field programmable gate arrays

Evolutionary Digital Circuit Design with Fast Candidate Solu...

引用

IEEE International Conference on Evolvable Systems (ICES)

作者： Dobai, Roland Glette, Kyrre Torresen, Jim Sekanina, Lukas Brno Univ Technol Fac Informat Technol CS-61090 Brno Czech Republic Univ Oslo Dept Informat N-0316 Oslo Norway

ISBN: (纸本)9781479944798

field programmable gate arrays (FPGAs) are a popular platform for evolving digital circuits. FPGAs allow to be reconfigured partially which provides a natural way of establishing candidate solutions. Recent research focuses on the hardware implementation of evolutionary design platforms. Several approaches have been developed for effective establishment and evaluation of candidate solutions in FPGAs. In this paper a new mutation operator is proposed for evolutionary algorithms. The chromosome representing the candidate solution is mutated in such a way that only one configuration frame is required for establishing the mutated candidate solution in hardware. The experimental results confirm that the reduced number of configuration frames and mutations at lower level of granularity ensure faster evolution, generation of more candidate solutions in a given time as well as solutions with better quality.

关键词： evolutionary computation field programmable gate arrays integrated circuit design FPGA chromosome configuration frame evolutionary algorithm evolutionary digital circuit design fast candidate solution establishment field programmable gate array granularity level hardware implementation mutation operator Biological cells Digital circuits field programmable gate arrays Sociology Statistics Table lookup Training field programmable gate arrays Feasible Solution evolutionary algorithm digital circuits Table lookup cytology integrated circuit design Sociology Chromosomes Training Functional training

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Reconfigurable processing with field programmable gate arrays

Reconfigurable processing with field programmable gate array...

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International Conference on Application-Specific Systems, Architectures and Processors

作者： Fawcett, BK Watson, J XILINX INC SAN JOSECA 95124

ISBN: (纸本)081867542X

In-system-programmable, SRAM-based field programmable gate arrays (FPGAs) can be used to create processors and coprocessors whose internal architecture as well as interconnections can be reconfigured to match the needs of a given application. Exploiting the inherent speed and parallelism of a hardware solution, FPGA-based coprocessors can execute computationally-intensive tasks while maintaining the flexibility of a programmable solution. The successes of this approach have led to the introduction of the first FPGA devices designed for coprocessing applications; the XC6200 FPGA architecture features an SRAM control store, abundant registers, on-chip memory capability, support for high-speed full or partial reconfiguration, and a flexible, hierarchical routing scheme.

关键词： field programmable gate arrays Coprocessors parallelism PROCESSOR configurability

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Multivariable controller implementation using field programmable gate arrays

Multivariable controller implementation using field programm...

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SPIE Conference on Smart Electronics and MEMS

作者： Rao, VS Pottinger, H Kelly, JS Yuan, LF Varadharajan, S Univ Missouri Rolla MO 65401 USA

ISBN: (纸本)0819427721

Implementation issues represent an unfamiliar challenge to most control engineers, and many techniques for controller design ignore these issues outright. Consequently, the design of controllers for smart structural systems usually proceeds without regard for their eventual implementation, thus resulting either in serious performance degradation or in hardware requirements that squander power, complicate integration, and drive up cost. This paper summarizes previously reported results in the application of FPGAs to the realization of digital controllers for smart structures and reports ongoing effort to extend these results to multiple input, multiple output systems.

关键词： field programmable gate arrays Logic Digital signal processing MATLAB Smart structures Binary data Device simulation Clocks Mathematical modeling Matrices

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field programmable gate arrays get enough speed and density for computer applications

Field programmable gate arrays get enough speed and density ...

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IEEE Compcon

作者： W. Patterson XILINX INC. San Jose CA USA

At the time of their introduction in 1985, field-programmable gate arrays (FPGAs) offered limited speed and logic density. Subsequent advances in architecture and process have resulted in major improvements in speed and logic density. Projections for further improvements in speed, density, and cost can be developed on the basis of anticipated improvements in architectures and process. These advances will result in a narrowing of the differences between conventional custom gate arrays and FPGAs. The topics covered are evolution of FPGA architectures, process advances for FPGAs, speed, density, cost, software, markets, and applications.< >

关键词： field programmable gate arrays Computer applications programmable logic arrays Application software Logic devices Computer architecture Costs EPROM Random access memory Testing

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A practical cut-based physical retiming algorithm for field programmable gate arrays 05

A practical cut-based physical retiming algorithm for field ...

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10th Asia and South Pacific Design Automation Conference

作者： Suaris, Peter Wang, Dongsheng Chou, Nan-Chi Mentor Graph Corp Wilsonville OR 97007 USA

ISBN: (纸本)0780387368

This paper presents a heuristic cut-based retiming algorithm for FPGA designs. It handles complex retiming constraints including timing, architectural and structural constraints;improves retimeability by incorporating logic resynthesis;and efficiently integrates with incremental placement. Thus, the algorithm improves timing compliance by allowing groups of registers to be rapidly retimed across blocks of combinational logic in the physical domain without violating any complex constraints. Experiments have shown that this algorithm can improve the performance of FPGA designs by 16% on average, while achieving a 61.7% speedup in terms of runtime compared with classic retiming algorithms.

关键词： field programmable gate arrays Timing Algorithm design and analysis Registers Constraint optimization Delay effects Integrated circuit interconnections Clocks programmable logic arrays Graphics

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A grayscale skin and facial detection mechanism for use in conjunction with security system technology via graphical block methodologies on field programmable gate arrays

A grayscale skin and facial detection mechanism for use in c...

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Conference on Visual Information Processing XVII

作者： Tickle, Andrew J. Smith, Jeremy S. Wu, Q. Henry Univ Liverpool Dept Elect Engn & Elect Liverpool L69 3GJ Merseyside England

ISBN: (纸本)9780819471697

Presented in this paper is the design of a skin filter which unlike many systems already developed for use, this system will not use RGB or HSI colour but an 8-bit greyscale instead. This is done in order to make the system more convenient to employ on an FPGA, to increase the speed to better enable real-time imaging and to make it easier to combine with the previously designed binary based algorithms. This paper will discuss the many approaches and methods that could be considered such as Bayes format and thresholds, pixel extraction, mathematical morphological strings, edge detection or a combination of the previous and a discussion about which provided the best performance. The research for this skin filter was carried out in two stages, firstly on people who had an ethnic origin of White - British, Asian or Asian British, Chinese and Mixed White and Asian. The second phase which won't be included here in great detail will cover the same principles for the other ethnic backgrounds of Black or Black British - Caribbean or Africa, Other Black background, Asian or Asian British - Indian. Pakistani or Bangladeshi. This is due to the fact that we have to modify the parameters that govern the detection process to account for greyscale changes in the skin tone, texture and intensity;however the same principles would still be applied for general detection and integration into the previous algorithm. The latter is discussed and, what benefits it will give.

关键词： facial detection texture analysis pixel extraction eye nose ratio field programmable gate arrays VHDL altera DSP builder

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field programmable gate arrays control based photovoltaic energy management

Field programmable gate arrays control based photovoltaic en...

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IEEE Students' Conference on Electrical, Electronics and Computer Science (SCEECS)

作者： Mohammad Meraj Alam Eric Escande Julie Szmigiel Victor Wilk Department of Electrical Engineering IIT DELHI New Delhi India ENSE3 Grenoble INP Grenoble France

This paper presents hardware implementation of PV module for photovoltaic (PV) applications by using buck converter, battery, electronic card and FPGA Board. The goal of the project was to control the chopper in order to be able to charge a battery and feed a load with energy from that battery and/or the solar panel, and display all the significant signals. Therefore it was necessary to make a hardware card using current transducers and an algorithm implementation on an FPGA. The control algorithm and coding for integration with the PV cell is proposed by means of the VHDL code and implemented using Xilinx Spartan-3 from Digilent (NEXYS-2) FPGA Board. In this work, a hardware implementation of electronic card interface and open loop control with rotary encoder as a reference input in a PV system has been developed. This has all been done, and the whole project works, including the control of the chopper and displaying the values of the currents and voltages. It is better to control the chopper in closed loop instead of the open loop system that we used. This way it is possible to make sure that the solar panels works in its optimal power point, by using an MPPT. The Developed hardware has the merits of easy programming in VHDL with high accuracy even with low resolution ADC which are utilized in microcontroller and dSPACE. The proposed technique has been described through detailed experimental work.

关键词： field programmable gate arrays Batteries Hardware Voltage measurement Photovoltaic systems Choppers (circuits)

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Integrated retiming and placement for field programmable gate arrays 02

Integrated retiming and placement for field programmable gat...

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FPGA 2002: Tenth ACM International Symposium on field-programmable gate arrays

作者： Singh, Deshanand P. Brown, Stephen D. Dept. of Elec. and Computer Eng. University of Toronto Toronto Ont. Canada

ISBN: (纸本)9781581134520

Retiming is a synchronous circuit transformation that can optimize the delay of a synchronous circuit by moving registers across combinational circuit elements. The combinational structure remains unchanged and the observable behavior of the circuit is identical to the original. In this paper, we address the problem of applying retiming techniques to circuits implemented in field programmable gate arrays (FPGAs). FPGAs contain prefabricated and configurable routing elements that allow us to easily implement a variety of circuits. However this interconnect contributes greatly to the overall delay in the implemented circuit. If a circuit is retimed prior to the placement and routing phases of the CAD flow, then it has no information about the delays introduced by the configurable interconnect. Our fundamental experiment is to determine whether there are any gains in tightly coupling retiming and placement so that the retiming algorithm has some estimate of the routing delays. Specifically, we introduce a post-placement retiming algorithm that understands how to take advantage of FPGA architectural features. This retiming algorithm may introduce extra registers into the circuit. These new registers need to be placed in some location in the FPGA. Retiming register placement is accomplished by a novel incremental clustering and placement algorithm. The incremental algorithm builds upon the placement of the non-retimed circuit to intelligently sift in the newly-introduced registers. In addition, we explore making the placement algorithms "retiming aware." These placement algorithms try to place logic blocks in such a way that the subsequent retiming produces better speed results. These techniques include the identification of retiming-critical cycles during placement. Our experiments show that the integration of retiming with placement results in 19% better clock periods in comparison to the application of retiming before the place and route steps.

关键词： field programmable gate arrays

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Use of field programmable gate arrays for reusable interfaces

Use of field programmable gate arrays for reusable interface...

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IEEE Systems Readines Technology Conference -Future Sustainment for military and Aerospace (AUTOTESTCON 2000)

作者： Stong, Nathan Ogden Air Logistics Cent Hill Air Force Base United States

Historically, whenever a unique digital interface was needed, a unique piece of hardware was created. In the field of program loaders/verifiers this often led to large, heavy and expensive equipment to support aircraft platforms such as the F-16 and F-15. field programmable gate arrays (FPGAs) can be used to create many different interfaces without the need for unique hardware. This paper will explore the techniques used to develop interfaces using FPGAs and provide examples of how FPGAs have reduced the size, weight and cost of flight line test equipment over the last 9 years. New uses of FPGAs for future applications are explored, showing additional benefits and further cost savings. FPGAs may also be used to implement some standard interfaces such as IEEE-488, RS-422 and PC parallel ports. The benefits and risk of using FPGAs for these standard interfaces are evaluated.

关键词： field programmable gate arrays

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An analysis of single event upset dependencies on high frequency and architectural implementations within Actel RTAX-S family field programmable gate arrays

An analysis of single event upset dependencies on high frequ...

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作者： Berg, Melanie Wang, Jih-Jong Ladbury, Ray Buchner, Steve Kim, Hak Howard, Jim LaBel, Ken Phan, Anthony Irwin, Tim Friendlich, Mark MEI Technology Inc. c/o NASA Goddard Space Flight Center Building 22 Greenbelt MD 20771 United States Actel Technology Development Actel Corporation Mountain View CA 94043 United States NASA Goddard Space Flight Center Code 561.4 Greenbelt MD 20770 United States QSS c/o NASA Goddard Space Flight Center Code 561.4 Greenbelt MD 20770 United States MEI Technology Inc. c/o NASA Goddard Space Flight Center Code 561.4 Greenbelt MD 20770 United States

In order to investigate frequency and architectural effects on Single Event Upset cross sections within RTAX-S FPGA devices, a novel approach to high speed testing is implemented. Testing was performed at variable spe... 详细信息

关键词： field programmable gate arrays

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