检索结果-内蒙古大学图书馆

A High-End Reconfigurable Computation Platform for Nuclear and Particle Physics Experiments

COMPUTING IN SCIENCE & ENGINEERING 2011年第2期13卷 52-63页

作者： Liu, Ming Kuehn, Wolfgang Lange, Soeren Yang, Shuo Roskoss, Johannes Lu, Zhonghai Jantsch, Axel Wang, Qiang Xu, Hao Jin, Dapeng Liu, Zhen'an Univ Giessen FPGAs Giessen Germany Royal Inst Technol Dept Elect Syst Stockholm Sweden Chinese Acad Sci Inst High Energy Phys Beijing Peoples R China Inst High Energy Phys Expt Phys Ctr Beijing 100039 Peoples R China

A high-performance computation platform based on field-programmable gate arrays targets nuclear and particle physics experiment applications. The system can be constructed or scaled into a supercomputer-equivalent size for detector data processing by inserting compute nodes into advanced telecommunications computing architecture (ATCA) crates. Among the case study results are that one ATCA crate can provide a computation capability equivalent to hundreds of commodity PCs for Hades online particle track reconstruction and Cherenkov ring recognition.

关键词： ATCA crates Cherenkov counters Cherenkov ring recognition FPGA implementation Hades online particle track reconstruction Reconfigurable computing advanced telecommunications computing architecture crates commodity PC computation capability compute nodes detector data processing field programmable gate arrays field-programmable gate arrays high energy physics instrumentation computing high-end reconfigurable computation platform high-performance computation platform nuclear and particle physics nuclear physics nuclear physics experiments particle physics experiments particle tracks pattern recognition reconfigurable architectures scientific computing supercomputer-equivalent size

来源：评论

学校读者我要写书评

暂无评论

Modular Design of Fully Pipelined Reduction Circuits on FPGAs

引用

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2013年第9期24卷 1818-1826页

作者： Huang, Miaoqing Andrews, David Univ Arkansas Dept Comp Sci & Comp Engn Fayetteville AR 72701 USA

Fast and efficient reduction circuits are critical for a broad range of scientific and embedded system applications. High throughput reduction circuits are typically hand designed for specific vector lengths. These circuits need to be modified when the set lengths are changed. In this paper, we present a new design approach that can handle any set length or combination of different consecutive set lengths without stalling and generates in-order results. The flexibility of the design allows it to be used for any reduction operations, such as floating-point addition and multiplication. By providing a simple and efficient interface to the user and a modular architecture for the designer, the proposed technique has a broad impact across a wide range of custom hardware designs.

关键词： Fully pipelined reduction circuits accumulator field-programmable gate arrays modular design digital_circuits

来源：评论

学校读者我要写书评

暂无评论

A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2018年第7期65卷 2196-2209页

作者： Khaleghi, Behnam Asadi, Hossein Sharif Univ Technol Dept Comp Engn Data Storage Networks & Proc DSN Lab Tehran 111558639 Iran Sharif Univ Technol Dept Comp Engn Tehran 111558639 Iran

Despite the considerable effort has been put on the application of Non-Volatile Memories (NVMs) in field-programmable gate arrays FPGAs, previously suggested designs are not mature enough to substitute the state of-the-art SRAM-based counterparts mainly due to the inefficient building blocks and/or the overhead of programming structure which can impair their potential benefits. In this paper, we present a Resistive Random Access Memory RRAM-based FPGA architecture employing efficient Switch Box (SB) and Look-Up Table (LUT) designs with programming circuitry integrated in both SB and LUT designs that creates area and power efficient programmable components while precluding performance overhead to these blocks. In addition, we present an efficient scheme to load the configuration bitstream into the memory elements, which makes the configuration time comparable to that of SRAM-based FPGAs. Besides, we investigate the correct functionality and reliability of the programming structure subject to fluctuations in attributes of RRAM cells. Using Versatile Place and Route (VTR) tool with the obtained characteristics of the proposed blocks demonstrate that the average area and delay of the proposed FPGA architecture are 59.4% and 20.1% less than conventional SRAM-based FPGAs. Compared with a recent RRAM-based architecture, the proposed architecture improves the area and power by 49.7% and 33.8% while keeps the delay intact.

关键词： Emerging non-volatile memory resistive random access memory field-programmable gate arrays programming circuitry resistive fluctuation

来源：评论

学校读者我要写书评

暂无评论

CUTE Mote, A Customizable and Trustable End-Device for the Internet of Things

引用

IEEE SENSORS JOURNAL 2017年第20期17卷 6816-6824页

作者： Gomes, Tiago Salgado, Filipe Tavares, Adriano Cabral, Jorge Univ Minho Ctr ALGORITMI P-4800058 Guimaraes Portugal

The ubiquitous connectivity of the low-end devices in the Internet of Things (IoT) brings new challenges over the traditional wireless sensor networks' architectures. Such challenges require not only security and privacy-related features, but also solutions to handle the ever-growing amount of data transferred over the network. However, performing such tasks on resource constrained devices is not straightforward. The need for energy-efficient devices, while preserving their performance and security capabilities, requires new solutions at the architectural level of the wireless device. This paper proposes a heterogeneous architecture that targets low-end and resource constrained IoT devices, combining a hardcore microcontroller unit (MCU) and a reconfigurable computing unit (RCU) with an IEEE 802.15.4 radio transceiver. The MCU hosts an embedded operating system with an IoT-enabled network stack, and exploits the available field-programmable gate array technology to implement the RCU and to deploy customized sensing-and network-related accelerators, offloading heavy, and/or complex software tasks to dedicated hardware blocks. The customizable and trustable end-device mote was implemented using the proposed architecture and the achieved results demonstrates the benefits, both in terms of performance and energy, of accelerating network-related tasks in always-connected resource constrained IoT devices.

关键词： Accelerator architectures heterogeneous networks Internet of Things field-programmable gate arrays wireless sensor networks

来源：评论

学校读者我要写书评

暂无评论

Mining Discriminative K-Mers in DNA Sequences Using Sketches and Hardware Acceleration

引用

IEEE ACCESS 2020年 8卷 114715-114732页

作者： Saavedra, Antonio Lehnert, Hans Hernandez, Cecilia Carvajal, Gonzalo Figueroa, Miguel Tech Univ Berlin Embedded Syst Architecture Grp D-10587 Berlin Germany Univ Tecn Federico Santa Maria Dept Elect Valparaiso 2390123 Chile Univ Concepcion Dept Comp Sci Concepcion 4030000 Chile Ctr Biotechnol & Bioengn CeBiB Santiago 8370456 Chile Univ Concepcion Dept Elect Engn Concepcion 4030000 Chile

Extracting discriminative k-mers is an important and challenging problem in DNA sequence analysis with applications in metagenomics and motif discovery. Despite the availability of multiple computational tools designed for this purpose, most discriminative k-mer discovery methods suffer from long execution times and high memory usage when processing large datasets. This paper presents a novel approach for discriminative k-mer discovery in DNA sequences, which leverages streaming and sketch algorithms to reduce space complexity and expose data parallelism, enabling the use of parallel platforms for accelerating the execution of computationally-intensive operations. To assess the performance of our method, we designed and implemented two versions of the algorithm that leverage parallelization at different levels: (i) a software version tailored for multithreading and vector instructions in commodity CPUs, and (ii) a custom architecture implemented on a field-programmable gate Array (FPGA) accelerator that exploits fine-grain parallelism and deep pipelining on reconfigurable logic. Experimental results show that, when mining discriminative k-mers from a set of well-known ChIP-seq sequences, our parallel software implementation executes at least 15% faster than exact-counting tools, and requires at least five times less memory when processing large datasets. More importantly, we designed a custom FPGA-based accelerator for our algorithm on a Xilinx KCU1500 board, which achieves speedups above 78x with the largest datasets, compared to our parallel software implementation. The accelerator uses less than 3% of the logic resources available on the on-board XCKU115 Kintex-7 Ultrascale FPGA, and between 12% and 70% of the memory resources, depending on the size of the dataset.

关键词： Discriminative k-mers heavy hitters counting sketches parallel processing hardware acceleration field-programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Real-time computing platform for spiking neurons (RT-Spike)

引用

IEEE TRANSACTIONS ON NEURAL NETWORKS 2006年第4期17卷 1050-1063页

作者： Ros, Eduardo Ortigosa, Eva M. Agis, Rodrigo Carrillo, Richard Arnold, Michael Univ Granada Dept Comp Architecture & Technol E-18071 Granada Spain CNL Salk Inst Biol Studies La Jolla CA 92037 USA

A computing platform is described for simulating arbitrary networks of spiking neurons in real time. A hybrid computing scheme is adopted that uses both software and hardware components to manage the tradeoff between flexibility and computational power;the neuron model is implemented in hardware and the network model and the learning are implemented in software. The incremental transition of the software components into hardware is supported. We focus on a spike response model (SRM) for a neuron where the synapses are modeled as input-driven conductances. The temporal dynamics of the synaptic integration process are modeled with a synaptic time constant that results in a gradual injection of charge. This type of model is computationally expensive and is not easily amenable to existing software-based event-driven approaches. As an alternative we have designed an efficient time-based computing architecture in hardware, where the different stages of the neuron model are processed in parallel. Further improvements occur by computing multiple neurons in parallel using multiple processing units. This design is tested using reconfigurable hardware and its scalability and performance evaluated. Our overall goal is to investigate biologically realistic models for the real-time control of robots operating within closed action-perception loops, and so we evaluate the performance of the system on simulating a model of the cerebellum where the emulation of the temporal dynamics of the synaptic integration process is important.

关键词： field-programmable gate arrays pipeline processing real time system spiking neural network hardware

来源：评论

学校读者我要写书评

暂无评论

G-AETCAM: gate-Based Area-Efficient Ternary Content-Addressable Memory on FPGA

引用

IEEE ACCESS 2017年 5卷 20785-20790页

作者： Irfan, Muhammad Ullah, Zahid CECOS Univ IT & Emerging Sci Dept Elect Engn Peshawar 25100 Pakistan

This paper presents a novel architecture for ternary content-addressable memory (TCAM), using G-AETCAM cells, which outputs the address of the provided input data. The proposed architecture is a matrix of G-AETCAM cells arranged in the form of rows and columns using flip-flop as a memory element and a control logic circuitry consisting of logic gates. One G-AETCAM cell encodes the input and stored bit into one encoded bit which results in a match-line after passing from the AND-gate-array. Many architectures configure random-access memory (RAM) available on FPGAs as content-addressable storage architecture but are efficient for specific size and deal with data only in ascending or descending order while the proposed architecture provides freedom in size with no chance of making a single memory cell as useless and can store ternary data in any order. RAM-based TCAMs require pre-processing for the storage of TCAM words while the proposed design does not involve any pre-processing. The proposed architecture reduces the transistor count by a factor of 25.55, as compared with the RAM-based TCAM, which ultimately reduces area and increases the speed of operations. The proposed architecture is successfully implemented on Xilinx Virtex-6 FPGA for the size 64 x 36 and achieves a speed of 358 MHz.

关键词： Content-addressable storage field-programmable gate arrays flip-flops logic gates memory RAM-based TCAM

来源：评论

学校读者我要写书评

暂无评论

Characterization and parameterized generation of synthetic combinational benchmark circuits

引用

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1998年第10期17卷 985-996页

作者： Hutton, MD Rose, J Grossman, JP Corneil, DG Altera Corp San Jose CA 95134 USA Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada Univ Toronto Dept Comp Sci Toronto ON M5S 3G4 Canada

The development of new field-programmed, mask-programmed, and laser-programmed gate-array architectures is hampered by the lack of realistic test circuits that exercise both the architectures and their automatic placement and routing algorithms. In this paper, we present a method and a tool for generating parameterized and realistic synthetic circuits. To obtain the realism, we propose a set of graph-theoretic characteristics that describe a physical netlist, and have built a tool that can measure these characteristics on existing circuits. The generation tool uses the characteristics as constraints in the synthetic circuit generation. To validate the quality of the generated netlists, parameters that are not specified in the generation are compared with those of real circuits and with those of more "random" graphs.

关键词： algorithms design automation field-programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multi-casting interconnection architecture

引用

MICROPROCESSORS AND MICROSYSTEMS 2004年第5-6期28卷 341-350页

作者： Kwon, YS Kyung, CM Korea Adv Inst Sci & Technol CHiPS VLSI Syst Lab Taejon 305701 South Korea

The gate utilization of FPGAs and speed of emulation in multi-FPGA system are limited by the interconnection architecture and the number of pins. The time-multiplexing of interconnection wires is required for multi-FPGA systems incorporating several state-of-the-art FPGAs. This article proposes a circuit partitioning algorithm called SCheduling driven Algorithm for TOMi (SCATOMi) for multi-FPGA systems with interconnection architecture called Time-multiplexed, Off chip, Multi-casting interconnection (TOMi). SCATOMi improves the performance of the TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Experiments on architecture comparison show that, by adopting the proposed TOMi interconnection architecture along with SCATOMi, the pin count is reduced to 15.2-81.3% while the critical path delay is reduced to 46.1-67.6% compared to traditional architectures. (C) 2004 Elsevier B.V. All rights reserved.

关键词： field-programmable gate arrays interconnection architecture time-multiplexing scheduling

来源：评论

学校读者我要写书评

暂无评论

Real-Time Finite-Element Simulation of Electromagnetic Transients of Transformer on FPGA

引用

IEEE TRANSACTIONS ON POWER DELIVERY 2018年第4期33卷 1991-2001页

作者： Liu, Peng Dinavahi, Venkata Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2R3 Canada

The computation of the electromagnetic transients in a power transformer with nonlinear material using the finite element method (FEM) is so dense that the traditional nonlinear solver employing the Newton-Raphson method can hardly execute in real time. In this paper, we emulate the finite-element computation of electromagnetic transients of a transformer in real time for the first time. The transmission line modeling (TLM) method employed in the FEM successfully decoupled the nonlinear elements from the linear network so the nonlinearities could he solved individually, which is perfect for parallel processing. The parallelism of the TLM-FE solution is sufficiently explored and realized on a field-programmable gate array with deep data pipelining, and the implementation can execute in real time and provide detailed field information of the transformer during the transients. The proposed noniterative field-circuit coupling enabled the transformer to interface with an external network and the comparison with commercial FEM software proved the accuracy and computational efficiency of the real-time FE model.

关键词： Electromagnetic transients field-programmable gate arrays field-circuit coupling finite element method parallel processing power transformer real-time systems transmission line modeling

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：