检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

191 册 图书
166 篇 期刊文献
82 篇 会议
11 篇 学位论文
2 篇 科技报告

馆藏范围

452 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

239 篇 工学
- 170 篇 电气工程
- 155 篇 计算机科学与技术...
- 41 篇 信息与通信工程
- 28 篇 软件工程
- 17 篇 仪器科学与技术
- 16 篇 电子科学与技术（可...
- 13 篇 控制科学与工程
- 7 篇 核科学与技术
- 5 篇 石油与天然气工程
- 3 篇 机械工程
- 3 篇 材料科学与工程（可...
- 3 篇 交通运输工程
- 3 篇 生物医学工程（可授...
- 2 篇 光学工程
- 2 篇 动力工程及工程热...
- 2 篇 测绘科学与技术
- 2 篇 环境科学与工程（可...
- 1 篇 力学（可授工学、理...
- 1 篇 化学工程与技术
- 1 篇 航空宇航科学与技...
23 篇 理学
- 18 篇 物理学
- 4 篇 数学
- 2 篇 化学
- 2 篇 天文学
- 2 篇 生物学
7 篇 医学
- 7 篇 临床医学
- 1 篇 特种医学
6 篇 管理学
- 5 篇 管理科学与工程(可...
1 篇 法学
- 1 篇 法学
1 篇 教育学
- 1 篇 教育学

主题

452 篇 field-programmab...
191 篇 nasa technical r...
191 篇 (ntrs)
39 篇 reports
28 篇 field programmab...
27 篇 algorithms
26 篇 single event ups...
23 篇 real time operat...
20 篇 signal processin...
20 篇 application spec...
18 篇 hardware descrip...
18 篇 integrated circu...
18 篇 design
17 篇 computer program...
17 篇 systems engineer...
15 篇 fpgas
15 篇 label, kenneth a...
15 篇 reconfigurable h...
15 篇 hardware
15 篇 microprocessors

机构

8 篇 univ toronto dep...
5 篇 univ concepcion ...
3 篇 univ british col...
3 篇 ryerson univ dep...
3 篇 univ alberta dep...
2 篇 princeton univ d...
2 篇 sharif univ tech...
2 篇 ati technol thor...
2 篇 univ concepcion ...
2 篇 ist nazl fis nuc...
2 篇 kumamoto univ gr...
2 篇 univ calif los a...
2 篇 xilinx toronto d...
2 篇 ctr biotechnol &...
2 篇 univ pisa dipart...
2 篇 aristo technol i...
2 篇 ctr biotechnol &...
2 篇 university of to...
2 篇 univ pisa dipart...
2 篇 nagoya inst tech...

作者

9 篇 figueroa miguel
5 篇 wilton steven j....
5 篇 dinavahi venkata
5 篇 hernandez cecili...
4 篇 anderson jason h...
4 篇 soto javier e.
4 篇 ye andy
4 篇 hernandez alvaro
4 篇 rose j
3 篇 asadi hossein
3 篇 irfan muhammad
2 篇 pietri m
2 篇 knodel oliver
2 篇 mateos raul
2 篇 delbem alexandre...
2 篇 mehmood shahid
2 篇 chung k
2 篇 jadhav shrikant ...
2 篇 fernandez yaime
2 篇 chow p

语言

439 篇 英文
9 篇 其他
3 篇 中文
1 篇 德文

检索条件"主题词=Field-Programmable Gate Arrays"

共 452 条记录，以下是101-110 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Learning accelerator of deep neural networks with logarithmic quantization 7

Learning accelerator of deep neural networks with logarithmi...

引用

7th IIAI International Congress on Advanced Applied Informatics (IIAI-AAI)

作者： Ueki, Takeo Iwai, Keisuke Matsubara, Takashi Kurokawa, Takakazu Natl Def Acad Japan Dept Comp Sci Yokosuka Kanagawa Japan

ISBN: (纸本)9781538674475

In recent years, Deep Neural Network (DNN)s have become widely spread. Several high-throughput hardware implementations for DNNs have been proposed. One of the key points for hardware implementations of DNNs is to reduce their circuit scale because DNNs require a lot of product-sum operations. Previous papers presented some accelerators using logarithmic quantization to reduce circuit scale by replacing multipliers with shifters. However, most of them are implemented only for inference, and we can find no previous paper using logarithmic quantization for learning. In this paper, a learning accelerator using a logarithmic quantization is proposed. The accelerator uses a stochastic approach for logarithmic quantization. It enables DNNs to learn using logarithmic quantization values. Preliminary evaluation confirmed that DNNs using the proposed method can achieve recognition of MNIST with an accuracy of 97.8%. This evaluation result proves that the proposed method can be used for learning DNNs. The accelerator using the proposed method is implemented on a field-programmable gate array (FPGA) (Xilinx Zynq7020) and synthesized with Xilinx Vivado 2017.1. As a result, it is confirmed to have 2.9 times smaller circuit scale compared with the same FPGA accelerator using 32-bit fixed point number.

关键词： neural networks logarithmic computation approximate computing field-programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Implementing Propositional Networks on FPGA 31th

Implementing Propositional Networks on FPGA

引用

31st Australasian Joint Conference on Artificial Intelligence (AI)

作者： Siwek, Cezary Kowalski, Jakub Sironi, Chiara F. Winands, Mark H. M. Univ Wroclaw Fac Math & Comp Sci Inst Comp Sci Wroclaw Poland Maastricht Univ Dept Data Sci & Knowledge Engn Games & AI Grp Maastricht Netherlands

ISBN: (纸本)9783030039912;9783030039905

The speed of game rules processing plays an essential role in the performance of a General Game Playing (GGP) agent. Propositional Networks (propnets) are an example of a highly efficient representation of game rules. So far, in GGP, only software implementations of propnets have been proposed and investigated. In this paper, we present the first implementation of propnets on field-programmable gate arrays (FPGAs), showing that they perform between 25 and 58 times faster than a software-propnet for most of the tested games. We also integrate the FPGA-propnet within an MCTS agent, discussing the challenges of the process, and possible solutions for the identified shortcomings.

关键词： General Game Playing field-programmable gate arrays Propositional Networks Monte Carlo Tree Search

来源：评论

学校读者我要写书评

暂无评论

Burst-Mode FEC Performance for PON Upstream Channels with EDFA Optical Transients 22

Burst-Mode FEC Performance for PON Upstream Channels with ED...

引用

International Conference on Optical Network Design and Modeling (ONDM)

作者： Brandonisio, Nicola Carey, Daniel Porto, Stefano Talli, Giuseppe Townsend, Paul D. Univ Coll Tyndall Natl Inst Cork Ireland

ISBN: (纸本)9783903176072

The performance of forward error correction (FEC) based on Reed-Solomon coding is analyzed experimentally for a burst-mode upstream channel within a passive optical network (PON) testbed. During this analysis, the upstream FEC performance is impaired by inducing correlated and localized errors within the burst through the injection of optical transients. These transients emulate the optical signal variation associated with the add-and-drop events of wavelength channels within a long-reach optical link based on a chain of erbium doped fiber amplifiers (EDFAs). The robustness of the FEC has been analyzed by measuring the post-FEC bit error rate (BER) as a function of the amplitude of the emulated transients and their delay with respect to the transmitted bursts. A margin of approximately 4dB is demonstrated for the transient amplitude before the FEC degradation. Furthermore, while the post-FEC BER is strongly degraded by the emulated transients, the pre-FEC BER stays below the FEC threshold, demonstrating the importance of measuring the post-FEC BER in order to correctly characterize the FEC performance in PON upstream channels affected by optical transients.

关键词： forward error correction passive optical networks burst-mode transmission field-programmable gate arrays erbium doped fiber amplifiers optical transients

来源：评论

学校读者我要写书评

暂无评论

FPGA-based Real-Time Super-Resolution System for Ultra High Definition Videos 26

FPGA-based Real-Time Super-Resolution System for Ultra High ...

引用

26th IEEE Annual International Symposium on field-programmable Custom Computing Machines (FCCM)

作者： He, Zhuolun Huang, Hanxian Jiang, Ming Bai, Yuanchao Luo, Guojie Peking Univ Ctr Energy Efficient Comp & Applicat Beijing 100871 Peoples R China Peking Univ Sch Math Sci Dept Informat Sci Beijing 100871 Peoples R China Peking Univ Sch Elect Engn & Comp Sci Beijing 100871 Peoples R China

ISBN: (纸本)9781538655221

The market benefits from a barrage of Ultra High Definition (Ultra-HD) displays, yet most extant cameras are barely equipped with Full-HD video capturing. In order to upgrade existing videos without extra storage costs, we propose an FPGA-based super-resolution system that enables real-time Ultra-HD upscaling in high quality. Our super-resolution system crops each frame into blocks, measures their total variation values, and dispatches them accordingly to a neural network or an interpolation module for upscaling. This approach balances the FPGA resource utilization, the attainable frame rate, and the image quality. Evaluations demonstrate that the proposed system achieves superior performance in both throughput and reconstruction quality, comparing to current approaches.

关键词： field-programmable gate arrays Ultra High Definition Super-Resolution Real-time

来源：评论

学校读者我要写书评

暂无评论

AutoRARE: An Automated Tool For Generating FPGA-Based Multi-Memory Hardware Accelerators For Compute-Intensive Applications 37

AutoRARE: An Automated Tool For Generating FPGA-Based Multi-...

引用

37th IEEE International Performance Computing and Communications Conference (IPCCC)

作者： Jadhav, Shrikant S. Gloster, Clay Doss, Christopher Kim, Youngsoo Naher, Jannatun North Carolina A&T State Univ Dept Elect & Comp Engn Greensboro NC 27401 USA North Carolina A&T State Univ Dept Comp Syst Technol Greensboro NC USA Bradley Univ Dept Elect & Comp Engn Peoria IL 61625 USA

ISBN: (纸本)9781538668085

In this paper, we present AutoRARE, a Java-based automated design tool for generating field programmable gate Array (FPGA)-based hardware accelerators. AutoRARE automatically generates all VHDL models needed to build/synthesize a processor specifically tailored for each application. The user needs only provide the VHDL description of a special-purpose floating point Arithmetic Logic Unit (ALU) or function core. The tool generates the VHDL description for the memory interface, memory controller, host processor interface, and the application specific processor. We also present details of the FPGA-based multi-memory hardware accelerator for accelerating computationally intensive applications, generated using AutoRARE. The multi-memory hardware accelerator is highly pipelined and able to simultaneously read and write multiple floating point values from multiple memories. The multi-memory architecture is the key to providing hardware accelerators that execute 10X-100X faster than typical multi-core processors. The Taylor Series expansion of the sine/cosine function is used as an application to demonstrate the merits of the multi-memory hardware accelerator. In our experiments, we executed the Taylor Series in software and compared execution times with an FPGA-based hardware implementation. Our experiments show that the FPGA-based multi-memory Taylor Series hardware accelerator is 481X faster than software executing the Taylor Series on a typical server.

关键词： Reconfigurable Computing field-programmable gate arrays field-programmable Custom Computing Machines High Performance Computing Multi-Memory Architecture Multiple Memory Banks

来源：评论

学校读者我要写书评

暂无评论

Real Time Photon-Counting Receiver for High Photon Efficiency Optical Communications

Real Time Photon-Counting Receiver for High Photon Efficienc...

引用

作者： Vyhnalek, Brian E.(NASA Glenn Research Center, Cleveland, OH, United States) Nappier, Jennifer M.(NASA Glenn Research Center, Cleveland, OH, United States) Tedder, Sarah A.(NASA Glenn Research Center, Cleveland, OH, United States) IEEE International Conference on Space Optical Systems and Applications October 14 2019 - October 16 2019 Portland OR United States

We present a scalable design for a photon-counting ground receiver based on superconducting nanowire single photon detectors (SNSPDs) and field programmable gate array (FPGA) real-time processing for applications to space-to-ground photon starved links, such as the Orion EM-2 Optical Communication Demonstration (O2O), and future deep space or low transmitter power missions. The receiver is designed to receive a serially concatenated pulse position modulation (SCPPM) waveform, which follows the Consultative Committee for Space Data Systems (CCSDS) Optical Communications Coding and Synchronization Red Book standard. The receiver design uses multiple individually fiber coupled, 80% detection efficiency commercial SNSPDs in parallel to scale to a required data rate, and is capable of achieving data rates up to 528 Mbps. For efficient fiber coupling from the telescope to the array of parallel detectors that can be scaled both to telescope aperture size and the number of detectors, we use either a single mode fiber (SMF) photonic lantern or a few-mode fiber (FMF) photonic lantern. In this paper we give an overview of the receiver system design, the characteristics of the photonic lanterns, the performance of the SNSPDs, and system level tests. We show that 40 Mbps can be received using a single SNSPD, and discuss aspects for scaling to higher data rates.

关键词： Aerospace systems Cost effectiveness Real time operation Space communication Superconductivity Systems engineering Transmitter receivers Cryogenic temperature Deep space Design analysis Extremely high frequencies Fiber optics field-programmable gate arrays Optical communication Photons

来源：评论

学校读者我要写书评

暂无评论

Can DSP48A1 Adders be used for High-Resolution Delay Generation? 7

Can DSP48A1 Adders be used for High-Resolution Delay Generat...

引用

7th Mediterranean Conference on Embedded Computing (MECO)

作者： Tancock, Scott Arabul, Ekin Dahnoun, Naim Mehmood, Shahid Univ Bristol Sch Comp Sci Elect Engn & Engn Math Bristol Avon England Quaid I Azam Univ Islamabad Pakistan

ISBN: (纸本)9781538656839

Time to digital conversion is an important task in many systems. It involves the conversion of time-based signals (as opposed to the amplitude-based signals in analog-to-digital conversion) into digital numbers so that a purely digital system may process them. This is widely used in rangefinders, all-digital phase-locked loops and quantum experiments. In order to obtain high-resolution time-to-digital conversion, the generation of small delays is necessary. This paper examines the viability of using the DSP48A1 blocks present on Xilinx FPGAs to generate these small delays, and ultimately concludes they are unsuitable in isolation due to the high differential non-linearity, but may be suitable as a semi-fine stage of a multi-stage TDC or when combined in an equivalent coding line.

关键词： Time-to-Digital Converters field-programmable gate arrays Xilinx Digital Signal Processing Delay Generation

来源：评论

学校读者我要写书评

暂无评论

Towards Compilation of an Imperative Language for FPGAs 10

Towards Compilation of an Imperative Language for FPGAs

引用

10th ACM SIGPLAN International Workshop on Virtual Machines and Language Implementations (VMIL)

作者： Pauget, Baptiste Pearce, David J. Potanin, Alex Ecole Normale Super Dept Informat Paris France Victoria Univ Wellington Engn & Comp Sci Wellington New Zealand

ISBN: (纸本)9781450360715

field-programmable gate arrays (FPGA's) have been around since the early 1980s and have now achieved relatively widespread use. For example, FPGAs are routinely used for high-performance computing, financial applications, seismic modelling, DNA sequence alignment, software defined networking and, occasionally, are even found in smartphones. And yet, despite their success, there still remains something of a gap between programming languages and circuit designs for an FPGA. We consider the compilation of an imperative programming language, Whiley, to VHDL for use on an FPGA. A key challenge lies in splitting an arbitrary function into a series of pipeline stages, as necessary to expose as much task parallelism as possible. To do this, we introduce a language construct which gives the programmer control over how the pipeline is constructed.

关键词： field-programmable gate arrays Compilers Hardware Description Languages

来源：评论

学校读者我要写书评

暂无评论

Optical Software Defined Radio Transmitter Extinction Ratio Enhancement with Differential Pulse Carving

Optical Software Defined Radio Transmitter Extinction Ratio ...

引用

作者： Lantz, N. C Nappier, J. M Vyhnalek, B. E Tedder, S. A NASA Glenn Research Center International Society for Optical Engineering

A unique challenge in the development of a deep space optical software defined radio (SDR) transmitter is the optimization of the extinction ratio (ER). For a Mars to Earth optical link, an ER approaching 40dB may be necessary. However, a high ER can be difficult to achieve at the low PPM orders and narrow slot widths required for high data rates. The quality of the digital signal transmitted by the SDR does not meet the amplitude and timing characteristics needed by an analog optical modulator. The conflicting implementation constraints of these two fundamentally different systems, the digital SDR and analog optical modulator, can make achieving the required ER very difficult. In this paper, the causes of fidelity loss at the interface between the SDR and optical modulator are discussed. The SDR signal quality requirements are derived and explored. It is shown that increasing the SDR signal quality enough to meet these requirements is impractical to implement due to bandwidth limitations of electronic components as well as field programmable gate Array (FPGA) clock speed constraints. A novel optical modulation architecture based on low-voltage differential signaling and dual Mach-Zehnder modulators is presented which reduces the signal quality requirements on the SDR and increases the system ER.

关键词： Bandwidth Deep space field-programmable gate arrays Modulators Optical communication Pulse position modulation Radio transmitters

来源：评论

学校读者我要写书评

暂无评论

Impact of Initialization on gate-based Area Efficient Ternary Content-Addressable Memory 1

Impact of Initialization on Gate-based Area Efficient Ternar...

引用

1st IEEE International Conference on Computing, Electronics and Communications Engineering (iCCECE)

作者： Irfan, Muhammad Ahmad, Aftab CECOS Univ IT & Emerging Sci Dept Elect Engn Peshawar Pakistan Univ Sci & Technol Dept Elect Engn Bannu Pakistan

ISBN: (纸本)9781538649046

Ternary content-addressable memory gives an address at the output after searching for the word that is provided at the input. The word ternary means that the said memory is capable of storing 'X' which represents the presence of '1' as well as '0'. gate-based area efficient TCAM (G-AETCAM) uses flip-flops as storing media in the form of storing as well as masking element. These flip-flops are millions in number in the latest FPGA devices and are used only 1% in implementing G-AETCAM of size 64x36. In this paper, we have initialized the flip-flops to some binary value ('1' or '0'). Technically, these flip-flops are made SET when we want to initialize it by '1' and are made CLEAR if we need to store '0' in the corresponding storing or masking element. The said algorithm of initialization is implemented successfully on Xilinx Virtex-6 FPGA for 64 x 36 configuration which resulted in 3.45% decrease in power consumption and 0.83% increase in speed of the whole architecture.

关键词： Flip-flops field-programmable gate arrays memory content-addressable storage ternary content-addressable storage

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共46页 << < 7 8 9 10 11 12 13 14 15 16 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：