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A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2018年第7期65卷 2196-2209页

作者： Khaleghi, Behnam Asadi, Hossein Sharif Univ Technol Dept Comp Engn Data Storage Networks & Proc DSN Lab Tehran 111558639 Iran Sharif Univ Technol Dept Comp Engn Tehran 111558639 Iran

Despite the considerable effort has been put on the application of Non-Volatile Memories (NVMs) in field-programmable gate arrays FPGAs, previously suggested designs are not mature enough to substitute the state of-the-art SRAM-based counterparts mainly due to the inefficient building blocks and/or the overhead of programming structure which can impair their potential benefits. In this paper, we present a Resistive Random Access Memory RRAM-based FPGA architecture employing efficient Switch Box (SB) and Look-Up Table (LUT) designs with programming circuitry integrated in both SB and LUT designs that creates area and power efficient programmable components while precluding performance overhead to these blocks. In addition, we present an efficient scheme to load the configuration bitstream into the memory elements, which makes the configuration time comparable to that of SRAM-based FPGAs. Besides, we investigate the correct functionality and reliability of the programming structure subject to fluctuations in attributes of RRAM cells. Using Versatile Place and Route (VTR) tool with the obtained characteristics of the proposed blocks demonstrate that the average area and delay of the proposed FPGA architecture are 59.4% and 20.1% less than conventional SRAM-based FPGAs. Compared with a recent RRAM-based architecture, the proposed architecture improves the area and power by 49.7% and 33.8% while keeps the delay intact.

关键词： Emerging non-volatile memory resistive random access memory field-programmable gate arrays programming circuitry resistive fluctuation

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CUTE Mote, A Customizable and Trustable End-Device for the Internet of Things

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IEEE SENSORS JOURNAL 2017年第20期17卷 6816-6824页

作者： Gomes, Tiago Salgado, Filipe Tavares, Adriano Cabral, Jorge Univ Minho Ctr ALGORITMI P-4800058 Guimaraes Portugal

The ubiquitous connectivity of the low-end devices in the Internet of Things (IoT) brings new challenges over the traditional wireless sensor networks' architectures. Such challenges require not only security and privacy-related features, but also solutions to handle the ever-growing amount of data transferred over the network. However, performing such tasks on resource constrained devices is not straightforward. The need for energy-efficient devices, while preserving their performance and security capabilities, requires new solutions at the architectural level of the wireless device. This paper proposes a heterogeneous architecture that targets low-end and resource constrained IoT devices, combining a hardcore microcontroller unit (MCU) and a reconfigurable computing unit (RCU) with an IEEE 802.15.4 radio transceiver. The MCU hosts an embedded operating system with an IoT-enabled network stack, and exploits the available field-programmable gate array technology to implement the RCU and to deploy customized sensing-and network-related accelerators, offloading heavy, and/or complex software tasks to dedicated hardware blocks. The customizable and trustable end-device mote was implemented using the proposed architecture and the achieved results demonstrates the benefits, both in terms of performance and energy, of accelerating network-related tasks in always-connected resource constrained IoT devices.

关键词： Accelerator architectures heterogeneous networks Internet of Things field-programmable gate arrays wireless sensor networks

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G-AETCAM: gate-Based Area-Efficient Ternary Content-Addressable Memory on FPGA

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IEEE ACCESS 2017年 5卷 20785-20790页

作者： Irfan, Muhammad Ullah, Zahid CECOS Univ IT & Emerging Sci Dept Elect Engn Peshawar 25100 Pakistan

This paper presents a novel architecture for ternary content-addressable memory (TCAM), using G-AETCAM cells, which outputs the address of the provided input data. The proposed architecture is a matrix of G-AETCAM cells arranged in the form of rows and columns using flip-flop as a memory element and a control logic circuitry consisting of logic gates. One G-AETCAM cell encodes the input and stored bit into one encoded bit which results in a match-line after passing from the AND-gate-array. Many architectures configure random-access memory (RAM) available on FPGAs as content-addressable storage architecture but are efficient for specific size and deal with data only in ascending or descending order while the proposed architecture provides freedom in size with no chance of making a single memory cell as useless and can store ternary data in any order. RAM-based TCAMs require pre-processing for the storage of TCAM words while the proposed design does not involve any pre-processing. The proposed architecture reduces the transistor count by a factor of 25.55, as compared with the RAM-based TCAM, which ultimately reduces area and increases the speed of operations. The proposed architecture is successfully implemented on Xilinx Virtex-6 FPGA for the size 64 x 36 and achieves a speed of 358 MHz.

关键词： Content-addressable storage field-programmable gate arrays flip-flops logic gates memory RAM-based TCAM

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Mining Discriminative K-Mers in DNA Sequences Using Sketches and Hardware Acceleration

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IEEE ACCESS 2020年 8卷 114715-114732页

作者： Saavedra, Antonio Lehnert, Hans Hernandez, Cecilia Carvajal, Gonzalo Figueroa, Miguel Tech Univ Berlin Embedded Syst Architecture Grp D-10587 Berlin Germany Univ Tecn Federico Santa Maria Dept Elect Valparaiso 2390123 Chile Univ Concepcion Dept Comp Sci Concepcion 4030000 Chile Ctr Biotechnol & Bioengn CeBiB Santiago 8370456 Chile Univ Concepcion Dept Elect Engn Concepcion 4030000 Chile

Extracting discriminative k-mers is an important and challenging problem in DNA sequence analysis with applications in metagenomics and motif discovery. Despite the availability of multiple computational tools designed for this purpose, most discriminative k-mer discovery methods suffer from long execution times and high memory usage when processing large datasets. This paper presents a novel approach for discriminative k-mer discovery in DNA sequences, which leverages streaming and sketch algorithms to reduce space complexity and expose data parallelism, enabling the use of parallel platforms for accelerating the execution of computationally-intensive operations. To assess the performance of our method, we designed and implemented two versions of the algorithm that leverage parallelization at different levels: (i) a software version tailored for multithreading and vector instructions in commodity CPUs, and (ii) a custom architecture implemented on a field-programmable gate Array (FPGA) accelerator that exploits fine-grain parallelism and deep pipelining on reconfigurable logic. Experimental results show that, when mining discriminative k-mers from a set of well-known ChIP-seq sequences, our parallel software implementation executes at least 15% faster than exact-counting tools, and requires at least five times less memory when processing large datasets. More importantly, we designed a custom FPGA-based accelerator for our algorithm on a Xilinx KCU1500 board, which achieves speedups above 78x with the largest datasets, compared to our parallel software implementation. The accelerator uses less than 3% of the logic resources available on the on-board XCKU115 Kintex-7 Ultrascale FPGA, and between 12% and 70% of the memory resources, depending on the size of the dataset.

关键词： Discriminative k-mers heavy hitters counting sketches parallel processing hardware acceleration field-programmable gate arrays

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Characterization and parameterized generation of synthetic combinational benchmark circuits

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1998年第10期17卷 985-996页

作者： Hutton, MD Rose, J Grossman, JP Corneil, DG Altera Corp San Jose CA 95134 USA Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada Univ Toronto Dept Comp Sci Toronto ON M5S 3G4 Canada

The development of new field-programmed, mask-programmed, and laser-programmed gate-array architectures is hampered by the lack of realistic test circuits that exercise both the architectures and their automatic placement and routing algorithms. In this paper, we present a method and a tool for generating parameterized and realistic synthetic circuits. To obtain the realism, we propose a set of graph-theoretic characteristics that describe a physical netlist, and have built a tool that can measure these characteristics on existing circuits. The generation tool uses the characteristics as constraints in the synthetic circuit generation. To validate the quality of the generated netlists, parameters that are not specified in the generation are compared with those of real circuits and with those of more "random" graphs.

关键词： algorithms design automation field-programmable gate arrays

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Acceleration of EM-Based 3D CT Reconstruction Using FPGA

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IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 2016年第3期10卷 754-767页

作者： Choi, Young-kyu Cong, Jason Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90095 USA

Reducing radiation doses is one of the key concerns in computed tomography (CT) based 3D reconstruction. Although iterative methods such as the expectation maximization (EM) algorithm can be used to address this issue, applying this algorithm to practice is difficult due to the long execution time. Our goal is to decrease this long execution time to an order of a few minutes, so that low-dose 3D reconstruction can be performed even in time-critical events. In this paper we introduce a novel parallel scheme that takes advantage of numerous block RAMs on field-programmable gate arrays (FPGAs). Also, an external memory bandwidth reduction strategy is presented to reuse both the sinogram and the voxel intensity. Moreover, a customized processing engine based on the FPGA is presented to increase overall throughput while reducing the logic consumption. Finally, a hardware and software flow is proposed to quickly construct a design for various CT machines. The complete reconstruction system is implemented on an FPGA-based server-class node. Experiments on actual patient data show that a 26.9 speedup can be achieved over a 16-thread multicore CPU implementation.

关键词： Accelerator architectures computed tomography field-programmable gate arrays parallel architectures ray tracing

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LegUp: An Open-Source High-Level Synthesis Tool for FPGA-Based Processor/Accelerator Systems

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ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 2013年第2期13卷 1–27页

作者： Canis, Andrew Choi, Jongsok Aldham, Mark Zhang, Victor Kammoona, Ahmed Czajkowski, Tomasz Brown, Stephen D. Anderson, Jason H. Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada Altera Toronto Technol Ctr Toronto ON M5S 1S4 Canada

It is generally accepted that a custom hardware implementation of a set of computations will provide superior speed and energy efficiency relative to a software implementation. However, the cost and difficulty of hardware design is often prohibitive, and consequently, a software approach is used for most applications. In this article, we introduce a new high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C program as input and automatically compiles the program to a hybrid architecture containing an FPGA-based MIPS soft processor and custom hardware accelerators that communicate through a standard bus interface. In the hybrid processor/accelerator architecture, program segments that are unsuitable for hardware implementation can execute in software on the processor. LegUp can synthesize most of the C language to hardware, including fixed-sized multidimensional arrays, structs, global variables, and pointer arithmetic. Results show that the tool produces hardware solutions of comparable quality to a commercial high-level synthesis tool. We also give results demonstrating the ability of the tool to explore the hardware/software codesign space by varying the amount of a program that runs in software versus hardware. LegUp, along with a set of benchmark C programs, is open source and freely downloadable, providing a powerful platform that can be leveraged for new research on a wide range of high-level synthesis topics.

关键词： Design Algorithms High-level synthesis field-programmable gate arrays FPGAs synthesis performance power hardware/software codesign

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Long-Range Pulse Interactions in Unclocked FPGAs

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IEEE ACCESS 2023年 11卷 41158-41166页

作者： Cohen, Seth D. Fendley, Casey M. Beal, Aubrey N. Corron, Ned J. Kratos SRE Inc Birmingham AL 35211 USA Univ Alabama Huntsville Dept Elect & Comp Engn Huntsville AL 35899 USA

Evidence of long-range interactions between logic transitions in unclocked FPGA circuits is reported. The relative positions of pulses traveling in digital feedback loops are observed to dynamically interact and move to equal spacing over long timescales. We confirm the presence of this interaction over different FPGA supply voltages and hypothesize the pulse interactions are due to current draw in the power distribution network of the FPGA. This pulse interaction effect is observed for different FPGA families and manufacturers, including Altera and Xilinx, and has been tested using both look-up table (LUT) and carry chain (CC) logic to realize the feedback delays.

关键词： field programmable gate arrays Feedback loop Delays Transient analysis Steady-state Couplings Table lookup Asynchronous circuits feedback circuits field-programmable gate arrays pulse circuits pulse interactions non-blocking delay lines oscillators network dynamics transient analysis

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Nonlinear Behavioral Modeling and Real-Time Simulation of Electric Propulsion System for the High-Fidelity X-in-the-Loop Applications

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IEEE TRANSACTIONS ON TRANSPORTATION ELECTRIFICATION 2023年第1期9卷 1708-1722页

作者： Bai, Hao Li, Qian Luo, Huan Huangfu, Yigeng Gao, Fei Northwestern Polytech Univ Sch Automat Xian 710072 Peoples R China Univ Bourgogne Franche Comte Franche Comte Elect Mech Thermal Sci & Opt Sci & Univ Technol Belft Montbeliard UTBM French Natl Ctr Sci Res CNRS F-90010 Belfort France Xian Univ Sci & Technol Sch Mat Sci & Engn Xian 710054 Peoples R China

The electric propulsion system (EPS) is an important enabling technology for electrified transportation. The short time-to-market of such a system relies on real-time simulation (RTS)-based efficient X-in-the-loop testing. To ensure high fidelity, the RTS should include the detailed behavior as much as possible while complying with the constraints of the model computing time. Therefore, a nonlinear behavioral real-time modeling approach is proposed for the EPS in this article, including the adaptive curve-fitting (ACF)-based device-level power electronics model and the nonlinear flux-linkage-based spatial harmonic (FLSH) PMSM model. The real-time models are designed and implemented on the NI FLEXRIO FPGA module. Ultralow RTS latencies are realized for the ACF power converter model and the FLSH PMSM model, which are 25 and 160 ns, respectively. The simulation accuracies are consistent with the off-line simulation tools. Moreover, the ACF model and the FLSH model are used in the RTS of a fuel cell electric vehicle (FCEV) EPS together with the generic fuel cell model, the battery model, and the vehicle dynamic motion model. The RTS results prove that the proposed EPS real-time model is an excellent candidate for RTS applications.

关键词： Computational modeling Integrated circuit modeling Transient analysis Real-time systems Switches Adaptation models Biological system modeling field-programmable gate arrays modeling power electronics real-time system simulation

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Real-Time Finite-Element Simulation of Electromagnetic Transients of Transformer on FPGA

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IEEE TRANSACTIONS ON POWER DELIVERY 2018年第4期33卷 1991-2001页

作者： Liu, Peng Dinavahi, Venkata Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2R3 Canada

The computation of the electromagnetic transients in a power transformer with nonlinear material using the finite element method (FEM) is so dense that the traditional nonlinear solver employing the Newton-Raphson method can hardly execute in real time. In this paper, we emulate the finite-element computation of electromagnetic transients of a transformer in real time for the first time. The transmission line modeling (TLM) method employed in the FEM successfully decoupled the nonlinear elements from the linear network so the nonlinearities could he solved individually, which is perfect for parallel processing. The parallelism of the TLM-FE solution is sufficiently explored and realized on a field-programmable gate array with deep data pipelining, and the implementation can execute in real time and provide detailed field information of the transformer during the transients. The proposed noniterative field-circuit coupling enabled the transformer to interface with an external network and the comparison with commercial FEM software proved the accuracy and computational efficiency of the real-time FE model.

关键词： Electromagnetic transients field-programmable gate arrays field-circuit coupling finite element method parallel processing power transformer real-time systems transmission line modeling

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