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Improved digital tachometer with reduced sensitivity to sensor nonideality

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2000年第4期47卷 890-897页

作者： Kavanagh, RC Natl Univ Ireland Univ Coll Cork Dept Elect & Elect Engn Cork Ireland

A constant sample-time digital tachometer, similar to Ohmae's "M/T" method, is described. This system is capable of accurate determination of shaft velocity, based on the outputs of an incremental encoder. Previous error analyses of such devices which consider only the asynchronous nature of counter operation are shown to be specious. It is highlighted that sensor nonidealities, including variations in the transition locations from their nominal values and phasing errors between encoder channels, can produce much larger tachometer errors. An estimate is made of the actual rms output error, based on a simple encoder model and simplified analysis. It is shown that the error can be significantly reduced by operating four sub-circuits in parallel, each dealing with either a low-to-high or high-to-low transition of a single incremental encoder signal. A field-programmable-gate-array/digital-signal-processor-based practical implementation is described. Both simulation and experimental results are presented which confirm the utility of the enhanced digital tachometer.

关键词： digital measurements field-programmable gate arrays optical transducers optical velocity measurement quantization servo systems tachometers

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Development of a customized processor architecture for accelerating genetic algorithms

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MICROPROCESSORS AND MICROSYSTEMS 2007年第5期31卷 347-359页

作者： Kavvadias, Nikolaos Giannakopoulou, Vasiliki Nikolaidis, Spirldon Aristotle Univ Thessaloniki Sect Elect & Comp Dept Phys Thessaloniki 54124 Greece

In this paper, a new programmable RISC processor architecture named VGP-I is proposed, aiming to the acceleration of genetic algorithms in embedded systems. Compared to other GA engines, the VGP-I specification defines a compact instruction set supporting multiple operator types, with scalable instruction encodings, prograrnmer-visible and auxiliary registers and optional extensions. Apart from the programmable accelerator approach, VGP-I instructions have been tightly integrated to the Nios II soft-core processor as well. For performance assessment, a cycle-accurate reference VGP-I model has been developed while VGP-I subsets have been realized on a prototype microarchitecture and as Nios 11 custom instructions, both verified on programmable logic. Performance improvements on the execution of genetic operators are typically at the level of two orders of magnitude with application kernels written in ANSI C being accelerated by about 20x due to the usage of GA instruction set extensions. (c) 2007 Elsevier B.V. All rights reserved.

关键词： embedded systems field-programmable gate arrays genetic algorithms application-specific processors hardware description languages

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Real-time digital hardware simulation of power electronics and drives

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IEEE TRANSACTIONS ON POWER DELIVERY 2007年第2期22卷 1235-1246页

作者： Parma, Gustavo G. Dinavahi, Venkata Univ Fed Minas Gerais Dept Elect BR-3009210 Belo Horizonte MG Brazil Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2V4 Canada

This gaper presents a digital hardware realization of a real-time simulator for a complete induction machine drive using a field-programmable gate array (FPGA) as the computational engine. The simulator was developed using Very High Speed Integrated Circuit Hardware Description Language (VHDL), making it flexible and portable. A novel device-characteristic based model suitable for FPGA implementation has been proposed for the 2-level 6-pulse IGBT-based voltage-source converter (VSC). The VSC model is computed at a fixed time-step of 12.5 ns allowing a highly detailed and precise accounting of gating signals. The simulator also models a squirrel cage induction machine, a direct field-oriented control system, a space-vector pulse-width modulation scheme (SVPWM) and a measurement system. A multirate simulation of the system shows the slow (machine) as well as the fast (VSC and control) dynamic components. Real time simulation results under steady-state and transient conditions demonstrate modeling accuracy and efficiency.

关键词： field-programmable gate arrays induction motor drives pulse-width-modulated power converters real-time systems

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Frequency Estimation Using a Genetic Algorithm With Regularization Implemented in FPGAs

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IEEE TRANSACTIONS ON SMART GRID 2012年第3期3卷 1353-1361页

作者： Coury, Denis V. Delbem, Alexandre C. B. de Carvalho, Janison Rodrigues Oleskovicz, Mario Simoes, Eduardo V. Barbosa, Daniel da Silva, Tiago V. Univ Sao Paulo Engn Sch Sao Carlos Dept Elect Engn Sao Carlos SP Brazil Univ Sao Paulo Inst Math & Comp Sci Sao Carlos SP Brazil Univ Salvador Salvador BA Brazil Univ Fed Bahia Salvador BA Brazil

This paper proposes an accurate and precise genetic algorithm(GA) for frequency estimation of electrical power system (EPS) signals. The problem of estimating the frequency of a distorted electrical signal is modeled as an optimization problem. A regularization technique is used to guide the GA to a plausible solution from a practical point of view when the signal has significant output distortions. In this approach, the GA using regularization (GAR) enables the balanced investigation of a number of potential solutions, largely exploring the search space from one side, and weighing the suitable solutions according to practical purposes from the other side. The GAR is programmed in a field-programmable gate array (FPGA) device. This is made possible due to 1) the implicit parallelism of FPGAs in computing their instructions and 2) the suitable choice of steps of GARs to explore this parallelism. To evaluate the performance of the proposed method, an EPS was simulated having typical operation conditions. The relatively high robustness exhibited by the GAR to harmonics and noise makes it a promising equipment in the challenge of construction of smart power grids.

关键词： Digital relaying field-programmable gate arrays frequency estimation genetic algorithms power system protection

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Fast placement approaches for FPGAs

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2002年第2期7卷 284-305页

作者： Tessier, R Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA

Recent trends in FPGA development indicate a strong shift toward design reuse through the use of intellectual property (IP). This design shift has motivated the development of Frontier, a timing-driven FPGA placement system that uses design macroblocks in conjunction with a series of placement algorithms to achieve highly routable and high-performance layouts quickly. In the first stage of design placement, a macro-based floorplanner is used to quickly identify an initial layout based on intermacro connectivity. Next, FPGA routability and performance metrics are used to evaluate the quality of the initial placement. Finally, if the floorplan is determined to be insufficient from a routability or performance standpoint, a feedback-driven placement perturbation step is employed to achieve a lower cost placement. For a collection of large reconfigurable computing benchmark circuits our timing-driven placement system exhibits a 2.6 x speedup in combined place and route time versus commercial FPGA CAD software with improved design performance for most designs. It is shown that floorplanning, placement evaluation, and backend optimization are all necessary to achieve high-performance placement solutions.

关键词： computer-aided design of VLSI field-programmable gate arrays layout synthesis

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High-Sampling Rate Dynamic Inversion-Filter Realization and Applications in Digital Control

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IEEE-ASME TRANSACTIONS ON MECHATRONICS 2014年第1期19卷 238-248页

作者： Chang, Herrick L. Tsao, Tsu-Chin Univ Calif Los Angeles Dept Mech & Aerosp Engn Los Angeles CA 90095 USA

This paper presents a stable inversion of nonminimum phase systems with highly efficient computation for high-sampling rate applications. The stable filter that inverts the dynamics of a nonminimum system is based on cascading a stable pole-zero cancellation infinite impulse response (IIR) filter with a high-order finite impulse response (FIR) filter which inverts the unstable zero dynamics. The high-order FIR filter is realized based on efficient IIR filter implementation first introduced by Powell and Chau then later modified by Kurosu. As a demonstrative example, the inversion filters are applied to feedforward tracking and repetitive control algorithms and realized by a field programmable gate array. The controllers are implemented at 100-kHz sampling rate to control the motion of a 4 degrees-of-freedom magnetically levitated shaft in experiment.

关键词： Digital control electromagnetic forces feedforward systems field-programmable gate arrays infinite impulse response (IIR) filters mechatronics

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An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2016年第1期24卷 178-191页

作者： Bsoul, Assem A. M. Wilton, Steven J. E. Tsoi, Kuen Hung Luk, Wayne Univ British Columbia Dept Elect & Comp Engn Vancouver BC V6T 1Z4 Canada Univ London Imperial Coll Sci Technol & Med Dept Comp London SW7 2AZ England

Leakage power is an important component of the total power consumption in field-programmable gate arrays (FPGAs) built using 90-nm and smaller technology nodes. Power gating was shown to be effective at reducing the leakage power. Previous techniques focus on turning OFF unused FPGA resources at configuration time;the benefit of this approach depends on resource utilization. In this paper, we present an FPGA architecture that enables dynamically controlled power gating, in which FPGA resources can be selectively powered down at run-time. This could lead to significant overall energy savings for applications having modules with long idle times. We also present a CAD flow that can be used to map applications to the proposed architecture. We study the area and power tradeoffs by varying the different FPGA architecture parameters and power gating granularity. The proposed CAD flow is used to map a set of benchmark circuits that have multiple power-gated modules to the proposed architecture. Power savings of up to 83% are achievable for these circuits. Finally, we study a control system of a robot that is used in endoscopy. Using the proposed architecture combined with clock gating results in up to 19% energy savings in this application.

关键词： Computer aided design field-programmable gate arrays power gating static/leakage power

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JACC-FPGA: A hardware accelerator for Jaccard similarity estimation using FPGAs in the cloud

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FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE 2023年 138卷 26-42页

作者： Soto, Javier E. Hernandez, Cecilia Figueroa, Miguel Univ Concepcion Elect Engn Dept Concepcion Chile Univ Concepcion Comp Sci Dept Concepcion Chile Ctr Biotechnol & Bioengn CeBiB Santiago Chile

Genomic similarity is a key metric in genomics, used in important tasks such as genome clustering and metagenomic profiling. One commonly-used approach is to treat each genome as a set of k-mers and to compute the Jaccard coefficient between each genome pair. However, computing the Jaccard coefficient between genomes in a large dataset is a computationally-challenging task. In this paper, we present an algorithm and accelerator architecture that uses an FPGA-as-a-service paradigm to compute the Jaccard similarity between pairs of genomes in large datasets using sketches and hardware acceleration in the cloud. The algorithm can compute the similarity between all genome pairs in the dataset, or it can use a selection criterion to reduce the amount of computation when only genome pairs with a Jaccard coefficient above a user-supplied threshold are of interest. After building the sketches, our heterogeneous accelerator can compute more than 96 million Jaccard coefficients per second running on an AWS EC2 f1.2xlarge instance with a Xilinx XCVU9P FPGA, which is 58 times faster than a state-of-the art software implementation that exploits SIMD instructions and thread-level parallelism on a compute-optimized EC2 c5.9xlarge instance with 36 hardware threads. The accelerator also computes similarities 27 times faster than a straightforward GPU-accelerated implementation of the Jaccard coefficient using sketches, and 4 times faster than an optimized GPU implementation of our algorithm, both running on an EC2 g5.4xlarge instance tailored with an NVIDIA A10G GPU. Furthermore, using a Jaccard coefficient threshold of 0.8 reduces the execution time of similarity computation to approximately one third in the hardware-accelerated and parallel software implementations, compared to computing the complete similarity matrix.(C) 2022 Elsevier B.V. All rights reserved.

关键词： Hardware acceleration Cloud computing field-programmable gate arrays Streaming algorithms Sketches Genomics

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The case for reconfigurable hardware in wearable computing

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PERSONAL AND UBIQUITOUS COMPUTING 2003年第5期7卷 299-308页

作者： Plessl, Christian Enzler, Rolf Walder, Herbert Beutel, Jan Platzner, Marco Thiele, Lothar Troester, Gerhard Comp Engn & Networks Lab TIK ETH Zentrum Off ETZ G81 CH-8092 Zurich Switzerland Swiss Fed Inst Technol Elect Lab Zurich Switzerland

Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM.

关键词： Body area computing system Embedded systems field-programmable gate arrays Reconfigurable hardware Wearable computing

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Enhanced Model and Real-Time Simulation Architecture for Modular Multilevel Converter

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IEEE TRANSACTIONS ON POWER DELIVERY 2018年第1期33卷 466-476页

作者： Ashourloo, Mojtaba Mirzahosseini, Ramin Iravani, Reza Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

This paper presents i) an equivalent model of the half-bridge modular multilevel converter (HB-MMC) which is suitable for real-time applications, ii) a hybrid central-processing unit/ field-programmable gate array (CPU/FPGA)-based architecture for real-time simulation of electromagnetic transients of systems which include HB-MMC, and iii) a novel arrangement for sorting results referred to as the "sub-module (SM) rank list", which tackles the bottleneck for parallel implementation of the MMC arm model solver on the FPGA. The Adam-Bashforth (AB) method is used for numerical integration of the HB-SM capacitor model. The second-order AB method provides a constant admittance matrix of the HB-MMC and, thus, reduces computational burden while offering the same accuracy as that of the widely used Trapezoidal method. The CPU/FPGA-based architecture is optimized to obtain maximum parallelism of the HB-MMC model implementation, adopting a standard, single-precision, floating-point computational engine. The proposed sorting arrangement is independent of the utilized sorting algorithm and its application to the odd-even bubble sorting scheme is presented in this paper. The proposed architecture offers a simulation time-step of 825 ns while including the sorting module as the SM capacitor voltage-balancing control unit. This enables accurate analysis of MMC controls based on either software-in-the-loop or hardware-in-the-loop approaches. Performance and accuracy of the MMC model and the hybrid CPU/FPGA-based architecture are evaluated based on a set of case studies on a 401-level HB-MMC-based HVDC station and verified based on offline simulation results in the PSCAD/EMTDC environment.

关键词： Equivalent circuits field-programmable gate arrays HVDC converters real-time systems

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