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Nonlinear Behavioral Modeling and Real-Time Simulation of Electric Propulsion System for the High-Fidelity X-in-the-Loop Applications

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IEEE TRANSACTIONS ON TRANSPORTATION ELECTRIFICATION 2023年第1期9卷 1708-1722页

作者： Bai, Hao Li, Qian Luo, Huan Huangfu, Yigeng Gao, Fei Northwestern Polytech Univ Sch Automat Xian 710072 Peoples R China Univ Bourgogne Franche Comte Franche Comte Elect Mech Thermal Sci & Opt Sci & Univ Technol Belft Montbeliard UTBM French Natl Ctr Sci Res CNRS F-90010 Belfort France Xian Univ Sci & Technol Sch Mat Sci & Engn Xian 710054 Peoples R China

The electric propulsion system (EPS) is an important enabling technology for electrified transportation. The short time-to-market of such a system relies on real-time simulation (RTS)-based efficient X-in-the-loop testing. To ensure high fidelity, the RTS should include the detailed behavior as much as possible while complying with the constraints of the model computing time. Therefore, a nonlinear behavioral real-time modeling approach is proposed for the EPS in this article, including the adaptive curve-fitting (ACF)-based device-level power electronics model and the nonlinear flux-linkage-based spatial harmonic (FLSH) PMSM model. The real-time models are designed and implemented on the NI FLEXRIO FPGA module. Ultralow RTS latencies are realized for the ACF power converter model and the FLSH PMSM model, which are 25 and 160 ns, respectively. The simulation accuracies are consistent with the off-line simulation tools. Moreover, the ACF model and the FLSH model are used in the RTS of a fuel cell electric vehicle (FCEV) EPS together with the generic fuel cell model, the battery model, and the vehicle dynamic motion model. The RTS results prove that the proposed EPS real-time model is an excellent candidate for RTS applications.

关键词： Computational modeling Integrated circuit modeling Transient analysis Real-time systems Switches Adaptation models Biological system modeling field-programmable gate arrays modeling power electronics real-time system simulation

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New high-performance thyristor gate control set for line-commutated converters

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 1999年第5期46卷 972-978页

作者： Benedetti, M Uicich, G Consejo Nacl Invest Cient & Tecn Buenos Aires DF Argentina Univ Nacl Mar del Plata Fac Ingn RA-7600 Mar Del Plata Buenos Aires Argentina

In this paper, a novel implementation to obtain the triggering pulses for thyristorized ac/dc power converters is presented. The system developed is a variant of the digital ramp-and-threshold strategy employing parallel hardware calculation. In order to reduce the number of components otherwise involved, innovative ideas that make feasible the use of only one low-cost field-programmable gate array as the digital core, have been introduced. Based on the proposed topology, a compact high-resolution optimum-speed thyristor gate control circuit is achieved. The resulting system is very flexible and can be easily configured to drive series- or parallel-connected multiple-pulse controlled rectifiers. Practical results are provided.

关键词： AC/DC power conversion digital circuits field-programmable gate arrays thyristor

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KGPMAP - LIBRARY-BASED TECHNOLOGY-MAPPING TECHNIQUE FOR ANTIFUSE BASED FPGAS

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 1994年第6期141卷 361-368页

作者： CHATTOPADHYAY, S ROY, S CHAUDHURI, PP Dept. of Comput. Sci. & Eng. Indian Inst. of Technol. Kharagpur India

Owing to their high degree of flexibility and low design-turnaround time, field-programmable-gate-array (FPGA) based designs are becoming very popular. With the availability of different types of FPGA, the need of a unified approach for logic-block-independent technology mapping is being felt increasingly. The paper presents a new approach to efficient realisation of a given combinational function in terms of a prespecified k-input-single-output logic block. All subfunctions of 1 to k inputs realisable by the logic block are generated and kept in a library. The approach is general in the sense that it is not targeted to any specific FPGA built around a specified set of basic blocks. It uses a node-clustering technique for breaking up the given combinational function into subfunctions with special treatment for the fanout nodes. The scheme utilises a novel signature-based strategy to find a match for a subfunction in the library. One contribution is the elegant signature-generation scheme that can be applied for any library-based search problem. The signature is unique for functions of up to four variables and has an aliasing of around 0.5% for functions with larger number of variables. For comparison with other mapping techniques, the KGPMAP algorithm has been applied to several combinational benchmark circuits using Actel's act1-library. The result has been found to be superior to other well known library-based technology mappers and some Actel-specific mappers.

关键词： field-programmable gate arrays LOGIC BLOCKS FUNCTION MAPPING

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Long-Range Pulse Interactions in Unclocked FPGAs

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IEEE ACCESS 2023年 11卷 41158-41166页

作者： Cohen, Seth D. Fendley, Casey M. Beal, Aubrey N. Corron, Ned J. Kratos SRE Inc Birmingham AL 35211 USA Univ Alabama Huntsville Dept Elect & Comp Engn Huntsville AL 35899 USA

Evidence of long-range interactions between logic transitions in unclocked FPGA circuits is reported. The relative positions of pulses traveling in digital feedback loops are observed to dynamically interact and move to equal spacing over long timescales. We confirm the presence of this interaction over different FPGA supply voltages and hypothesize the pulse interactions are due to current draw in the power distribution network of the FPGA. This pulse interaction effect is observed for different FPGA families and manufacturers, including Altera and Xilinx, and has been tested using both look-up table (LUT) and carry chain (CC) logic to realize the feedback delays.

关键词： field programmable gate arrays Feedback loop Delays Transient analysis Steady-state Couplings Table lookup Asynchronous circuits feedback circuits field-programmable gate arrays pulse circuits pulse interactions non-blocking delay lines oscillators network dynamics transient analysis

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High-Time-Resolution Nuclear Magnetic Resonance With Nitrogen-Vacancy Centers

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IEEE MAGNETICS LETTERS 2016年 7卷 1-5页

作者： Qin, Xi Xie, Yijin Li, Rui Rong, Xing Kong, Xi Shi, Fazhan Wang, Pengfei Du, Jiangfeng Hefei Natl Lab Phys Sci Microscale Hefei 230026 Anhui Peoples R China Univ Sci & Technol China Dept Modern Phys Hefei 230026 Anhui Peoples R China Synerget Innovat Ctr Quantum Informat & Quantum P Hefei 230026 Anhui Peoples R China

We present a field-programmable gate array (FPGA)-based solution for high-time-resolution nanoscale nuclear magnetic resonance, with nitrogen-vacancy centers as a probe. The Xilinx FPGA is used to implement a high-performance pulse generator, which contributes to high-precision measurement for the nuclear magnetic resonance (NMR) signal. The pulse generator outputs continuous pulses with a time resolution of 50 ps and a dynamic range of 5 ns to 2.68 s. The central control and the readout logics for the NMR experiment are fully implemented in the FPGA. We observed nanoscale NMR signals of hydrogen atoms by measuring the period of the Larmor precession with a 50 ps time resolution. Furthermore, we demonstrate the ability to distinguish signals of adjacent frequencies, which is a great advantage in high-resolution analysis for the nanoscale NMR.

关键词： Magnetic instruments field-programmable gate arrays nitrogen-vacancy centers nuclear spin

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On optimal board-level routing for FPGA-based logic emulation

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1997年第3期16卷 282-289页

作者： Mak, WK Wong, DF Department of Computer Sciences University of Technology Austin TX USA

In this paper, we consider a board-level routing problem which is applicable to held-programmable gate arrays (FPGA)-based logic emulation systems such as the Realizer System [3] and the Enterprise Emulation System [5] manufactured by Quickturn Design Systems. For the case where all nets are two-terminal nets, we present an O(n(2))-time optimal algorithm where n is the number of nets. Our algorithm guarantees 100% routing completion if the number of interchip signal pins on each FPGA chip in the logic emulation system is less than or equal to the number of I/O pins on the chip. Our algorithm is based on iterative computation of Euler circuits in graphs. We also prove that the routing problem with multiterminal nets is NP-complete. And we suggest one way to handle multiterminal nets using some additional resources.

关键词： design automation field-programmable gate arrays logic emulation routing

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The ReadoutCard Userspace Driver for the New Alice O² Computing System

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2021年第8期68卷 1876-1883页

作者： Alexopoulos, Konstantinos Costa, Filippo CERN European Org Nucl Res CH-1221 Geneva Switzerland

A large ion collider experiment (ALICE) experiment focuses on the study of the quark-gluon plasma as a product of heavy-ion collisions at the CERN large hadron collider (LHC). During the long shutdown 2 of the LHC in 2019-2020, a major upgrade is underway in order to cope with a hundredfold input data rate increase with peaks of up to 3.5 TB/s. This upgrade includes the new online-offline computing system called O-2. The O-2 readout chain runs on commodity Linux servers equipped with custom peripheral component interconnect express (PCIe) field-programmable gate array (FPGA)-based readout cards: the PCIe Gen 3 x 16, Intel Arria 10-based common readout unit (CRU), and the PCIe Gen 2 x 8, Xilinx Vertex 6-based Common ReadOut Receiver Card (CRORC). Access to the cards is provided through the O2 ReadoutCard userspace driver, which handles synchronization and communication for direct memory access (DMA) transfers, provides base address registers (BAR) access, and facilitates card configuration and monitoring. The ReadoutCard driver is the lowest level interface to the readout cards within O-2 and is in use by all central systems and detector teams of the ALICE experiment. This communication presents the architecture of the driver and the suite of tools used for card configuration and monitoring. It also discusses its interaction with the tangent subsystems within the O-2 framework.

关键词： Base address register (BAR) data acquisition systems direct memory access (DMA) drivers field-programmable gate arrays

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A Very Fast Trace-Driven Simulation Platform for Chip-Multiprocessors Architectural Explorations

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2017年第11期28卷 3033-3045页

作者： Elrabaa, Muhammad E. S. Hroub, Ayman Mudawar, Muhamed F. Al-Aghbari, Amran Al-Asli, Mohammed Khayyat, Ahmad King Fahd Univ Petr & Minerals Comp Engn Dept Dhahran 31261 Saudi Arabia

Simulation is the main tool for computer architects and parallel application developers for developing new architectures and parallel algorithms on many-core machines. Simulating a many-core architecture represent a challenge to software simulators even with parallelization of these SW on multi-cores. field programmable gate arrays offer an excellent implementation platform due to inherent parallelism. Existing FPGA-based simulators however, are mostly execution-driven which consumes too many FPGA resources. Hence, they still trade-off accuracy with simulation speed as SW simulators do. In this work, an application-level trace-driven FPGA-based many-core simulator is presented. A parameterized Verilog template was developed that can generate any number of simulator tiles. The input trace has an architecturally agnostic format that is directly interpreted by the FPGA-based timing model to re-construct the execution events of the original application with accurate timing. This allows fitting a large number of simulation tiles on a single FPGA without sacrificing simulation speed or accuracy. Experimental results show that the simulator's average accuracy is similar to 14 percent with simulation speeds ranging from 100's of MIPs to over 2,200 MIPS for a 16-core target architecture. Hence, with accuracy similar to SW simulators, its speed is higher than all other FPGA-based simulators.

关键词： Trace-driven simulations hardware simulators chip-multiprocessors multithreading field-programmable gate arrays

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Single ADC Digital PFC Controller Using Precalculated Duty Cycles

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IEEE TRANSACTIONS ON POWER ELECTRONICS 2014年第2期29卷 996-1005页

作者： Sanchez, Alberto de Castro, Angel Manuel Lopez, Victor Azcondo, Francisco J. Garrido, Javier Univ Autonoma Madrid HCTLab Lab E-28049 Madrid Spain Univ Cantabria Dept Elect Technol Syst & Automat Engn E-39005 Santander Spain

Traditional digital power factor correction (PFC) uses three sensors to measure the input and output voltages and the input current. Each sensor, especially the input current one, increases the cost of the system and generates power losses in case of resistive sensors. This paper presents a controller for boost PFC converters. It uses precalculated duty cycles generated offline, and applies them to the switch. In order to control the converter with nonnominal conditions, just one analog-to-digital converter (ADC) is used, which measures the output voltage. Measuring the average and the ripple of the output voltage with this ADC, the controller takes compensation action for changes in the input voltage but also in the load of the converter. The average value is used to control the input voltage changes, while the ripple value is used to control load changes. These two loops present low frequency bandwidth, so the ADC and the whole system can be low cost. Finally, a comparator is used to detect the zero-crossing of the input voltage, so the precalculated values are synchronized with the ac mains. In this way, the converter only uses one ADC and one comparator, both with low bandwidth. Results show that high power factor and normative compliance are reached, even under nonnominal conditions.

关键词： Digital control field-programmable gate arrays rectifiers switched mode power supplies

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Partial-encryption technique for intellectual property protection of FPGA-based products

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2000年第1期46卷 183-190页

作者： Yip, KW Ng, TS Univ Hong Kong Dept Elect & Elect Engn Hong Kong Hong Kong Peoples R China

The configuration-data sequence of a field-programmable gate array (FPGA) is an intellectual property (IP) of the original designer. This paper proposes a partial-encryption (PE) technique for IP protection of configuration-data sequences by means of increasing the reverse-engineering cost. The PE technique encrypts a few selected data of the sequence. These data are selected in a judicious way such that, when a rival competitor copies the partially encrypted sequence into a cloned product, the cloned product performs the expected task to a certain degree of correctness but not absolutely error-free. Debugging is required. It is shown that, without an initial knowledge that a reverse-engineering countermeasure is employed, the PE technique outperforms the full-encryption technique in terms of the reverse-engineering cost. This paper describes implementation details of the proposed PE technique. Issues regarding system designs that embed hidden imperfections are also discussed.

关键词： partial encryption intellectual property protection reverse engineering reverse-engineering countermeasure field-programmable gate arrays SRAM-based FPGA obfuscation

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