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Effects of technology mapping on fault-detection coverage in reprogrammable FPGAs

IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 1995年第6期142卷 407-410页

作者： Kwiat, K Debany, W Hariri, S SYRACUSE UNIV DEPT ELECT & COMP ENGNSYRACUSENY 13244

Although field-programmable gale arrays (FPGAs) are tested by their manufacturers prior to shipment, they are still susceptible to failures in the field, In this paper test vectors generated for the emulated (i.e. mission) circuit are fault-simulated on two different models: the original view of the circuit, and the design as it is mapped to the FPGA's logic cells, Faults in the cells and in the programming logic are considered. Experiments show that this commonly-used approach fails to detect most of the faults in the FPGA.

关键词： fault detection field-programmable gate arrays

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Embedded Flash on a Low-Power 65-nm Logic Technology

IEEE ELECTRON DEVICE LETTERS

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IEEE ELECTRON DEVICE LETTERS 2012年第9期33卷 1261-1263页

作者： Fong, S. Ariyoshi, J. Ema, T. Lattice Semicond Inc San Jose CA 95134 USA Fujitsu Semicond Ltd Kuwana 5110192 Japan

We have successfully integrated an embedded Flash technology into a 65-nm leading-edge logic technology. We have also optimized the logic transistor characteristics to achieve an extremely low standby current suitable... 详细信息

关键词： Embedded Flash memory field-programmable gate arrays low power

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Comparative study of LDPC coding schemes and FPGA implementation for inter-vehicle communications

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ELECTRONICS LETTERS 2015年第16期51卷 1255-1256页

作者： Kiokes, G. Zountouridou, E. Hellen Air Force Acad Dept Elect Elect Power & Telecommun Dekeleia Air Base Dekeleia Attica Greece Natl Tech Univ Athens Sch Elect & Comp Engn Zografos Greece

A novel comparative study of different low-density parity-check (LDPC) coding algorithms and implementation issues through field-programmable gate arrays (FPGAs) technology for wireless vehicular applications is presented. A key development in LDPC codes is the iterative decoding algorithm which uses the belief propagation algorithm. A comprehensive investigation of the performance of different coding schemes was carried out. Four different decoding techniques were tested by computer-based simulations of messages modulated under the binary phase-shift keying modulation scheme and transmitted through a vehicular channel model. Finally, the best performance ratio against complexity algorithm was chosen to be implemented on a Xilinx FPGA platform.

关键词： field programmable gate arrays iterative decoding parity check codes phase shift keying FPGA implementation LDPC coding schemes belief propagation algorithm field-programmable gate arrays inter-vehicle communications iterative decoding algorithm low-density parity-check coding algorithm phase-shift keying modulation scheme vehicular channel model

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High-Performance Packet Routing Acceleration for Cloud Systems Using High Bandwidth Memory

IEEE OPEN JOURNAL OF THE COMMUNICATIONS SOCIETY

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IEEE OPEN JOURNAL OF THE COMMUNICATIONS SOCIETY 2022年 3卷 119-126页

作者： Shimizu, Takashi Hyoudou, Kazuki Murakawa, Hiroshi Ishihara, Tomohiro Fujitsu Ltd Infrastruct Syst Dept Kawasaki Kanagawa 2110053 Japan Fujitsu Labs Ltd ICT Syst Lab Kawasaki Kanagawa 2110053 Japan

Virtual routers (vRouters) in cloud systems are in great demand due to the ever-increasing network bandwidth. To meet this demand, hardware offload technologies are mandatory for vRouters. Furthermore, offload hardware needs new architecture to achieve a throughput of several hundred Gbps, because memories that store routing tables will create a bottleneck. Therefore, we propose a new hardware architecture using high bandwidth memories (HBMs) and an acceleration engine equipped with multi-pipeline processing. In this paper, we improved the performance of the random memory-accesses from multiple pipelines by distributing to the memory channels of HBMs. In our prototype, vRouter packet processing performances were achieved 320 M packet per second(pps) and 250 Gbit per second (bps). Moreover, the prototype showed low and stable latency of packet transfers that was not affected by background traffic.

关键词： Computer architecture Software Cloud computing Routing Hardware field programmable gate arrays Pipelines Accelerator architecture field-programmable gate arrays high bandwidth memory virtual router hardware offload

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High-Speed Energy-Efficient Fixed-Point Signed Multipliers for FPGA-Based DSP Applications

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IEEE EMBEDDED SYSTEMS LETTERS 2024年第4期16卷 417-420页

作者： Nagar, Mitul Sudhirkumar Mathuriya, Aditya Patel, Sohan H. Engineer, Pinalkumar J. Sardar Vallabhbhai Natl Inst Technol Dept Elect Engn Surat 395007 India

Among various platforms for computer vision algorithms, FPGA has gained popularity as a low-power solution. These algorithms involve convolution operation which are extensively performed using signed multipliers. Hence, this work proposes high-speed and energy-efficient signed fixed-point multipliers for digital signal processing (DSP) applications. This work focuses on reducing the combinational path delay (CPD) using LUT-based Booth radix-4 partial product (PP) generation with Bewick's sign extension and Dadda-based concurrent PP reduction with carry save adder (CSA) for Xilinx (now AMD) FPGA. The proposed design eliminates the requirement of a long carry chain for PP reduction. The proposed multiplier reduces CPD by 3%, 4%, and 16% compared to the state-of-the-art (SoA) multiplier for 8x8 , 16x16 , and 32x32 sizes, respectively. We have also analyzed our proposed 32x32 multiplier by pipelining, which offers CPD and EDP reduction by 12.28% and 19.47% at the cost of a 3% and 80% increase in LUTs and flip-flops, respectively, compared to the combinatorial multiplier.

关键词： Table lookup field programmable gate arrays Adders Vegetation Standards Signal processing algorithms Resource management Booth radix-4 digital signal processing (DSP) energy-efficient field-programmable gate arrays signed fixedpoint multiplier

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Island-Based Adaptable Embedded System Design

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IEEE EMBEDDED SYSTEMS LETTERS 2011年第2期3卷 53-57页

作者： Beretta, Ivan Rana, Vincenzo Atienza, David Sciuto, Donatella Ecole Polytech Fed Lausanne Embedded Syst Lab CH-1015 Lausanne Switzerland Politecn Milan Dipartimento Elettron & Informaz I-20133 Milan Italy

Nowadays, hardware devices are meant to host the execution of many complex, multicore applications, whose functional and nonfunctional requirements vary according to the specific working domain. In this work, we propose a design methodology that combines an efficient reconfigurable architecture and a related mapping flow. In particular, the proposed island-based hardware architecture couples an efficient area usage and an adaptable communication infrastructure. The proposed mapping flow distributes the cores on the device to optimize both performance and reconfiguration related metrics.

关键词： CAD tools field-programmable gate arrays (FPGAs) platform-based design reconfigurable computing

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A framework of embedded reconfigurable systems based on re-locatable virtual components

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INTERNATIONAL JOURNAL OF EMBEDDED SYSTEMS 2010年第3-4期4卷 182-194页

作者： Dumitriu, Victor Kirischian, Lev Ryerson Univ Dept Elect & Comp Engn 350 Victoria St Toronto ON M5B 2K3 Canada

The use of modern field-programmable logic devices can help system designers achieve better cost-performance characteristics, in particular in the case of multi-task and multi-modal workloads. This is particularly true when the embedded systems are based on run-time and partially reconfigurable FPGA devices. Such devices permit a system to implement part of its functionality in virtual form, by storing circuits as configuration bit-streams. The use of such virtual components, however, imposes certain requirements on both the behaviour of the system as well as the components themselves. The work presented here analyses some of these requirements, and proposes a potential framework for designing embedded systems using virtual resources. Two examples of a system using virtual components are presented and the infrastructure overhead for supporting virtual components is analysed. It is found that such systems can be implemented efficiently, both in terms of hardware resources as well as timing performance.

关键词： dynamic reconfiguration embedded systems field-programmable gate arrays system design video processing virtual hardware component virtualisation

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A Random Number Generator Using Ring Oscillators and SHA-256 as Post-Processing

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INTERNATIONAL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS 2015年第2期61卷 199-204页

作者： Loza, Szymon Matuszewski, Lukasz Jessa, Mieczyslaw Poznan Univ Tech Fac Elect & Telecommun Ul Polanka 3 PL-61131 Poznan Poland

Today, cryptographic security depends primarily on having strong keys and keeping them secret. The keys should be produced by a reliable and robust to external manipulations generators of random numbers. To hamper different attacks, the generators should be implemented in the same chip as a cryptographic system using random numbers. It forces a designer to create a random number generator purely digitally. Unfortunately, the obtained sequences are biased and do not pass many statistical tests. Therefore an output of the random number generator has to be subjected to a transformation called post-processing. In this paper the hash function SHA-256 as post-processing of bits produced by a combined random bit generator using jitter observed in ring oscillators (ROs) is proposed. All components - the random number generator and the SHA-256, are implemented in a single field programmable gate Array (FPGA). We expect that the proposed solution, implemented in the same FPGA together with a cryptographic system, is more attack-resistant owing to many sources of randomness with significantly different nominal frequencies.

关键词： random numbers cryptography ring oscillators hash functions field-programmable gate arrays

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Optimization and performance evaluation of graphic processing units for voice processing

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JOURNAL OF ALGORITHMS & COMPUTATIONAL TECHNOLOGY 2017年第4期11卷 388-394页

作者： Sayadi, Fatma E. Bahri, Haythem Chouchene, Marwa Atri, Mohamed Monastir Univ Fac Sci Lab Elect & Microelect EE Environm St Monastir 5019 Tunisia

With the advancement in the device technology and parallel architecture, field-programmable gate arrays (FPGAs) can well perform the speech processing operation. FPGAs have very impressive results, despite their low operating frequency, by completely extracting the parallelism. Nevertheless, recent central processing unit and graphic processing unit (GPU) have also an inherent feature for high performance. In fact, recent GPUs enable dramatic increases in computing performance by harnessing great number of cores. In this context, we seek to analyze the performance of the linear prediction coding algorithm implementation on two different platforms: one based on the GPU NVIDIA GeForce GTX 480 and another on the FPGA Spartan-6. Subsequently, we try to apply several optimization strategies on those platforms. The experimental results highlight the relative robustness or weakness of both these platforms. The tests prove that, for several samples, GPU manages speedups of up to 4x compared to the FPGA and around 48x compared to a sequential execution.

关键词： Linear predictive coding graphic processing unit field-programmable gate arrays optimization strategies shared memory

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programmable logic devices - key components for today's and tomorrow's electronic-based systems

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ELEKTROTECHNIK UND INFORMATIONSTECHNIK 2020年第1期137卷 45-51页

作者： Roessler, Peter Hoeller, Roland Dept Elect Engn Fachhochschule Technikum Wien Hochstadtplatz 6 A-1200 Vienna Austria

Since their introduction in the 1970s, programmable Logic Devices (PLDs) evolved from implementing small glue-logic designs to large, configurable multi-processor Systems-on-Chip (SoC). Today's most prominent PLD technology, known as FPGA (field-programmable gate Array), is used in an increasing number of application domains, such as the telecom industry, the automotive electronics sector or automation technology, and recent market studies expect a continuous demand for these sophisticated microelectronic devices in the future. For small and medium enterprises and/or SME-dominated countries like Austria, FPGAs can provide access to VLSI (Very Large Scale Integration) technology by avoiding the immense NRE (Non-Recurring Engineering) costs of ASICs (Application-Specific Integrated Circuits). This work outlines how today's and future electronic-based systems can benefit from FPGA technology. Trends, tools and design flows will be explained as well as research challenges that are currently investigated within two public funded R&D projects at the University of Applied Sciences Technikum Wien.

关键词： programmable Logic Devices field-programmable gate arrays PLD FPGA

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