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Novo-G#: a multidimensional torus-based reconfigurable cluster for molecular dynamics

CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2016年第8期28卷 2374-2393页

作者： Lawande, Abhijeet G. George, Alan D. Lam, Herman Univ Florida Dept Elect & Comp Engn NSF Ctr High Performance Reconfigurable Comp CHRE Gainesville FL 32611 USA

Molecular dynamics (MD) is a large-scale, communication-intensive problem that has been the subject of high-performance computing research and acceleration for years. Not surprisingly, the most success in accelerating MD comes from specialized systems such as the Anton machine. In this paper, we describe Novo-G# (novo-jee-sharp), a multi-node reconfigurable system designed for the acceleration of communication-intensive scientific problems in general, and MD in particular. This system provides a high-bandwidth, low-latency 3D torus network to allow direct communication between kernels running on multiple field-programmable gate arrays. We also present a performance model for Novo-G# running the 3D Fast Fourier Transform (FFT) kernel that forms the core of MD simulations. We validate the model against published Anton performance data and through initial hardware experiments on Novo-G#. Finally, through simulation studies, we show that this system at scale performs better than specialized systems like Anton and outperforms established CPU-based clusters like Blue Gene/Q by an order of magnitude for the 3D FFT kernel, with greater flexibility and lower costs. Copyright (c) 2015John Wiley & Sons, Ltd.

关键词： high-performance computing modeling computer simulation reconfigurable architectures field-programmable gate arrays

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High-Speed Implementation of bcrypt Password Search using Special-Purpose Hardware

High-Speed Implementation of bcrypt Password Search using Sp...

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2014 International Conference on Reconfigurable Computing and FAGAs

作者： Wiemer, Friedrich Zimmermann, Ralf Ruhr Univ Bochum Horst Gortz Inst IT Secur HGI Bochum Germany

ISBN: (纸本)9781479959440

Using passwords for user authentication is still the most common method for many internet services and attacks on the password databases pose a severe threat. To reduce this risk, servers store password hashes, which were generated using special password-hashing functions, to slow down guessing attacks. The most frequently used functions of this type are PBKDF2, bcrypt and scrypt. In this paper, we present a novel, flexible, high-speed implementation of a bcrypt password search system on a low-power Xilinx Zynq 7020 FPGA. The design consists of 40 parallel bcrypt cores running at 100 MHz. Our implementation outperforms all currently available implementations and improves password attacks on the same platform by at least 42%, computing 6,511 passwords per second for a cost parameter of 5.

关键词： cryptography field programmable gate arrays message authentication bcrypt password search system field-programmable gate arrays frequency 100 MHz high-speed password search system implementation low-power Xilinx Zynq 7020 FPGA parallel bcrypt cores password attacks special-purpose hardware Clocks Cryptography Fabrics field programmable gate arrays Hardware Power demand Registers

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FPGA Design of a New Frequency Relay Based on Evolutionary Algorithms

FPGA Design of a New Frequency Relay Based on Evolutionary A...

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IEEE PES 2nd Latin American Conference on Innovative Smart Grid Technologies (ISGT Latin America)

作者： Coury, Denis V. Delbem, Alexandre C. B. Oleskovicz, Mario Simoes, Eduardo V. Barbosa, Daniel de Carvalho, Janison R. Univ Sao Paulo Depto Engn Eletr & Comp EESC BR-13566590 Sao Carlos SP Brazil

ISBN: (纸本)9781467352741;9781467352727

This paper presents an efficient technique for frequency estimation in Electrical Power Systems (EPS) based on Genetic Algorithms (GAs). Frequency estimation of a distorted electrical signal is modeled as an optimization problem. The motivation concerning the use of the GA approach is related to its intrinsic robustness to noise. The GA is implemented in a FPGA (field-programmable gate Array) device and the estimation process is computed in real-time. This is made possible due to (a) the implicit parallelism of FPGAs (b) the suitable choice of the GA operators to explore this parallelism and (c) the determination of the appropriate architecture for a FPGA that parallelizes the GA routine and ensures its good performance. In order to evaluate the performance of the proposed method, an EPS was simulated using the ATP software for some typical operation conditions. The resulting signals were analyzed by the proposed GA/FPGA approach and they were compared to the performance of a commercial relay. Promising results were found with the proposed methodology.

关键词： Frequency Estimation Genetic Algorithms field-programmable gate arrays Digital Relaying Power System Protection

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A Less Configuration Memory Reconfigurable Logic Device with Error Detect and Correct Circuit

A Less Configuration Memory Reconfigurable Logic Device with...

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IEEE Region 10 Conference on TENCON 2010

作者： Zhao, Qian Ichinomiya, Yoshihiro Okamoto, Yasuhiro Amagasaki, Motoki Iida, Masahiro Sueyoshi, Toshinori Kumamoto Univ Grad Sch Sci & Technol Kumamoto 8608555 Japan

ISBN: (纸本)9781424468904

The field-programmable gate arrays (FPGAs) are widely used in varies fields in recent years. However, because of large amounts of configuration memories in FPGAs are used to implement logic and routing, the single event upset (SEU) problem makes them not feasible for applications that need high reliability. Moreover, as the threshold voltage becomes lower with the development of silicon process technology, the configuration memories are becoming more sensitive to SEU. Therefore, FPGAs require new technology to improve its dependability. In this research, we first develop a new Hamming code based error detect and correct (EDC) circuit that can prevent the configuration memory of a reconfigurable device from SEU. We then propose a novel reconfigurable logic element, namely COGRE, which will use much less configuration memory than the conventional FPGA 4-, 5- or 6-LUTs (lookup tables). Evaluation revealed that compared to the 6-LUT FPGAs with triple modular redundancy (TMR) configuration memory blocks, the 5- and 6-input COGRE with the novel error detect and correct circuit save about 75.44 and 74.29% memories on average, respectively. And the dependability of the proposed architectures is about 6.8 to 10 times better than the LUTs with a tile level TMR structure on average. Moreover, with the consideration of the on the fly scrubbing advantage of the EDC, SEUs cannot be accumulated, so a much higher dependability can be achieved.

关键词： EDC circuit Hamming code based error detect Hamming codes configuration memory reconfigurable logic device correct circuit error detect circuit field-programmable gate arrays logic circuits reconfigurable architectures reconfigurable logic element table l

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Virtualizing FPGAs in the Cloud 20

Virtualizing FPGAs in the Cloud

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25th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

作者： Zha, Yue Li, Jing Univ Penn Philadelphia PA 19104 USA

ISBN: (纸本)9781450371025

field-programmable gate arrays (FPGAs) have been integrated into the cloud infrastructure to enhance its computing performance by supporting on-demand acceleration. However, system support for FPGAs in the context of the cloud environment is still in its infancy with two major limitations, i.e., the inefficient runtime management due to the tight coupling between compilation and resource allocation, and the high programming complexity when exploiting scale-out acceleration. The root cause is that FPGA resources are not virtualized. In this paper, we propose a full-stack solution, namely ViTAL, to address the aforementioned limitations by virtualizing FPGA resources. Specifically, ViTAL provides a homogeneous abstraction to decouple the compilation and resource allocation. Applications are offline compiled onto the abstraction, while the resource allocation is dynamically determined at runtime. Enabled by a latency-insensitive communication interface, applications can be mapped flexibly onto either one FPGA or multiple FPGAs to maximize the resource utilization and the aggregated system throughput. Meanwhile, ViTAL creates an illusion of a single and large FPGA to users, thereby reducing the programming complexity and supporting scale-out acceleration. Moreover, ViTAL also provides virtualization support for peripheral components (e.g., on-board DRAM and Ethernet), as well as protection and isolation support to ensure a secure execution in the multi-user cloud environment. We evaluate ViTAL on a real system-an FPGA cluster composed of the latest Xilinx UltraScale+ FPGAs (XCVU37P). The results show that, compared with the existing management method, ViTAL enables fine-grained resource sharing and reduces the response time by 82% on average (improving Quality-of-Service) with a marginal virtualization overhead. Moreover, ViTAL also reduces the response time by 25% compared to AmorphOS (operating in high-throughput mode), a recently proposed FPGA virtualization method.

关键词： scale-out acceleration system abstraction compilation framework cloud computing field-programmable gate arrays

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Intelligent Structure Control System Based on FPGA 12

Intelligent Structure Control System Based on FPGA

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IEEE 12th Data Driven Control and Learning Systems Conference (DDCLS)

作者： Qiu Ruikang Li Shengquan Cui Ronghua Zhang Lujin Li Juan Yangzhou Univ Coll Elect Energy & Power Engn Yangzhou 225127 Peoples R China

ISBN: (纸本)9798350321050

A linear active disturbance rejection control (LADRC) strategy is proposed to suppress the structural vibration caused by external excitations and internal uncertainties in intelligent structures under complex working conditions via an Anlu EG4S20B256 chip. First, the electromechanical coupling model of the whole vibration control system is obtained based on the dynamic equations of the all-clamped plate structure and the electromagnetic equations of the inertial actuator. Second, based on the system model, a third-order extended state observer (ESO) is designed to estimate the internal modelling errors and external excitation perturbations of the system in real time. In addition, the influence of internal and external disturbances on the control effect in the experiment is offset by a feedforward compensation. Finally, a vibration control platform based on the Anlu FPGA chip is built to verify the control effect of the proposed vibration active control strategy through physical real-time simulation.

关键词： All-clamped plate Active vibration control Linear active disturbance rejection control field-programmable gate arrays

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A pipeline of associative memory boards for track finding

A pipeline of associative memory boards for track finding

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Annual Nuclear Science Symposium (NSS)

作者： Annovi, A Bagliesi, MG Bardi, A Carosi, R Dell'Orso, M Giannetti, P Iannaccone, G Morsani, F Pietri, M Varotto, G Ist Nazl Fis Nucl Pisa Italy Univ Pisa Dipartimento Fis I-56100 Pisa Italy Univ Pisa Dipartimento Ingn Informaz I-56126 Pisa Italy

We present a pipeline of associative memory boards for track finding, which satisfies the requirements of level two triggers of the next large hadron collider experiments. With respect to previous realizations, the pipelined architecture warrants full scalability of the memory bank, increased bandwidth (by one order of magnitude), and increased number of detector layers (by a factor of two). Each associative memory board consists of four smaller boards, each containing 32 programmable associative memory chips, implemented with a low-cost commercial field-programmable gate array (FPGA). FPGA programming has been optimized for maximum efficiency in terms of pattern density, while printed circuitboard design has been optimized in terms of modularity and FPGA chip density. A complete associative memory board has been successfully tested at 40 MHz;it can contain 7.2 x 10(3) particle trajectories.

关键词： associative memories data acquisition field-programmable gate arrays parallel processing particle tracking pattern matching pattern recognition pipeline processing trigger

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A hardware accelerator for quantile estimation of network packet attributes 27

A hardware accelerator for quantile estimation of network pa...

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27th Euromicro Conference on Digital System Design

作者： Gallardo-Pavesi, Carolina Fernandez, Yaime Soto, Javier E. Hernandez, Cecilia Figueroa, Miguel Univ Concepcion Dept Elect Engn Concepcion Chile Univ Concepcion Dept Comp Sci Concepcion Chile Ctr Biotechnol & Bioengn CeBiB Santiago Chile Adv Ctr Elect & Elect Engn AC3E Santiago Chile

ISBN: (纸本)9798350380392;9798350380385

Measuring statistical properties of network traffic can improve our understanding of traffic distribution and help us detect short and long-term anomalies. However, computing the exact value of these properties requires significant storage and computation, which limits their application in high-speed networks. Hardware accelerators provide the computational power to process a large sequence of network packets with high throughput and low latency, but their performance is ultimately limited by the amount of on-chip memory available on the device. Consequently, researchers have proposed sketch-based algorithms to estimate properties of a data stream with sublinear memory and theoretical estimation error bounds. In this paper, we present a streaming algorithm and hardware accelerator for quantile estimation, which is based on the architecture of the KLL sketch. Implemented on an AMD Virtex XCU55 UltraScale+ FPGA, the accelerator operates at a clock frequency of 356 MHz, thereby achieving a minimum line rate of 182 Gbps and a maximum estimation latency of 4.33 mu s. When processing a set of 10 real traffic traces of up to 123 million packets, the accelerator estimates 1000 packet-size quantiles per trace with a median error of 0.39% or less, and a maximum error of 1.3% or less across all traces.

关键词： Quantile estimation network measurement hardware acceleration sketch-based algorithms field-programmable gate arrays

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A hardware accelerator for entropy estimation using the top-k most frequent elements 23

A hardware accelerator for entropy estimation using the top-...

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23rd Euromicro Conference on Digital System Design (DSD)

作者： Soto, Javier E. Ubisse, Paulo Hernandez, Cecilia Figueroa, Miguel Univ Concepcion Dept Elect Engn Concepcion Chile Univ Concepcion Dept Comp Sci Concepcion Chile Ctr Biotechnol & Bioengn CeBiB Concepcion Chile

ISBN: (纸本)9781728195353

Estimating the empirical entropy of the elements in a dataset is an important task in data analysis. In particular, empirical entropy can be effectively used to detect anomalies in network traffic. However, computing the empirical entropy of a large dataset is computationally expensive and requires a large amount of memory. This is particularly important in highspeed network traffic analysis, where computing the entropy of a data flow in real time requires using hardware accelerators with restricted on-chip memory and arithmetic resources. In this work, we propose a method to estimate the entropy using a streaming algorithm with sublinear space requirements. Our approach uses a sketch to estimate the frequency of the elements in the stream, and a priority queue to store the top-k most frequent elements. We show that our method can provide a good approximation of the entropy of the dataset, and present the design of a hardware accelerator that can compute the entropy of the stream with a throughput of one packet per clock cycle. Implemented on a Xilinx Zynq UltraScale+ MPSoC ZCU102 FPGA, our accelerator can operate at line rates above 181 Gbps, consuming 511 mW and using less than 24% of the resources available on the device.

关键词： Entropy estimation heavy hitters sketch priority queue hardware acceleration field-programmable gate arrays

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Accounting for Floorplan Irregularity and Configuration Dependence in FPGA Routing Delay Models 24

Accounting for Floorplan Irregularity and Configuration Depe...

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24th International Symposium on Quality Electronic Design (ISQED)

作者： Barajas, Gabriel Greene, Jonathan W. Li, Fei Tandon, James Microchip San Jose CA 95134 USA Cambios Comp LLC Palo Alto CA USA Calif State Univ East Bay Hayward CA USA

ISBN: (纸本)9798350334753

Accurate delay estimates for a user application implemented in a field-programmable gate Array (FPGA) are essential for a quality FPGA timing flow and to avoid leaving performance on the table. FPGA inter-cluster routing consists of wire segments of a limited number of types which repeat in a somewhat regular pattern, interconnected by configurable muxes. The delay at any fanout of a segment can be significantly impacted by configuration-dependent capacitive loading related to other fanouts. Also, the insertion of RAM and math blocks into the FPGA floorplan introduces irregular stretching of the wire segments, altering their delays. We explain why and how commercial FPGA software typically employs a parameterized model for the delay at each fanout of a segment, based on the configuration and the irregularities present, with the parameters determined by fitting SPICE simulation data for a representative sample of cases. We propose incorporating readily-computed common path resistance values into the model. This enables high accuracy with fewer parameters and without the large amounts of SPICE data that would otherwise be required to explore interactions between floorplan irregularities and the set of active fanouts. In combination with other features of our models, errors in segment delay are reduced by almost half.

关键词： field-programmable gate arrays FPGAs delay estimation Elmore delay common path resistance

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