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Reconfigurable hardware solution to parallel prefix computation

JOURNAL OF SUPERCOMPUTING 2008年第1期43卷 43-58页

作者： Park, Jin Hwan Dai, H. K. SUNY Albany Dept Comp Sci New Paltz NY 12561 USA Oklahoma State Univ Dept Comp Sci Stillwater OK 74078 USA

This paper presents the design and implementation of an efficient reconfigurable parallel prefix computation hardware on field-programmable gate arrays (FPGAs). The design is based on a pipelined dataflow algorithm, and control logic is added to reconfigure the system for arbitrary parallelism degree. The system receives multiple input streams of elements in parallel and produces output streams in parallel. It has an advantage of controlling the degree of parallelism explicitly at run time. The time complexity of the design is O(d+(N-d)/d), where d and N are parallelism degree and stream size, respectively. When the stream size is sufficiently larger than the initial trigger time of the pipeline (d), the time complexity becomes O(N/d). Unlike the prefix computation circuits found in the literature, the design is scalable for different problem sizes including unknown sized data. The design is modular based on a finite state machine, and implemented and tested for target FPGA devices Xilinx Spartan2S XC2S300EFT256-6Q and XC2S600EFG676-6.

关键词： parallel prefix computation reconfigurable hardware field-programmable gate arrays dataflow pipeline

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FPGA-Based Real-Time Data Acquisition for Ultrafast X-Ray Computed Tomography

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2021年第12期68卷 2779-2786页

作者： Windisch, Dominic Knodel, Oliver Juckeland, Guido Hampel, Uwe Bieberle, Andre Tech Univ Dresden Chair Imaging Tech Energy & Proc Engn D-01069 Dresden Germany Helmholtz Zentrum Dresden Rossendorf D-01328 Dresden Germany

Ultrafast X-ray computed tomography (UFXCT) is a fast tomographic imaging technique based on the principle of electron beam scanning. It is used for the investigation of transient multiphase flows. A UFXCT scanner comprises multiple detector modules generating gigabytes of raw data per second for imaging rates of up to 8000 fps. During the data acquisition, these data are stored in RAM on each detector module and can therefore only be accessed after the acquisition. This limits the applicability of UFXCT systems because real-time control of the scanned process or the scanner itself is not possible. To achieve this, data streaming with low latency and high throughput is necessary. Using the newly developed FPGA-based data acquisition described in this article, the data acquisition is enhanced to real-time operation, i.e., streaming the acquired data to the processing computer within microseconds of their acquisition. The developed FPGA hardware implementation handles control of peripherals [such as analog-digital converters (ADC)], synchronization between detector modules, electron beam deflection, and data transfer via Gigabit Ethernet (GbE).

关键词： Detectors Hardware Ethernet Clocks Real-time systems Computed tomography X-ray imaging Computed tomography (CT) data acquisition field-programmable gate arrays

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An Implementation Method Using Cut-Off Bits for Restricted Boltzmann Machines Without Random Number Generators

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IEEE ACCESS 2022年 10卷 42791-42801页

作者： Hori, Sansei Tamukoh, Hakaru Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Wakamatsu Ku Kitakyushu Fukuoka 8080135 Japan Kyushu Inst Technol Res Ctr Neuromorph AI Hardware Kitakyushu Fukuoka 8080135 Japan

This study proposes an implementation method of a hardware-oriented restricted Boltzmann machine (RBM) without random number generators (RNGs) that employ cut-off bits, which are obtained from fixed-point binary arithmetic operations on digital hardware, such as field-programmable gate arrays (FPGAs), instead of random numbers. Most FPGA circuits employ fixed-point binary arithmetic operations to improve hardware resource efficiency. Therefore, the proposed method applies the unique feature of the operation, which is bit width extension and cut-off bits. Stochastic neural networks, including RBMs, employ sampling processes based on a probability distribution associated with the network, and the processes require many random numbers. However, implementing RNGs in hardware is costly because it requires considerable hardware resources. The proposed method can mitigate this requirement. To validate the proposed method, we implement an RBM with the proposed method on the software, emulate fixed-point binary arithmetic operations, and train the RBM using the MNIST and Fashion MNIST datasets. Furthermore, we apply the chi-square goodness-of-fit test to evaluate the uniformity of the cut-off bits. Additionally, we compare hardware resource requirements and power consumption for the proposed method and some major RNGs, a linear feedback shift register (LFSR), and a xorshift. Experimental results showed that it was possible to use the cut-off bits for training the RBM using the datasets and clarified the properties of the cut-off bits using statistical analyses. Moreover, hardware implementation of the proposed method involved the lowest hardware resource requirements and power consumption among the RNGs compared in this study.

关键词： Hardware field programmable gate arrays Neural networks Power demand Generators Cloud computing Training field-programmable gate arrays neural networks random number generation restricted Boltzmann machines

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A High-Throughput Hardware Accelerator for Network Entropy Estimation Using Sketches

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IEEE ACCESS 2021年 9卷 85823-85838页

作者： Soto, Javier E. Ubisse, Paulo Fernandez, Yaime Hernandez, Cecilia Figueroa, Miguel Univ Concepcion Elect Engn Dept Concepcion 4030000 Chile Univ Concepcion Comp Sci Dept Concepcion 4030000 Chile Ctr Biotechnol & Bioengn CeBiB Santiago 8370456 Chile

Network traffic monitoring uses empirical entropy to detect anomalous events such as various types of attacks. However, the exact computation of the entropy in high-speed networks is a difficult process due to the limited memory resources available in the data plane hardware. In this paper, we present a method and hardware accelerator to approximate the empirical entropy of a large data set with high throughput and sublinear memory requirements. Our method uses streaming algorithms that exploit the fine-grained parallelism of existing hardware platforms for data plane processing, such as field-programmable gate arrays (FPGAs). The method uses sketches to compute the cardinality of the stream and the frequencies of the top-K elements on line, and then it estimates the contribution to the entropy of the rest of the stream assuming a simple uniform distribution for these elements. Implemented on a Xilinx UltraScale+ ZCU102 FPGA, the accelerator implements the method using only on-chip memory, with less than 50% resource usage. Tested on real network traces of up to 120 million packets and more than 5 million flows, the accelerator estimates the empirical entropy with less than 1.5% mean relative error and 21 mu s latency, and supports a minimum throughput of 204 gigabits per second.

关键词： Empirical entropy network monitoring hardware acceleration field-programmable gate arrays streaming algorithms sketches

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Extensible FlexRay Communication Controller for FPGA-Based Automotive Systems

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IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY 2015年第2期64卷 453-465页

作者： Shreejith, Shanker Fahmy, Suhaib A. Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore TUM CREATE Singapore 138602 Singapore

Modern vehicles incorporate an increasing number of distributed compute nodes, resulting in the need for faster and more reliable in-vehicle networks. Time-triggered protocols such as FlexRay have been gaining ground as the standard for high-speed reliable communications in the automotive industry, marking a shift away from the event-triggered medium access used in controller area networks (CANs). These new standards enable the higher levels of determinism and reliability demanded from next-generation safety-critical applications. Advanced applications can benefit from tight coupling of the embedded computing units with the communication interface, thereby providing functionality beyond the FlexRay standard. Such an approach is highly suited to implementation on reconfigurable architectures. This paper describes a field-programmable gate array (FPGA)-based communication controller (CC) that features configurable extensions to provide functionality that is unavailable with standard implementations or off-the-shelf devices. It is implemented and verified on a Xilinx Spartan 6 FPGA, integrated with both a logic-based hardware ECU and a fully fledged processor-based electronic control unit (ECU). Results show that the platform-centric implementation generates a highly efficient core in terms of power, performance, and resource utilization. We demonstrate that the flexible extensions help enable advanced applications that integrate features such as fault tolerance, timeliness, and security, with practical case studies. This tight integration between the controller, computational functions, and flexible extensions on the controller enables enhancements that open the door for exciting applications in future vehicles.

关键词： Automotive systems field-programmable gate arrays networks

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Design of a filter bank multi-carrier system for broadband power line communications

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SIGNAL PROCESSING 2016年 128卷 57-67页

作者： Poudereux, Pablo Hernandez, Alvaro Mateos, Raul Pinto-Benel, Freddy A. Cruz-Roldan, Fernando Univ Alcala Dept Elect E-28805 Alcala De Henares Madrid Spain Univ Alcala Dept Teoria Senal & Comun E-28805 Alcala De Henares Madrid Spain

A semi-parallel architecture to implement a filter-bank multi-carrier system for broadband communications is presented. The signal processing schemes for both the transmitter and the receiver have been analyzed in terms of computational complexity, thus determining the corresponding requirements and constraints to be considered in the definition of architecture parameters, such as internal data rates or operation frequencies. Furthermore, the proposed design allows to achieve a real-time implementation of the whole transmultiplexer for broadband multi-carrier communications in a field-programmable gate Array (FPGA) device. This implementation has been carried out by means of a System-on-Chip (SoC)-based architecture, where the specific hardware for the transmultiplexer has been integrated as an advanced peripheral. For experimental tests, all the architecture description has been particularized for a transmultiplexer configuration recommended by the IEEE 1901 working group for broadband power line communications. Nevertheless, the designed architecture can be easily adapted to other options by suitably defining some generic parameters in its HDL (Hardware Description Language) specification. (C) 2016 Elsevier B.V. All rights reserved.

关键词： field-programmable gate arrays Multi-carrier communication (MCM) Broadband power-line communications Orthogonal Frequency-division multiplexing (OFDM) Filter-bank multi-carrier (FBMC)

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field-programmable gate Array-Based Multichannel Measurement System for Interrogating Fiber Bragg Grating Sensors

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IEEE SENSORS JOURNAL 2019年第15期19卷 6163-6172页

作者： Yamaguchi, Latsuya Ishihara, Keisuke Shinoda, Yukitaka Nihon Univ Dept Elect Engn Coll Sci & Technol Tokyo 1010062 Japan Nihon Univ Dept Elect Engn Grad Sch Sci & Technol Tokyo 1010062 Japan

We develop a field-programmable gate array (FPGA)-based multichannel measurement system for sensing multiplexed fiber Bragg gratings (FBGs), using a high-speed wavelength-swept laser. The wavelength-swept laser, operated with Fourier-domain mode locking (FDML), exhibits a sweep frequency of 50.7 kHz and sweep band of similar to 60 nm. A breakthrough in multichannel and real-time measurement is achieved by implementing an FPGA with unique parallel-processing circuits. This FPGA enables the implementation of a high-speed centroid-peak-detection circuit for FBG detection, which can be operated with a sampling frequency of 250 MHz. In multichannel measurement systems, the light propagating through each sensor path produces a delay, which reduces the measurement accuracy. This can be solved by implementing a delay-correction technique, which utilizes the time difference between two spectra obtained by a bidirectional scan of the FDML laser. The system is demonstrated to exhibit multichannel sensing and high measurement time resolution of 9.9 mu s, without being affected by the delay.

关键词： field-programmable gate arrays optical fiber sensors sensor systems system integration

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An embedded architecture for real-time object detection in digital images based on niching particle swarm optimization

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JOURNAL OF REAL-TIME IMAGE PROCESSING 2015年第1期10卷 75-89页

作者： Mehmood, Shahid Cagnoni, Stefano Mordonini, Monica Khan, Shoab Ahmad Ctr Adv Studies Engn Islamabad Pakistan Univ Parma Dept Informat Engn I-43100 Parma Italy

Particle swarm optimization (PSO) is an efficient population-based optimization technique. Niching is introduced into PSO to deal with multimodal problems, and converge onto the largest possible number of minima. In this paper, a niching PSO algorithm is described, which targets the imaging domain;our niching PSO enhances the fitness of a particle dynamically, based on the current position of the particle's neighbors, while also contemplating the chance of stopping exploration by halting a particle over favorable regions of the fitness landscape. It also caters for repulsion among closely located neighbors, which induces the particles to spread over the region of interest instead of converging onto a single punctual optimum. Based on this technique, an architecture is proposed and implemented for detecting objects in digital images. The new architecture, being efficient and portable, can be used in embedded computer vision and pattern recognition applications. We have assessed the architecture performance in the real-world task of detecting license plates in digital images, an instance of the more general class of object detection problems for which it has been designed. In doing so, we have compared our results with respect to both a corresponding sequential implementation and a standard computer implementation of a classical algorithm which solves the same problem.

关键词： Niching particle swarm optimization Swarm intelligence field-programmable gate arrays Object detection

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Modeling Method for Development of Digital System Algorithms Based on programmable Logic Devices

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CYBERNETICS AND SYSTEMS ANALYSIS 2020年第5期56卷 710-717页

作者： Letychevskyi, O. O. Peschanenko, V. S. Kharchenko, V. S. Volkov, V. A. Odarushchenko, O. M. Natl Acad Sci Ukraine VM Glushkov Inst Cybernet Kiev Ukraine Kherson State Univ Kherson Ukraine MM Zhukovsky Natl Aerosp Univ Kharkiv Aviat Inst Kharkiv Ukraine SPE RadiCS LLC Kropyvnytskyi Ukraine

The paper deals with state-of-the-art trends in the field of automated hardware development, specifically development of digital systems using programmable logic integrated circuits, as exemplified by field-programmable logic arrays. The paper suggests a modeling method of development using an algebraic model of design specifications, requirements and binary codes in order to apply formal methods of verification, model-based testing, as well as methods of algebraic matching. The specifications of the algebraic hardware model are behavior algebra determined on a set of actions and behaviors.

关键词： field-programmable gate arrays symbolic modeling algebraic matching behavior algebra

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Wireless baseband digital signal processing

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2000年第11期35卷 1697-1704页

作者： Zhang, H Prabhu, V George, V Wan, M Benes, M Abnous, A Rabaey, JM Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94704 USA Myricom Inc Arcadia CA 91006 USA

A heterogeneous reconfigurable platform enables the flexible implementation of baseband wireless functions at energy levels between 10 and 100 MOPS/mW, six times higher than traditional digital signal processors. A 5.2 mm x 6.7 mm prototype processor, targeted for voice compression, is implemented in a 0.25-mum 6-metal CMOS process, and consumes 1.8 mW at an average operation rate of 40 MHz. It combines an embedded microprocessor with an array of computational units of different granularities, connected by a hierarchical reconfigurable interconnect network.

关键词： digital signal processors energy conservation field-programmable gate arrays reconfigurable architectures speech coders wireless

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