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Power and area minimization for multidimensional signal processing

IEEE JOURNAL OF SOLID-STATE CIRCUITS 2007年第4期42卷 922-934页

作者： Markovic, Dejan Nikolic, Borivoje Brodersen, Robert W. Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90095 USA Univ Calif Berkeley Berkeley Wireless Res Ctr Berkeley CA 94704 USA

Sensitivity-based methodology is applied to optimization of performance, power and area across several levels of design abstraction for a complex wireless baseband signal processing algorithm. The design framework is based on a unified, block-based graphical description of the algorithm to avoid design re-entry in various phases of chip development. The use of architectural techniques for minimization of power and area for complex signal processing algorithms is demonstrated using this framework. As a proof of concept, an ASIC realization of the MIMO baseband signal processing for a multi-antenna WLAN is described. The chip implements a 4 x 4 adaptive singular value decomposition (SVD) algorithm with combined power and area minimization achieving a power efficiency of 2.1 GOPS/mW (12-bit add equivalent) in just 3.5 mm(2) in a standard 90 nm CMOS process. The computational throughput of 70 GOPS is implemented with 0.5 M cells at a 100 MHz clock and 385 mV supply, dissipating 34 mW of power. With optimal channel conditions the algorithm implemented can deliver up to 250 Mb/s over 16 sub-carriers.

关键词： circuit optimization CMOS digital integrated circuits design methodology field-programmable gate arrays matrix decomposition MIMO systems multidimensional signal processing parallel architectures pipelines sensitivity

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High resolution FPGA pulse width modulation control of full-bridge DC-DC converters

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IET CIRCUITS DEVICES & SYSTEMS 2020年第7期14卷 1110-1116页

作者： Tomov, Viktor Iliev, Ivo Krasteva, Vessela Tech Univ Sofia Dept Elect Engn & Technol 8 Kl Ohridski BlvdBl 1 Sofia Bulgaria Bulgarian Acad Sci Inst Biophys & Biomed Engn Acad G Bonchev Str Bl 105 Sofia 1113 Bulgaria

This study describes a field-programmable gate arrays (FPGAs) based technique, which aims to significantly improve the resolution of complementary drivers in full-bridge DC-DC converters. An algorithm for precise adjustment of both the duty cycle and the frequency of the pulse width modulator (PWM) is presented. It is experimentally verified by software simulation and FPGA hardware implementation. The results prove that the designed 12-bit digital PWM is able to provide switching frequency of 100 kHz in the range of 99.61 [99.51-99.70] kHz [mean value (95% confidence interval)] using clock frequency of just 160 MHz. In comparison, the conventional counter-based PWM gives the same output resolution at operating frequency of 410 MHz. In addition, the proposed algorithm is scalable and could be used to provide better resolution even at higher clock frequencies >400 MHz. For example, if phase-locked loop is 480 MHz then the conventional counter for 100 kHz PWM has a resolution slightly >12 bits, while the proposed algorithm could extend the resolution up to 14 bits. Due to the high reliability of the FPGA technology, the proposed PWM control is applicable in highly critical medical systems, such as electrosurgical devices.

关键词： PWM power convertors DC-DC power convertors field programmable gate arrays driver circuits bridge circuits PWM control full-bridge DC-DC converters field-programmable gate arrays FPGA hardware implementation digital PWM switching frequency clock frequency counter-based PWM high resolution FPGA pulse width modulation control complementary drivers software simulation phase-locked loop electrosurgical devices frequency 100 0 kHz word length 12 0 bit word length 14 0 bit frequency 99 51 kHz to 99 70 kHz frequency 160 0 MHz to 480 MHz

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A Hardware-Accelerated Quantum Monte Carlo framework (HAQMC) for N-body systems

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COMPUTER PHYSICS COMMUNICATIONS 2009年第12期180卷 2563-2573页

作者： Gothandaraman, Akila Peterson, Gregory D. Warren, G. Lee Hinde, Robert J. Harrison, Robert J. Univ Tennessee Dept Elect Engn & Comp Sci Knoxville TN 37996 USA Yeshiva Univ Dept Chem New York NY 10033 USA Univ Tennessee Dept Chem Knoxville TN 37996 USA

Interest in the study of structural and energetic properties of highly quantum clusters, such as inert gas clusters has motivated tile development of a hardware-accelerated framework for Quantum Monte Carlo simulations. In the Quantum Monte Carlo method, the properties of a system of atoms, such as the ground-state energies, are averaged over a number of iterations. Our framework is aimed at accelerating the computations in each iteration of the QMC application by offloading the calculation of properties, namely energy and trial wave function, onto reconfigurable hardware. This gives a user tile capability to run simulations for a large number of iterations, thereby reducing the statistical uncertainty in the properties, and for larger clusters. This framework is designed to run oil the Cray XD1 high performance reconfigurable computing platform, which exploits the coarse-grained parallelism of the processor along with the fine-grained parallelism of the reconfigurable computing devices available in the form of fieldprogrammable gate arrays. In this paper, we illustrate the functioning of the framework, which can be used to calculate the energies for a model cluster of helium atoms. In addition, we present the capabilities of the framework that allow the user to vary the chemical identities of the simulated atoms. Program summary Program title: Hardware Accelerated Quantum Monte Carlo (HAQMC) Catalogue identifier: AEEP _0_0 Program summary URL: http://***/summaries/AEEP_v1_*** Program obtainable from: CPC Program Library, Queen's University, Belfast, N. Ireland Licensing provisions: Standard CPC licence, http://***/licence/*** No. of lines in distributed program, including test data, etc.: 691537 No. of bytes in distributed program, including test data, etc.: 5 03 1226 Distribution format. *** Programming language: C/C++ for the QMC application, VHDL and Xilinx 8.1 ISE/EDK tools for FPGAdesigil and development Computer- Cray

关键词： Reconfigurable computing field-programmable gate arrays FPGA Cray XD1 Monte Carlo Quantum Monte Carlo

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Post-Measurement Adjustment of the Coincidence Window in Quantum Optics Experiments

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IEEE ACCESS 2021年 9卷 94010-94016页

作者： Carine, Jaime Gomez, Santiago A. Obregon, Giannini F. Gomez, Esteban S. Figueroa, Miguel Lima, Gustavo Xavier, Guilherme B. Univ Catolica Santisima Concepcion Dept Ingn Elect Concepcion 2850 Chile Univ Concepcion Dept Elect Engn 160-C Concepcion Chile Univ Concepcion Millennium Inst Res Opt Millennium Sci Initiat Program ANID 160-C Concepcion Chile Univ Concepcion Dept Fis 160-C Concepcion Chile Linkopings Univ Inst Systemtekn S-58183 Linkoping Sweden

We report on an electronic coincidence detection circuit for quantum photonic applications implemented on a field-programmable gate array (FPGA), which records each the time separation between detection events coming from single-photon detectors. We achieve a coincidence window as narrow as 500 ps with a series of optimizations on a readily-available and affordable FPGA development board. Our implementation allows real-time visualization of coincidence measurements for multiple coincidence window widths simultaneously. To demonstrate the advantage of our high-resolution visualization, we certified the generation of polarized entangled photons by collecting data from multiple coincidence windows with minimal accidental counts, obtaining a violation of the Clauser-Horne-Shimony-Holt (CHSH) Bell inequality by more than 338 standard deviations. Our results have shown the applicability of our electronic design in the field of quantum information.

关键词： field programmable gate arrays Delays Photonics Image edge detection Detectors Clocks Logic gates field-programmable gate arrays quantum information coincidence counting

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Reconfigurable architecture for real-time image compression on-board satellites

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JOURNAL OF APPLIED REMOTE SENSING 2015年第1期9卷

作者： Manthey, Kristian Krutz, David Juurlink, Ben German Aerosp Ctr DLR Inst Opt Sensor Syst Opt Sensors & Elect D-12489 Berlin Germany Tech Univ Berlin Embedded Syst Architecture D-10587 Berlin Germany

A high-speed image compression architecture with region-of-interest (ROI) support and with flexible access to compressed data based on the Consultative Committee for Space Data Systems 122.0-B-1 image data compression standard is presented. Modifications of the standard permit a change of compression parameters and the reorganization of the bit stream after compression. An additional index of the compressed data is created, which renders it possible to locate individual parts of the bit stream. On request, stored images can be reassembled according to the application's needs and as requested by the ground station. Interactive transmission of the compressed data is possible such that overview images can be transmitted first followed by detailed information for the ROI. The architecture was implemented for a Xilinx Virtex-5QV and a single instance is able to compress images at a rate of 200 Mpx/s at a clock frequency of 100 MHz. The design ensures that all parts of the system have a high utilization and parallelism. A Virtex-5QV allows compression of images with a width of up to 4096 px without external memory. The power consumption of the architecture is similar to 4 W. This example is one of the fastest implementations yet reported and sufficient for future high-resolution imaging systems. (C) 2015 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： remote sensing image data compression field-programmable gate arrays focal plane assembly Consultative Committee for Space Data Systems Earth observation

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Architecture and Application Co-Design for Beyond-FPGA Reconfigurable Acceleration Devices

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IEEE ACCESS 2022年 10卷 95067-95082页

作者： Boutros, Andrew Nurvitadhi, Eriko Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada Intel Corp Programmable Solut Grp Santa Clara CA 95054 USA

In recent years, field-programmable gate arrays (FPGAs) have been increasingly deployed in datacenters as programmable accelerators that can offer software-like flexibility and custom-hardware-like efficiency for key datacenter workloads. To improve the efficiency of FPGAs for these new datacenter use cases and data-intensive applications, a new class of reconfigurable acceleration devices (RADs) is emerging. In these devices, the FPGA fine-grained reconfigurable fabric is a component of a bigger monolithic or multi-die system-in-package that can incorporate general-purpose software-programmable cores, domain-specialized accelerator blocks, and high-performance networks-on-chip (NoCs) for efficient communication between these system components. The integration of all these components in a RAD results in a huge design space and requires re-thinking the implementation of applications that need to be migrated from conventional FPGAs to these novel devices. In this work, we introduce RAD-Sim, an architecture simulator that allows rapid design space exploration for RADs and facilitates the study of complex interactions between their various components. We also present a case study that highlights the utility of RAD-Sim in re-designing applications for these novel RADs by mapping a state-of-the-art deep learning (DL) inference FPGA overlay to different RAD instances. Our case study illustrates how RAD-Sim can capture a wide variety of reconfigurable architectures, from conventional FPGAs to devices augmented with hard NoCs, specialized matrix-vector blocks, and 3D-stacked multi-die devices. In addition, we show that our tool can help architects evaluate the effect of specific RAD architecture parameters on end-to-end workload performance. Through RAD-Sim, we also show that novel RADs can potentially achieve 2.6x better performance on average compared to conventional FPGAs in the key DL application domain.

关键词： Deep learning field-programmable gate arrays hardware acceleration network-on-chip reconfigurable computing

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Using Data Contention in Dual-ported Memories for Security Applications

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2012年第1期67卷 15-29页

作者： Gueneysu, Tim Ruhr Univ Bochum Horst Gortz Inst IT Secur Bochum Germany

field programmable gate arrays (FPGA) provide the invaluable feature of dynamic hardware reconfiguration by loading configuration bit files. However, this flexibility also opens up the threat of theft of Intellectual Property (IP) since these configuration files can be easily extracted and cloned. In this context, the ability to bind an application configuration to a specific device is an important step to prevent product counterfeiting. Furthermore, such a technology can also enable advanced business models such as device-specific feature activation. In this work, we present a new technique to generate entropy on FPGA device-based on data contention in the hardware circuitry. For this entropy, we use the output of intentionally generated write collisions in synchronous dual-ported block RAMs (BRAM). We show that the parts of this output generated by such write collisions can be either probabilistic but also deterministic and device-specific. The characteristics of such an entropy source can be used for a large variety of security applications, such as chip identification and device authentication. In addition to that, we also propose a solution to efficiently create cryptographic keys on-chip at runtime. As a last contribution, we eventually present a strategy how to transform this entropy source into a circuit for True Random Number Generation (TRNG).

关键词： Write collisions field-programmable gate arrays Security applications Device identification Random number generation Metastability Data contention Dual-ported block RAM

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Correlation-Based Detection of OFDM Signals in the Angular Domain

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IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY 2012年第3期61卷 951-958页

作者： Turunen, Vesa Kosunen, Marko Vaarakangas, Mikko Ryynanen, Jussi Aalto Univ Dept Micro & Nanosci Espoo 00076 Finland Nokia Res Ctr Helsinki 00180 Finland

Spectrum sensing is an essential part of future cognitive radios, as the spectrum sensor provides information about the utilization of the surrounding radio spectrum. Several approaches to implementing spectrum sensing have been proposed in the literature, one of them being the class of feature detectors. Cyclostationary feature detectors are, in general, considered to be superior in performance but suffer from high implementation complexity. Therefore, most studies still utilize energy detectors, which may not reach the performance requirements set for practical implementations. This paper presents angular domain feature detection algorithms that are based on cyclostationary properties. Angular domain signal processing is shown to simplify the implementation considerably while preserving comparable performance. Moreover, a new detection algorithm that leads to multiplier-free implementation and reduces the memory requirements, compared with any previous approaches, is proposed.

关键词： Autocorrelation cognitive radio detection algorithms digital signal processing field-programmable gate arrays orthogonal frequency-division multiplex (OFDM)

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Fiber-on-Chip: Digital Emulation of Channel Impairments for Real-Time DSP Evaluation

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JOURNAL OF LIGHTWAVE TECHNOLOGY 2023年第3期41卷 888-896页

作者： Borjeson, Erik Larsson-Edefors, Per Chalmers Univ Technol Dept Comp Sci & Engn S-41296 Gothenburg Sweden

We describe the Fiber-on-Chip (FoC) approach to verification of digital signal processing (DSP) circuits, where digital models of a fiber-optic communication system are implemented in the same hardware as the DSP under test. The approach can enable cost-effective long-term DSP evaluations without the need for complex optical-electronic testbeds with high-speed interfaces, shortening verification time and enabling deep bit-error rate evaluations. Our FoC system currently contains a digital model of a transmitter generating a pseudo-random bitstream and a digital model of a channel with additive white Gaussian noise, phase noise and polarization-mode dispersion. In addition, the FoC system contains digital features for real-time control of channel parameters, using low-speed communication interfaces, and for autonomous real-time analysis, which enable us to batch multiple unsupervised emulations on the same hardware. The FoC system can target both field-programmable gate arrays, for fast evaluation of fixed-point logic, and application-specific integrated circuits, for accurate power dissipation measurements.

关键词： field programmable gate arrays Hardware Optical transmitters Integrated circuit modeling Emulation Real-time systems Pipeline processing Application-specific integrated circuits channel models digital signal processing field-programmable gate arrays optical fiber communication very large-scale integration

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System-Level, FPGA-Based, Real-Time Simulation of Ship Power Systems

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IEEE TRANSACTIONS ON ENERGY CONVERSION 2017年第2期32卷 737-747页

作者： Milton, Matthew Benigni, Andrea Bakos, Jason Univ South Carolina Dept Elect Engn Columbia SC 29208 USA Univ South Carolina Dept Comp Sci & Engn Columbia SC 29208 USA

In this paper, we present a scalable approach for real-time simulation of ship power systems with high-frequency power electronics converters (100-200 kHz). The proposed approach is based on the latency-based linear multistep compound method and relies on field-programmable gate array (FPGA) execution. Several examples of increasing dimension and complexity are used to evaluate the scalability-both of in terms of computational delay and of resources usage-of the proposed approach. Real-time execution with a 50 ns time step is achieved for all the examples considered.

关键词： field-programmable gate arrays parallel algorithms power system simulation power electronics real time systems

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