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检索条件"主题词=Field-Programmable Gate Arrays"
452 条 记 录,以下是81-90 订阅
A novel high speed Artificial Neural Network-based chaotic True Random Number Generator on field programmable gate Array
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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2019年 第3期47卷 365-378页
作者: Alcin, Murat Koyuncu, Ismail Tuna, Murat Varan, Metin Pehlivan, Ihsan Afyon Kocatepe Univ Fac Technol Dept Mechatron Engn TR-03200 Afyon Turkey Afyon Kocatepe Univ Fac Technol Dept Elect & Elect Engn Afyon Turkey Kirklareli Univ Tech Sci Vocat Sch Dept Elect Kirklareli Turkey Sakarya Univ Fac Technol Dept Elect Elect Engn Sakarya Turkey
It is well observed that cryptographic applications have great challenges in guaranteeing high security as well as high throughput. Artificial neural network (ANN)-based chaotic true random number generator (TRNG) str... 详细信息
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Scalable register bypassing for FPGA-based processors
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MICROPROCESSORS AND MICROSYSTEMS 2009年 第7-8期33卷 441-452页
作者: Kavvadias, Nikolaos Nikolaidis, Spiridon Aristotle Univ Thessaloniki Dept Phys Sect Elect & Comp Thessaloniki 54124 Greece
In this paper, a scalable scheme, configurable via register-transfer level parameters, for full register bypassing in a modern embedded processor architecture, termed ByoRISC, is presented. The register bypassing spec... 详细信息
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Scheduling configuration memory error checks to improve the reliability of FPGA-based systems
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IET COMPUTERS AND DIGITAL TECHNIQUES 2019年 第3期13卷 154-165页
作者: Nguyen Tran Huu Nguyen Cetin, Ediz Diessel, Oliver Ho Chi Minh City Univ Technol VNU HCM Sch Comp Sci & Engn 268 Ly Thuong Kiet Ho Chi Minh City Vietnam Macquarie Univ Sch Engn Sydney NSW 2109 Australia UNSW Sydney Sch Comp Sci & Engn Sydney NSW 2052 Australia
field-programmable gate arrays are susceptible to radiation-induced single event upsets. These are commonly dealt with using triple modular redundancy (TMR) and module-based configuration memory error recovery (MER). ... 详细信息
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The design of an SRAM-based field-programmable gate array -: Part I:: Architecture
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1999年 第2期7卷 191-197页
作者: Chow, P Seo, SO Rose, J Chung, K Páez-Monzón, G Rahardja, I ATI Technol Thornhill ON L3T 7N6 Canada Xilinx Toronto Dev Ctr Toronto ON M5S 2T9 Canada Natl Semicond Corp Santa Clara CA 95052 USA Aristo Technol Inc Cupertino CA 95104 USA
field-programmable gate arrays (FPGA's) are now widely used for the implementation of digital systems, acid many commercial architectures are available. Although the literature and data books contain detailed desc... 详细信息
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Tradeoff literals against support for logic synthesis of LUT-based FPGAs
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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 1996年 第2期143卷 111-119页
作者: Lu, A Dagless, E Saul, J UNIV OXFORD COMP LABOXFORD OX1 3QDENGLAND
The paper deals with logic synthesis of lookup-table (LUT) based field-programmable gate arrays (FPGAs). Because each LUT can implement any k input Boolean function with the same area cost, the optimisation criterion ... 详细信息
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Symbolic system-level design methodology for multi-mode reconfigurable systems
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DESIGN AUTOMATION FOR EMBEDDED SYSTEMS 2013年 第2期17卷 343-375页
作者: Wildermann, Stefan Reimann, Felix Ziener, Daniel Teich, Juergen Univ Erlangen Nurnberg D-91054 Erlangen Germany
Modern embedded systems provide a variety of functionality as operational modes, each corresponding to a mutually exclusive phase of operation. This paper provides a system level design methodology tailored for such m... 详细信息
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A 47.14-$\mu\text{W}$ 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications
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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2019年 第11期54卷 2991-3004页
作者: Natsui, Masanori Suzuki, Daisuke Tamakoshi, Akira Watanabe, Toshinari Honjo, Hiroaki Koike, Hiroki Nasuno, Takashi Ma, Yitao Tanigawa, Takaho Noguchi, Yasuo Yasuhira, Mitsuo Sato, Hideo Ikeda, Shoji Ohn, Hideo Endoh, Tetsuo Hanyu, Takahiro Tohoku Univ Res Inst Elect Commun Lab Brainware Syst Sendai Miyagi 9808577 Japan Tohoku Univ Ctr Spintron Integrated Syst Sendai Miyagi 9808577 Japan Tohoku Univ Ctr Innovat Integrated Elect Syst Sendai Miyagi 9808577 Japan Tohoku Univ Res Inst Elect Commun Sendai Miyagi 9808577 Japan Tohoku Univ Ctr Innovat Integrated Elect Syst Sendai Miyagi 9808572 Japan Tohoku Univ Ctr Spintron Integrated Syst Grad Sch Engn Sendai Miyagi 9808572 Japan Tohoku Univ Ctr Spintron Integrated Syst Sendai Miyagi 9808572 Japan Tohoku Univ Ctr Spintron Res Network Sendai Miyagi 9808572 Japan Tohoku Univ Res Inst Elect Commun Sendai Miyagi 9808572 Japan Tohoku Univ WPI Adv Inst Mat Res Sendai Miyagi 9808577 Japan Tohoku Univ Ctr Spintron Res Network Sendai Miyagi 9808577 Japan Tohoku Univ Grad Sch Engn Sendai Miyagi 9808572 Japan
The demand for energy-efficient, high-performance microcontroller units (MCUs) for the use in power-supply-critical Internet-of-Things (IoT) sensor-node applications has witnessed a substantial increase. In response, ... 详细信息
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System-level performance evaluation of reconfigurable processors
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MICROPROCESSORS AND MICROSYSTEMS 2005年 第2-3期29卷 63-73页
作者: Enzler, R Plessl, C Platzner, M ETH Zentrum Elect Lab Swiss Fed Inst Technol ETH CH-8092 Zurich Switzerland ETH Zentrum Comp Engn & Networks Lab Swiss Fed Inst Technol ETH CH-8092 Zurich Switzerland
Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving increased attention. The design of such a hybrid reconfigurable process... 详细信息
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New Hardware Architectures for Montgomery Modular Multiplication Algorithm
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IEEE TRANSACTIONS ON COMPUTERS 2011年 第7期60卷 923-936页
作者: Huang, Miaoqing Gaj, Kris El-Ghazawi, Tarek 1 Univ Arkansas Dept Comp Sci & Comp Engn Fayetteville AR 72701 USA George Mason Univ Dept Elect & Comp Engn Fairfax VA 22030 USA George Washington Univ Dept Elect & Comp Engn Washington DC 20052 USA
Montgomery modular multiplication is one of the fundamental operations used in cryptographic algorithms, such as RSA and Elliptic Curve Cryptosystems. At CHES 1999, Tenca and Koc proposed the Multiple-Word Radix-2 Mon... 详细信息
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Real-Time Nonlinear Magnetic Equivalent Circuit Model of Induction Machine on FPGA for Hardware-in-the-Loop Simulation
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IEEE TRANSACTIONS ON ENERGY CONVERSION 2016年 第2期31卷 520-530页
作者: Tavana, Nariman Roshandel Dinavahi, Venkata Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2V4 Canada
Real-time simulation of induction machine plays a crucial role in hardware-in-the-loop (HIL) scenarios. Due to the key advantages offered by magnetic equivalent circuits (MEC) for modeling induction machines compared ... 详细信息
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