Dynamic receive beamforming (DRBF) is challenging for field-programmablegate array (FPGA)-based ultrasound (US) imaging because it is computationally intense. Work has been done to either simplify the delay calculati...
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ISBN:
(纸本)9781538633830
Dynamic receive beamforming (DRBF) is challenging for field-programmablegate array (FPGA)-based ultrasound (US) imaging because it is computationally intense. Work has been done to either simplify the delay calculation or precalculate the delays and store them on the FPGA. The former sacrifices image quality and the latter is challenged by limited memory resource on the FPGA. In this work, we report on the design of a compact US imaging system for capacitive micromachined ultrasonic transducer (CMUT) arrays implemented on an FPGA evaluation board. The system features high frequency and high frame rate. It transmits ultrasound pulses centered at up to 20 MHz and can receive ultrasound echo signals up to 60 MHz. When working with a 16-element 2.48-mm CMUT array centered at 4.5 MHz, the system can perform conventional phased array (CPA) imaging at 170 FPS from a depth of 2.48 mm to 17.34 mm within a 90 degrees sector. The system features full DRBF for every pixel.
We detail a field-programmablegate array (FPGA) based implementation of linear programming (LP) decoding. LP decoding frames error correction as an optimization problem. This is in contrast to variants of belief prop...
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ISBN:
(纸本)9781509041176
We detail a field-programmablegate array (FPGA) based implementation of linear programming (LP) decoding. LP decoding frames error correction as an optimization problem. This is in contrast to variants of belief propagation (BP) that view error correction as a problem of graphical inference. LP decoding, when implemented with standard LP solvers, does not easily scale to the block-lengths of modern error-correction codes. This is the main challenge we surmount in this paper. In earlier work we demonstrated how to draw on decomposition methods from optimization theory to build an LP decoding solver competitive with BP, in terms of both performance and speed, but only in double-precision floating point. In this paper we translate the novel computational primitives of our new LP decoding technique into fixed-point. Using our FPGA implementation, we demonstrate that error-rate performance very close to double-precision is possible with 10-bit fixed-point messages.
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