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Real-Time Nonlinear Magnetic Equivalent Circuit Model of Induction Machine on FPGA for Hardware-in-the-Loop Simulation

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IEEE TRANSACTIONS ON ENERGY CONVERSION 2016年第2期31卷 520-530页

作者： Tavana, Nariman Roshandel Dinavahi, Venkata Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2V4 Canada

Real-time simulation of induction machine plays a crucial role in hardware-in-the-loop (HIL) scenarios. Due to the key advantages offered by magnetic equivalent circuits (MEC) for modeling induction machines compared with finite element analysis and electric equivalent circuits in terms of computational expense and achieved accuracy, this paper proposes a real-time nonlinearMECof the induction machine. Themodel is emulated in real time on the field-programmable gate array (FPGA) by exploiting the parallel hardware architecture and fully pipelined arithmetic processing. The performance of the FPGA-based real-time emulated induction machine model is investigated and compared with the behavior of an experimental setup of induction machine and finite element results to demonstrate the effectiveness and accuracy of proposed approach for HIL applications.

关键词： Electrical machines field-programmable gate arrays finite element method hardware-in-the-loop simulation induction machine magnetic equivalent circuit real-time systems

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An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2016年第1期24卷 178-191页

作者： Bsoul, Assem A. M. Wilton, Steven J. E. Tsoi, Kuen Hung Luk, Wayne Univ British Columbia Dept Elect & Comp Engn Vancouver BC V6T 1Z4 Canada Univ London Imperial Coll Sci Technol & Med Dept Comp London SW7 2AZ England

Leakage power is an important component of the total power consumption in field-programmable gate arrays (FPGAs) built using 90-nm and smaller technology nodes. Power gating was shown to be effective at reducing the leakage power. Previous techniques focus on turning OFF unused FPGA resources at configuration time;the benefit of this approach depends on resource utilization. In this paper, we present an FPGA architecture that enables dynamically controlled power gating, in which FPGA resources can be selectively powered down at run-time. This could lead to significant overall energy savings for applications having modules with long idle times. We also present a CAD flow that can be used to map applications to the proposed architecture. We study the area and power tradeoffs by varying the different FPGA architecture parameters and power gating granularity. The proposed CAD flow is used to map a set of benchmark circuits that have multiple power-gated modules to the proposed architecture. Power savings of up to 83% are achievable for these circuits. Finally, we study a control system of a robot that is used in endoscopy. Using the proposed architecture combined with clock gating results in up to 19% energy savings in this application.

关键词： Computer aided design field-programmable gate arrays power gating static/leakage power

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Hardware-based linear programming decoding via the alternating direction method of multipliers

Hardware-based linear programming decoding via the alternati...

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IEEE International Conference on Acoustics, Speech and Signal Processing

作者： Mitchell Wasson Mario Milicevic Stark C. Draper Glenn Gulak University of Toronto Edward S. Rogers Sr. Department of Electrical and Computer Engineering Canada

ISBN: (纸本)9781509041183

We detail a field-programmable gate array (FPGA) based implementation of linear programming (LP) decoding. LP decoding frames error correction as an optimization problem. This is in contrast to variants of belief propagation (BP) that view error correction as a problem of graphical inference. LP decoding, when implemented with standard LP solvers, does not easily scale to the block-lengths of modern error-correction codes. This is the main challenge we surmount in this paper. In earlier work we demonstrated how to draw on decomposition methods from optimization theory to build an LP decoding solver competitive with BP, in terms of both performance and speed, but only in double-precision floating point. In this paper we translate the novel computational primitives of our new LP decoding technique into fixed-point. Using our FPGA implementation, we demonstrate that error-rate performance very close to double-precision is possible with 10-bit fixed-point messages.

关键词： Linear programming decoding alternating direction method of multipliers field-programmable gate arrays low-density parity-check codes lowering error floors

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High-Time-Resolution Nuclear Magnetic Resonance With Nitrogen-Vacancy Centers

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IEEE MAGNETICS LETTERS 2016年 7卷 1-5页

作者： Qin, Xi Xie, Yijin Li, Rui Rong, Xing Kong, Xi Shi, Fazhan Wang, Pengfei Du, Jiangfeng Hefei Natl Lab Phys Sci Microscale Hefei 230026 Anhui Peoples R China Univ Sci & Technol China Dept Modern Phys Hefei 230026 Anhui Peoples R China Synerget Innovat Ctr Quantum Informat & Quantum P Hefei 230026 Anhui Peoples R China

We present a field-programmable gate array (FPGA)-based solution for high-time-resolution nanoscale nuclear magnetic resonance, with nitrogen-vacancy centers as a probe. The Xilinx FPGA is used to implement a high-performance pulse generator, which contributes to high-precision measurement for the nuclear magnetic resonance (NMR) signal. The pulse generator outputs continuous pulses with a time resolution of 50 ps and a dynamic range of 5 ns to 2.68 s. The central control and the readout logics for the NMR experiment are fully implemented in the FPGA. We observed nanoscale NMR signals of hydrogen atoms by measuring the period of the Larmor precession with a 50 ps time resolution. Furthermore, we demonstrate the ability to distinguish signals of adjacent frequencies, which is a great advantage in high-resolution analysis for the nanoscale NMR.

关键词： Magnetic instruments field-programmable gate arrays nitrogen-vacancy centers nuclear spin

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A field-programmable gate array implementation of a real-time nonlinear Runge-Kutta model predictive control

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TRANSACTIONS OF THE INSTITUTE OF MEASUREMENT AND CONTROL 2016年第5期38卷 555-564页

作者： Iplikci, Serdar Bahtiyar, Bedri Pamukkale Univ Dept Elect & Elect Engn Merkez Denizli Turkey Pamukkale Univ Elect & Energy Dept Merkez Denizli Turkey

This paper presents the very first field-programmable gate array (FPGA) implementation of the Runge-Kutta model predictive control (RKMPC) mechanism to the real-time experimental electromagnetic levitation system, which is an unstable nonlinear continuous-time system with a very small time constant. In the control mechanism, the so called Runge-Kutta model of the nonlinear system is employed as an approximate discrete-time model of the system and used in the model predictive control loop for prediction and derivative calculation purposes. Experimental results have shown the effectiveness of the proposed implementation under different control conditions. Moreover, the RKMPC has been compared to a conventional nonlinear model predictive control (NMPC) method to show the advantages of the RKMPC over the NMPC.

关键词： Nonlinear model based control field-programmable gate arrays optimal control model predictive control embedded systems

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1 Tb/s Anti-Replay Protection with 20-port On-Chip RAM Memory in FPGAs

1 Tb/s Anti-Replay Protection with 20-port On-Chip RAM Memor...

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International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Buhrow, Benjamin R. Goetzinger, William J. Gilbert, Barry K. Mayo Clin Special Purpose Processor Dev Grp Rochester MN 55905 USA

ISBN: (纸本)9781509037070

As network data rates advance toward 1 Tb/s, hardware-based implementations of anti-replay offer desirable tradeoffs over software. However, internal logic busses in FPGAs are becoming wider (512+ bits) and segmented (more than one packet per clock cycle) to accommodate increased network data rates. Such busses are challenging for applications such as anti-replay that require read-modify-write operations to a coherent database on each packet arrival. In this paper we present an FPGA-targeted pipelined anti-replay design capable of accommodating 1024 IPsec tunnels at 1 Tb/s data rate. The novel design is enabled by fast on-chip block RAMs in a xcvu190 Virtex Ultrascale FPGA that are used to construct a 20-port RAM memory operating at 400 MHz with over 5 Tb/s of peak bandwidth. Custom single-clock write-combining techniques are described that accommodate multiple concurrent updates to the same database address. We also investigate the limits of capacity and concurrency for the anti-replay application.

关键词： 400 GbE high-speed networks field-programmable gate arrays anti-replay segmented bus multi-port RAM

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Novo-G#: a multidimensional torus-based reconfigurable cluster for molecular dynamics

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2016年第8期28卷 2374-2393页

作者： Lawande, Abhijeet G. George, Alan D. Lam, Herman Univ Florida Dept Elect & Comp Engn NSF Ctr High Performance Reconfigurable Comp CHRE Gainesville FL 32611 USA

Molecular dynamics (MD) is a large-scale, communication-intensive problem that has been the subject of high-performance computing research and acceleration for years. Not surprisingly, the most success in accelerating MD comes from specialized systems such as the Anton machine. In this paper, we describe Novo-G# (novo-jee-sharp), a multi-node reconfigurable system designed for the acceleration of communication-intensive scientific problems in general, and MD in particular. This system provides a high-bandwidth, low-latency 3D torus network to allow direct communication between kernels running on multiple field-programmable gate arrays. We also present a performance model for Novo-G# running the 3D Fast Fourier Transform (FFT) kernel that forms the core of MD simulations. We validate the model against published Anton performance data and through initial hardware experiments on Novo-G#. Finally, through simulation studies, we show that this system at scale performs better than specialized systems like Anton and outperforms established CPU-based clusters like Blue Gene/Q by an order of magnitude for the 3D FFT kernel, with greater flexibility and lower costs. Copyright (c) 2015John Wiley & Sons, Ltd.

关键词： high-performance computing modeling computer simulation reconfigurable architectures field-programmable gate arrays

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Performance Evaluation of Parallel Delay-and-Sum Algorithm Based on SuperVessel High-Performance Cloud Computing 2

Performance Evaluation of Parallel Delay-and-Sum Algorithm B...

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2nd IEEE International Conference on Computer and Communications (ICCC)

作者： Chen, Junying Zhou, Shunfeng Min, Huaqing South China Univ Technol Sch Software Engn Guangzhou Key Lab Robot & Intelligent Software Guangzhou 510006 Guangdong Peoples R China

ISBN: (纸本)9781467390262

Delay-and-sum algorithm is a widespread algorithm used in various typical applications, such as medical ultrasound imaging, radar signal emission and reception, antenna directional signal formation, and so on. It is not a typical computationally demanding algorithm, but under new circumstance, for example medical imaging cloud service, its calculation speed should be increased so as to meet the cloud network data communication speed requirements. The conventional cloud infrastructures using central processing units as prime computing resources are not adequate for the fast image formation process. Therefore, SuperVessel cloud with heterogeneous field-programmable gate arrays as accelerators was used as the implementation platform for the parallel delay-and-sum algorithm in this paper. The computing speed of the high-performance SuperVessel heterogeneous implementation is 30 times faster than the computing speed of the algorithm implementation on a central processing unit, including the data transfer time between the central processing unit and the field-programmable gate array.

关键词： heterogeneous acceleration parallel delay-andsum high-performance cloud computing field-programmable gate arrays

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Just In Time Assembly (JITA) - A Run Time Interpretation Approach for Achieving Productivity of Creating Custom Accelerators in FPGAs

Just In Time Assembly (JITA) - A Run Time Interpretation App...

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作者： Ma, Sen University of Arkansas

学位级别：Ph.D.

The reconfigurable computing community has yet to be successful in allowing programmers to access FPGAs through traditional software development flows. Existing barriers that prevent programmers from using FPGAs include: 1) knowledge of hardware programming models, 2) the need to work within the vendor specific CAD tools and hardware synthesis. This thesis presents a series of published papers that explore different aspects of a new approach being developed to remove the barriers and enable programmers to compile accelerators on next generation reconfigurable manycore architectures. The approach is entitled Just In Time Assembly (JITA) of hardware accelerators. The approach has been defined to allow hardware accelerators to be built and run through software compilation and run time interpretation outside of CAD tools and without requiring each new accelerator to be synthesized. The approach advocates the use of libraries of pre-synthesized components that can be referenced through symbolic links in a similar fashion to dynamically linked software libraries. Synthesis still must occur but is moved out of the application programmers software flow and into the initial coding process that occurs when programming patterns that define a Domain Specific Language (DSL) are first coded. Programmers see no difference between creating software or hardware functionality when using the DSL. A new run time interpreter is introduced to assemble the individual pre-synthesized hardware accelerators that comprise the accelerator functionality within a configurable tile array of partially reconfigurable slots at run time. Quantitative results are presented that compares utilization, performance, and productivity of the approach to what would be achieved by full custom accelerators created through traditional CAD flows using hardware programming models and passing through synthesis.

关键词： Applied sciences Custom accelerators field-programmable gate arrays Just in time Productivity Run time interpretation

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First Steps Towards Designing a Compact Language for the Description of Logic Circuits 11

First Steps Towards Designing a Compact Language for the Des...

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IEEE 11th International Conference on Communications (COMM)

作者： Birleanu, Florin-Marian Enache, Bogdan-Adrian Alexandru, Magdalena Univ Pitesti Dept Elect Comp Sci & Elect Engn Pitesti Romania

ISBN: (纸本)9781467381970

The paper introduces a new hardware description language, especially designed to be extremely concise compared to the VHDL language. Its purpose is to allow the designer to tackle the problem of digital circuit prototyping in a faster, more compact, uniform and higher-level manner. The proposed language reduces the syntax redundancy and facilitates the rapid description of frequently used functionalities. Examples of using the new language arc presented, as well as some guidelines for translating it to VHDL.

关键词： logic circuit design hardware description language field-programmable gate arrays programming language translation

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