The reconfigurable computing community has yet to be successful in allowing programmers to access FPGAs through traditional software development flows. Existing barriers that prevent programmers from using FPGAs inclu...
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The reconfigurable computing community has yet to be successful in allowing programmers to access FPGAs through traditional software development flows. Existing barriers that prevent programmers from using FPGAs include: 1) knowledge of hardware programming models, 2) the need to work within the vendor specific CAD tools and hardware synthesis. This thesis presents a series of published papers that explore different aspects of a new approach being developed to remove the barriers and enable programmers to compile accelerators on next generation reconfigurable manycore architectures. The approach is entitled Just In Time Assembly (JITA) of hardware accelerators. The approach has been defined to allow hardware accelerators to be built and run through software compilation and run time interpretation outside of CAD tools and without requiring each new accelerator to be synthesized. The approach advocates the use of libraries of pre-synthesized components that can be referenced through symbolic links in a similar fashion to dynamically linked software libraries. Synthesis still must occur but is moved out of the application programmers software flow and into the initial coding process that occurs when programming patterns that define a Domain Specific Language (DSL) are first coded. Programmers see no difference between creating software or hardware functionality when using the DSL. A new run time interpreter is introduced to assemble the individual pre-synthesized hardware accelerators that comprise the accelerator functionality within a configurable tile array of partially reconfigurable slots at run time. Quantitative results are presented that compares utilization, performance, and productivity of the approach to what would be achieved by full custom accelerators created through traditional CAD flows using hardware programming models and passing through synthesis.
The paper introduces a new hardware description language, especially designed to be extremely concise compared to the VHDL language. Its purpose is to allow the designer to tackle the problem of digital circuit protot...
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ISBN:
(纸本)9781467381970
The paper introduces a new hardware description language, especially designed to be extremely concise compared to the VHDL language. Its purpose is to allow the designer to tackle the problem of digital circuit prototyping in a faster, more compact, uniform and higher-level manner. The proposed language reduces the syntax redundancy and facilitates the rapid description of frequently used functionalities. Examples of using the new language arc presented, as well as some guidelines for translating it to VHDL.
NASA Technical Reports Server (Ntrs) 20150021506: Intelligent Hardware-Enabled Sensor and Software Safety and Health Management for Autonomous Uas by NASA Technical Reports Server (Ntrs); NASA Technical Reports Server...
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