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Wake-Up-Word Feature Extraction on FPGA

World Journal of Engineering and Technology 2014年第1期2卷 1-12页

作者： Veton ZKepuska Mohamed MEljhani Brian HHight Electrical&Computer Engineering Department Florida Institute of TechnologyMelbourneUSA

Wake-Up-Word Speech Recognition task (WUW-SR) is a computationally very demand, particularly the stage of feature extraction which is decoded with corresponding Hidden Markov Models (HMMs) in the back-end stage of the WUW-SR. The state of the art WUW-SR system is based on three different sets of features: Mel-Frequency Cepstral Coefficients (MFCC), Linear Predictive Coding Coefficients (LPC), and Enhanced Mel-Frequency Cepstral Coefficients (ENH_MFCC). In (front-end of Wake-Up-Word Speech Recognition System Design on FPGA) [1], we presented an experimental FPGA design and implementation of a novel architecture of a real-time spectrogram extraction processor that generates MFCC, LPC, and ENH_MFCC spectrograms simultaneously. In this paper, the details of converting the three sets of spectrograms 1) Mel-Frequency Cepstral Coefficients (MFCC), 2) Linear Predictive Coding Coefficients (LPC), and 3) Enhanced Mel-Frequency Cepstral Coefficients (ENH_MFCC) to their equivalent features are presented. In the WUW- SR system, the recognizer’s frontend is located at the terminal which is typically connected over a data network to remote back-end recognition (e.g., server). The WUW-SR is shown in Figure 1. The three sets of speech features are extracted at the front-end. These extracted features are then compressed and transmitted to the server via a dedicated channel, where subsequently they are decoded.

关键词： Speech Recognition System Feature Extraction Mel-Frequency Cepstral Coefficients Linear Predictive Coding Coefficients Enhanced Mel-Frequency Cepstral Coefficients Hidden Markov Models field-programmable gate arrays

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A scalable architecture for Variable Block Size Motion Estimation on field-programmable gate arrays

A scalable architecture for Variable Block Size Motion Estim...

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Canadian Conference on Electrical and Computer Engineering

作者： Moorthy, Theepan Ye, Andy Ryerson Univ Dept Elect & Comp Engn Toronto ON M5B 2K3 Canada

ISBN: (纸本)9781424416424

The flexibility of field-programmable gate arrays (FPGAs) encourages design reuse and can greatly enhance the upgradability of digital systems. This flexibility is particularly useful in the design of highly flexible video encoding systems that can accommodate a multitude of existing standards as well as the rapid emergence of new standards. In this paper, we investigate the use of FPGAs in the design of a highly scalable Variable Block Size Motion Estimation (VBSME) architecture for the H.264/AVC video encoding standard. The scalability of the architecture allows one to incorporate the system into low cost single FPGA solutions for low resolution encoding applications as well as into high performance multi-FPGA solutions targeting high-resolution video encoding applications. To overcome the performance gap between FPGAs and Application Specific Integrated Circuits (ASICs), our algorithm intelligently increases its parallelism as the design scales while minimizing the use of memory bandwidth. The core computing unit of the architecture is implemented on FPGAs and its performance is reported in this paper. It is shown that the computing unit is able to achieve real-time 40 fps performance for 640x480 resolution VGA video while incurring only 4% device utilization on a Xilinx XC5VLX330 (Virtex-5) FPGA. With 8 computing units (at 36% device utilization), the architecture is able to achieve real-time 45 fps performance for encoding full 1920x1088 progressive HDTV video.

关键词： Variable Block Size Motion Estimation H.264/AVC field-programmable gate arrays

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Symbolic system-level design methodology for multi-mode reconfigurable systems

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DESIGN AUTOMATION FOR EMBEDDED SYSTEMS 2013年第2期17卷 343-375页

作者： Wildermann, Stefan Reimann, Felix Ziener, Daniel Teich, Juergen Univ Erlangen Nurnberg D-91054 Erlangen Germany

Modern embedded systems provide a variety of functionality as operational modes, each corresponding to a mutually exclusive phase of operation. This paper provides a system level design methodology tailored for such multi-mode systems. By incorporating knowledge about the temporal behavior, it is possible to share hardware by means of partial reconfiguration on sophisticated field programmable gate arrays (FPGAs), and thus, reduce costs and improve performance. The presented methodology is based on an exploration model, which specifies the temporal behavior of the system functionality as well as the architectural characteristics of nowadays reconfigurable technology. We develop a symbolic encoding of this system specification, which enables unified system synthesis by applying sophisticated optimization techniques to perform allocation, binding, placement of partially reconfigurable modules, and routing the on-chip communication. The presented system-level design methodology complies with the state-of-the-art synthesis tools and communication technologies for partially reconfigurable systems. We demonstrate this by experiments on test cases from the image processing domain applying state-of-the-art technology. The results give evidence of the efficiency of the methodology and show the superiority in terms of runtime and quality of the found solutions compared to existing system-level synthesis approaches.

关键词： Design space exploration System level design Partial reconfiguration field-programmable gate arrays

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Modular Design of Fully Pipelined Reduction Circuits on FPGAs

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2013年第9期24卷 1818-1826页

作者： Huang, Miaoqing Andrews, David Univ Arkansas Dept Comp Sci & Comp Engn Fayetteville AR 72701 USA

Fast and efficient reduction circuits are critical for a broad range of scientific and embedded system applications. High throughput reduction circuits are typically hand designed for specific vector lengths. These circuits need to be modified when the set lengths are changed. In this paper, we present a new design approach that can handle any set length or combination of different consecutive set lengths without stalling and generates in-order results. The flexibility of the design allows it to be used for any reduction operations, such as floating-point addition and multiplication. By providing a simple and efficient interface to the user and a modular architecture for the designer, the proposed technique has a broad impact across a wide range of custom hardware designs.

关键词： Fully pipelined reduction circuits accumulator field-programmable gate arrays modular design digital_circuits

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FPGA Design of a New Frequency Relay Based on Evolutionary Algorithms

FPGA Design of a New Frequency Relay Based on Evolutionary A...

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IEEE PES 2nd Latin American Conference on Innovative Smart Grid Technologies (ISGT Latin America)

作者： Coury, Denis V. Delbem, Alexandre C. B. Oleskovicz, Mario Simoes, Eduardo V. Barbosa, Daniel de Carvalho, Janison R. Univ Sao Paulo Depto Engn Eletr & Comp EESC BR-13566590 Sao Carlos SP Brazil

ISBN: (纸本)9781467352741;9781467352727

This paper presents an efficient technique for frequency estimation in Electrical Power Systems (EPS) based on Genetic Algorithms (GAs). Frequency estimation of a distorted electrical signal is modeled as an optimization problem. The motivation concerning the use of the GA approach is related to its intrinsic robustness to noise. The GA is implemented in a FPGA (field-programmable gate Array) device and the estimation process is computed in real-time. This is made possible due to (a) the implicit parallelism of FPGAs (b) the suitable choice of the GA operators to explore this parallelism and (c) the determination of the appropriate architecture for a FPGA that parallelizes the GA routine and ensures its good performance. In order to evaluate the performance of the proposed method, an EPS was simulated using the ATP software for some typical operation conditions. The resulting signals were analyzed by the proposed GA/FPGA approach and they were compared to the performance of a commercial relay. Promising results were found with the proposed methodology.

关键词： Frequency Estimation Genetic Algorithms field-programmable gate arrays Digital Relaying Power System Protection

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Characterization and Simulation of NMOS Pass Transistor Reliability for FPGA Routing Circuits

Characterization and Simulation of NMOS Pass Transistor Reli...

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26th IEEE International Conference on Microelectronic Test Structures (ICMTS)

作者： Chen, Christopher S. Watt, Jeffrey T. Altera Corp Proc Technol Dev San Jose CA 95134 USA

ISBN: (纸本)9781467348485;9781467348454

In this work, the impact of bias temperature instability is evaluated for routing pass gate circuits. A simple test structure is proposed and measured data is compared to aging models to demonstrate the importance of modeling circuit level aging effects. Aging models which are shown to be accurate at the transistor level are inadequate at the circuit level unless frequency dependent aging effects are taken into account.

关键词： MOSFETs reliability bias temperature instability field-programmable gate arrays

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A HARDWARE TEST PLATFORM IN field-programmable LOGIC FOR PARALLELIZED DIGITAL SIGNAL PROCESSING

A HARDWARE TEST PLATFORM IN FIELD-PROGRAMMABLE LOGIC FOR PAR...

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26th IEEE Annual Canadian Conference on Electrical and Computer Engineering (CCECE)

作者： Sokalski, Tayler Manjikian, Naraig Queens Univ Dept Math & Stat Kingston ON K7L 3N6 Canada Queens Univ Dept Elect & Comp Engn Kingston ON K7L 3N6 Canada

ISBN: (纸本)9781479900336;9781479900312

This paper describes the development and application of a self-contained platform to support hardware implementation and testing of components and systems for parallelized digital signal processing in field-programmable gate-array (FPGA) logic chips. To more closely reflect the usage of parallelized components in actual applications, high-speed input/output pins of FPGA chips are utilized in a loopback configuration so that parallel streams of representative digitized complex fixed-point data are fed as input to a system under test. On-chip FPGA memory is used to implement high-speed FIFO buffers connected to the system under test. On-chip memory is also used to stage data for the input FIFO buffer feeding the system under test and to collect processed data from the output FIFO buffer. An embedded processor executes software used to perform data transfers between the FIFO buffers and staging memory, and to initiate full-speed operation for a system under test with data flowing through the external loopback connection. This paper also provides sample results from a representative parallelized finite-impulse-response filter tested using the hardware platform described in this paper.

关键词： field-programmable gate arrays digital signal processing finite impulse response filter systolic arrays

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Novel Fine Tunable Multichannel All-Digital Transmitter

Novel Fine Tunable Multichannel All-Digital Transmitter

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IEEE MTT-S International Microwave Symposium Digest (IMS)

作者： Silva, Nelson V. Oliveira, Arnaldo S. R. Carvalho, Nuno Borges Univ Aveiro Inst Telecomunicacoes Dept Elect Telecomunicacoes & Informat P-3810193 Aveiro Portugal

ISBN: (纸本)9781467321419;9781467361774

All-digital transmitters are gaining an increased research importance due to the unparalleled proliferation of dissimilar wireless standards and more recently due to the white space technology needs. In this paper, a new fine tunable multi-channel transmitter is presented. This new architecture supports concurrent multi-rate, multi-band, multi-standard transmission and significantly minimizes the output frequencies restrictions of current approaches by allowing fine frequency tuning for channel selection. The obtained results show the feasibility and potential of FPGA-embedded RF transmitters where the use of polyphase datapaths substantially improves the SNR of the desired signals.

关键词： Cognitive radio delta-sigma modulation field-programmable gate arrays radio transmitters software radio

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Using FPGAs to Simulate Novel Datacenter Network Architectures at Scale

Using FPGAs to Simulate Novel Datacenter Network Architectur...

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作者： Tan, Zhangxi University of California Berkeley

学位级别：Ph.D., Doctor of Philosophy

The tremendous success of Internet services has led to the rapid growth of Warehouse-Scale Computers (WSCs). The networking infrastructure has become one of the most vital components in a datacenter. With the rapid evolving set of workloads and software, evaluating network designs really requires simulating a computer system with three key features: scale, performance, and accuracy. To avoid the high capital cost of hardware prototyping, many designs have only been evaluated with a very small testbed built with off-the-shelf devices, often running unrealistic microbenchmarks or traces collected from an old cluster. Many evaluations assume the workload is static and that computations are only loosely coupled with the very adaptive networking stack. We argue the research community is facing a hardware-software co-evaluation *** this dissertation, we propose a novel cost-efficient evaluation methodology, called Datacenter-in-a-Box at Low cost (DIABLO), which uses field-programmable gate arrays (FPGAs) and treats datacenters as whole computers with tightly integrated hardware and software. Instead of prototyping everything in FPGAs, we build realistic reconfigurable abstracted performance models at scales of O(10,000) servers. Our server model runs the full Linux operating system and open-source datacenter software stack, including production software such as memcached. It achieves two orders of magnitude simulation speedup over software-based simulators. This speedup enables us to run the full datacenter software stack for O(100) seconds of simulated time. We have built a DIABLO prototype of a 2,000-node simulated cluster with runtime-configurable 10 Gbps interconnect using 6 multi-FPGA BEE3 boards.

关键词： Warehouse-Scale Computers field-programmable gate arrays Datacenter-in-a-Box at Low cost Software-based simulators

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Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2013年第4期6卷 16-16页

作者： Plavec, Franjo Vranesic, Zvonko Brown, Stephen Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

This article describes the design and implementation of a novel compilation flow that implements circuits in FPGAs from a streaming programming language. The streaming language supported is called FPGA Brook and is based on the existing Brook language. It allows system designers to express applications in a way that exposes parallelism, which can be exploited through hardware implementation. FPGA Brook supports replication, allowing parts of an application to be implemented as multiple hardware units operating in parallel. Hardware units are interconnected through FIFO buffers which use the small memory modules available in FPGAs. The FPGA Brook automated design flow uses a source-to-source compiler, developed as a part of this work, and combines it with a commercial behavioral synthesis tool to generate the hardware implementation. A suite of benchmark applications was developed in FPGA Brook and implemented using our design flow. Experimental results indicate that performance of many applications scales well with replication. Our benchmark applications also achieve significantly better results than corresponding implementations using a commercial behavioral synthesis tool. We conclude that using an automated design flow for implementation of streaming applications in FPGAs is a promising methodology.

关键词： Design Languages Performance Data parallelism task parallelism replication throughput scalability high-level synthesis parallel reduction field-programmable gate arrays streaming behavioral synthesis

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