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IEEE/MTT-S International Microwave Symposium

作者： Nelson V. Silva Arnaldo S. R. Oliveira Nuno Borges Carvalho Departamento de Electronica Telecomunicacoes e Informatica Instituto de Telecomunicacoes Universidade de Aveiro

ISBN: (纸本)9781467361750

All-digital transmitters are gaining an increased research importance due to the unparalleled proliferation of dissimilar wireless standards and more recently due to the white space technology needs. In this paper, a new fine tunable multi-channel transmitter is presented. This new architecture supports concurrent multi-rate, multi-band, multi-standard transmission and significantly minimizes the output frequencies restrictions of current approaches by allowing fine frequency tuning for channel selection. The obtained results show the feasibility and potential of FPGA-embedded RF transmitters where the use of polyphase datapaths substantially improves the SNR of the desired signals.

关键词： Cognitive radio Delta-sigma modulation field-programmable gate arrays Radio transmitters Software radio

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Improved Performance of TES Bolometers using Digital Feedback

Improved Performance of TES Bolometers using Digital Feedbac...

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Conference on Millimeter, Submillimeter, and Far-Infrared Detectors and Instrumentation for Astronomy VI

作者： de Haan, Tijmen Smecher, Graeme Dobbs, Matt McGill Univ Dept Phys Montreal PQ H3A 2T8 Canada

ISBN: (纸本)9780819491534

Voltage biased, frequency multiplexed TES bolometers have become a widespread tool in mm-wave astrophysics. However, parasitic impedance and dynamic range issues can limit stability, performance, and multiplexing factors. Here, we present novel methods of overcoming these challenges, achieved through digital feedback, implemented on a field-programmable gate Array (FPGA). In the first method, known as Digital Active Nulling (DAN), the current sensor (e.g. SQUID) is nulled in a separate digital feedback loop for each bolometer frequency. This nulling removes the dynamic range limitation on the current sensor, increases its linearity, and reduces its effective input impedance. Additionally, DAN removes constraints on wiring lengths and maximum multiplexing frequency. DAN has been fully implemented and tested. Integration for current experiments, including the South Pole Telescope, will be discussed. We also present a digital mechanism for strongly increasing stability in the presence of large series impedances, known as Digitally Enhanced Voltage Bias (DEVB).

关键词： Digital feedback baseband feedback TES bolometers field-programmable gate arrays

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Synchronized-Transfer-Level Design Methodology applied to Hardware Matrix Multiplication

Synchronized-Transfer-Level Design Methodology applied to Ha...

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International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Daigneault, Marc-Andre David, Jean Pierre Ecole Polytech Montreal PQ H3C 3A7 Canada

ISBN: (纸本)9781467329194;9781467329200

In an effort to reduce the productivity gap separating hardware design and software programming practices, this paper presents the application of our synchronized-transfer-level hardware design methodology to the implementation of a hardware matrix multiplication accelerator. The methodology builds on a hardware description language for which the designer manages dynamic connections between sources and sinks that may not always be ready to send or receive data tokens. In addition to these connections, the designer can constrain the authorization of data transfers by the means of logical rules that make transfers dependant on each other. Combining both finite state machine and constraint programming paradigms, the featured description language enhances the ability to express and exploit low-level parallelism. A compiler automates the generation and the optimization of the synchronization logic, whose low-level complexity is thus hidden to the designer. Applied to the design of the pipelined matrix multiplication circuit, the proposed methodology leads to similar computing performances than the dedicated designs reported in the literature but within shorter design times (a single day), simpler source code and no need for advanced hardware design skills.

关键词： High-Level Synthesis Hardware Description Language Synchronized-Transfer-Level field-programmable gate arrays

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Guarded Evaluation: An Algorithm for Dynamic Power Reduction in FPGAs

Guarded Evaluation: An Algorithm for Dynamic Power Reduction...

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作者： Ravishankar, Chirag University of Waterloo

学位级别：master

Guarded evaluation is a power reduction technique that involvesidentifying sub-circuits (within a larger circuit) whose inputs can beheld constant (guarded) at specific times during circuit operation,thereby reducing switching activity and lowering dynamic power. Theconcept is rooted in the property that under certain conditions, somesignals within digital designs are not "observable" at designoutputs, making the circuitry that generates such signals a candidatefor guarding. Guarded evaluation has been demonstrated successfullyfor custom ASICs; in this work, we apply the technique to FPGAs. InASICs, guarded evaluation entails adding additional hardware to thedesign, increasing silicon area and cost. Here, we apply the techniquein a way that imposes minimal area overhead by leveraging existingunused circuitry within the FPGA. The LUT functionality is modifiedto incorporate the guards and reduce toggle rates. The primary challenge in guarded evaluation is in determining the specific conditions under which a sub-circuit''s inputs can be held constant without impacting the largercircuit''s functional correctness. We propose a simple solution tothis problem based on discovering gating inputs using "non-inverting paths" and trimming inputs using "partial non-inverting paths" in thecircuit''s AND-Inverter graph representation. Experimental results show that guarded evaluation can reduce switching activity by as much as 32% for FPGAs with 6-LUT architectures and 25% for 4-LUT architectures, onaverage, and can reduce power consumption in the FPGA interconnect by29% for 6-LUTs and 27% for 4-LUTs. A clustered architecture with four LUTs to a cluster and ten LUTs to a cluster produced the best power reduction *** implement guarded evaluation at various stages of the FPGA CAD flow and analyze the reductions. We implementthe algorithm as post technology mapping, post packing and post placement optimizations. Guarded Evaluationas a post technology mapping algorithm inse

关键词： field-programmable gate arrays Power optimization low-power design logic synthesis technology mapping

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Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation

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ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 2012年第S2期11卷 42-42页

作者： Mark, Cindy Chin, Scott Y. L. Shannon, Lesley Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada Simon Fraser Univ Burnaby BC V5A 1S6 Canada

We describe a stochastic circuit generator that can be used to automatically create benchmark circuits for use in FPGA architecture studies. The circuits consist of a hierarchy of interconnected modules, reflecting the structure of circuits designed using a system-on-chip design flow. Within each level of hierarchy, modules can be connected in a bus, star, or dataflow configuration. Our circuit generator is calibrated based on a careful study of existing system-on-chip circuits. We show that our benchmark circuits lead to more realistic architectural conclusions than circuits generated using previous generators.

关键词： Design field-programmable gate arrays benchmark circuits

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Optimized FPGA-based elliptic curve cryptography processor for high-speed applications

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INTEGRATION-THE VLSI JOURNAL 2011年第4期44卷 270-279页

作者： Jarvinen, Kimmo Aalto Univ Sch Sci & Technol Dept Informat & Comp Sci FIN-00076 Aalto Finland

In this paper, we introduce an FPGA-based processor for elliptic curve cryptography on Koblitz curves. The processor targets specifically to applications requiring very high speed. The processor is optimized for performing scalar multiplications, which are the basic operations of every elliptic curve cryptosystem, only on one specific Koblitz curve;the support for other curves is achieved by reconfiguring the FPGA. We combine efficient methods from various recent papers into a very efficient processor architecture. The processor includes carefully designed processing units dedicated for different parts of the scalar multiplication in order to increase performance. The computation is pipelined providing simultaneous processing of up to three scalar multiplications. We provide experimental results on an Altera Stratix II FPGA demonstrating that the processor computes a single scalar multiplication on average in 11.71 mu s and achieves a throughput of 235,550 scalar multiplications per second on NIST K-163. (C) 2010 Elsevier B.V. All rights reserved.

关键词： Elliptic curve cryptography field-programmable gate arrays Koblitz curve Parallelism

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Highly scalable IP core to accelerate the forward/backward modified discrete cosine transform in MP3 implemented to FPGA and low-power ASIC

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IET CIRCUITS DEVICES & SYSTEMS 2011年第5期5卷 351-359页

作者： Malik, P. Slovak Acad Sci Inst Informat Bratislava 84507 Slovakia

Modified discrete cosine transform (MDCT) is used in many audio coding standards for time-to-frequency transformation of digital signals. It is one of the most computationally intensive operations in audio compression and decompression processes. In this study, optimised dedicated hardware architectures utilised in a highly scalable MDCT IP core are proposed to accelerate the forward/backward MDCT computation in MP3 audio coding standard. The MDCT IP core is pipelined, capable to compute both the forward and backward MDCT on the same hardware and it is optimised with field-programmable gate arrays (FPGA) and application-specific integrated circuit (ASIC) technologies. The MDCT IP core is implemented to FPGA and ASIC, whereby the FPGA implementation used Xilinx Virtex-4 FPGA, while the ASIC implementation used AMS 350 nm CMOS standard cell library. The MDCT IP core is further optimised and implemented utilising UMC 90 nm CMOS low-power digital libraries and clock gating technique. As a result, power consumption and the area are reduced significantly. The proposed hardware architectures are optimised to achieve high computational speed with high precision, and therefore they are suitable for a lossless audio compression. In particular, high computational speed permits multichannel real-time acceleration of the forward and backward MDCT computation.

关键词： field-programmable gate arrays application-specific integrated circuit low-power ASIC backward modified discrete cosine transform Xilinx Virtex-4 FPGA size 350 nm forward modified discrete cosine transform low-power electronics AMS CMOS standard cell library size 90 nm digital signals time-to-frequency transformation CMOS low-power digital libraries discrete cosine transforms MP3 application specific integrated circuits lossless audio compression logic design IP core clock gating technique CMOS integrated circuits field programmable gate arrays clocks audio decompression audio coding standards audio coding

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New Hardware Architectures for Montgomery Modular Multiplication Algorithm

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IEEE TRANSACTIONS ON COMPUTERS 2011年第7期60卷 923-936页

作者： Huang, Miaoqing Gaj, Kris El-Ghazawi, Tarek 1 Univ Arkansas Dept Comp Sci & Comp Engn Fayetteville AR 72701 USA George Mason Univ Dept Elect & Comp Engn Fairfax VA 22030 USA George Washington Univ Dept Elect & Comp Engn Washington DC 20052 USA

Montgomery modular multiplication is one of the fundamental operations used in cryptographic algorithms, such as RSA and Elliptic Curve Cryptosystems. At CHES 1999, Tenca and Koc proposed the Multiple-Word Radix-2 Montgomery Multiplication (MWR2MM) algorithm and introduced a now-classic architecture for implementing Montgomery multiplication in hardware. With parameters optimized for minimum latency, this architecture performs a single Montgomery multiplication in approximately 2n clock cycles, where n is the size of operands in bits. In this paper, we propose two new hardware architectures that are able to perform the same operation in approximately n clock cycles with almost the same clock period. These two architectures are based on precomputing partial results using two possible assumptions regarding the most significant bit of the previous word. These two architectures outperform the original architecture of Tenca and Koc, in terms of the product latency times area by 23 and 50 percent, respectively, for several most common operand sizes used in cryptography. The architecture in radix-2 can be extended to the case of radix-4, while preserving a factor of two speedup over the corresponding radix-4 design by Tenca, Todorov, and Koc from CHES 2001. Our optimization has been verified by modeling it using Verilog-HDL, implementing it on Xilinx Virtex-II 6000 FPGA, and experimentally testing it using SRC-6 reconfigurable computer.

关键词： Montgomery multiplication MWR2MM algorithm hardware optimization field-programmable gate arrays

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A High-End Reconfigurable Computation Platform for Nuclear and Particle Physics Experiments

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COMPUTING IN SCIENCE & ENGINEERING 2011年第2期13卷 52-63页

作者： Liu, Ming Kuehn, Wolfgang Lange, Soeren Yang, Shuo Roskoss, Johannes Lu, Zhonghai Jantsch, Axel Wang, Qiang Xu, Hao Jin, Dapeng Liu, Zhen'an Univ Giessen FPGAs Giessen Germany Royal Inst Technol Dept Elect Syst Stockholm Sweden Chinese Acad Sci Inst High Energy Phys Beijing Peoples R China Inst High Energy Phys Expt Phys Ctr Beijing 100039 Peoples R China

A high-performance computation platform based on field-programmable gate arrays targets nuclear and particle physics experiment applications. The system can be constructed or scaled into a supercomputer-equivalent size for detector data processing by inserting compute nodes into advanced telecommunications computing architecture (ATCA) crates. Among the case study results are that one ATCA crate can provide a computation capability equivalent to hundreds of commodity PCs for Hades online particle track reconstruction and Cherenkov ring recognition.

关键词： ATCA crates Cherenkov counters Cherenkov ring recognition FPGA implementation Hades online particle track reconstruction Reconfigurable computing advanced telecommunications computing architecture crates commodity PC computation capability compute nodes detector data processing field programmable gate arrays field-programmable gate arrays high energy physics instrumentation computing high-end reconfigurable computation platform high-performance computation platform nuclear and particle physics nuclear physics nuclear physics experiments particle physics experiments particle tracks pattern recognition reconfigurable architectures scientific computing supercomputer-equivalent size

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Island-Based Adaptable Embedded System Design

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IEEE EMBEDDED SYSTEMS LETTERS 2011年第2期3卷 53-57页

作者： Beretta, Ivan Rana, Vincenzo Atienza, David Sciuto, Donatella Ecole Polytech Fed Lausanne Embedded Syst Lab CH-1015 Lausanne Switzerland Politecn Milan Dipartimento Elettron & Informaz I-20133 Milan Italy

Nowadays, hardware devices are meant to host the execution of many complex, multicore applications, whose functional and nonfunctional requirements vary according to the specific working domain. In this work, we propose a design methodology that combines an efficient reconfigurable architecture and a related mapping flow. In particular, the proposed island-based hardware architecture couples an efficient area usage and an adaptable communication infrastructure. The proposed mapping flow distributes the cores on the device to optimize both performance and reconfiguration related metrics.

关键词： CAD tools field-programmable gate arrays (FPGAs) platform-based design reconfigurable computing

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