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Enhanced Self-Synchronized Reduced Media-Independent Interface for Robotic and Automotive Applications

IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS 2022年第4期18卷 2274-2286页

作者： Romanov, Alexey Mikhailovitch Gringoli, Francesco MIREA Russian Technol Univ Inst Cybernet Moscow 119454 Russia Univ Brescia Dept Informat Engn I-25123 Brescia Italy Italian Natl Interuniv Consortium Telecommun I-25123 Brescia Italy

The increasing pervasiveness of control systems used in robotic and automotive applications requires the installation of a growing number of sensors and actuators. In parallel to the downsizing of all the components, new techniques for tracing versatile printed circuit boards (PCBs) are emerging: a 3-D molded interconnection device, for example, creates the opportunity to reduce up to 75% of weight by combining a single-layer PCB with mechanical parts. Getting rid of unnecessary wires, hence, becomes indispensable, and new on-board interfaces with fewer pins must be designed. This article proposes a novel encoding scheme and the corresponding interface that reduces the number of wires between automotive Ethernet (100BASE-T1) MAC and PHY down to 2 and corrects up to 37.8% of single-bit errors. As this interface can be clocked at 33.33 MHz, it does not require differential transmitters, receivers, or any other special block, and for this reason, it can be easily implemented on a small-sized field-programmable gate array.

关键词： Ethernet field programmable gate arrays Encoding Wires Robots Clocks Media Encoding field-programmable gate arrays network interfaces reduced media-independent interface self-synchronization wire communication interference 3-D molded interconnection device (3D-MID)

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An Implementation Method Using Cut-Off Bits for Restricted Boltzmann Machines Without Random Number Generators

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IEEE ACCESS 2022年 10卷 42791-42801页

作者： Hori, Sansei Tamukoh, Hakaru Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Wakamatsu Ku Kitakyushu Fukuoka 8080135 Japan Kyushu Inst Technol Res Ctr Neuromorph AI Hardware Kitakyushu Fukuoka 8080135 Japan

This study proposes an implementation method of a hardware-oriented restricted Boltzmann machine (RBM) without random number generators (RNGs) that employ cut-off bits, which are obtained from fixed-point binary arithmetic operations on digital hardware, such as field-programmable gate arrays (FPGAs), instead of random numbers. Most FPGA circuits employ fixed-point binary arithmetic operations to improve hardware resource efficiency. Therefore, the proposed method applies the unique feature of the operation, which is bit width extension and cut-off bits. Stochastic neural networks, including RBMs, employ sampling processes based on a probability distribution associated with the network, and the processes require many random numbers. However, implementing RNGs in hardware is costly because it requires considerable hardware resources. The proposed method can mitigate this requirement. To validate the proposed method, we implement an RBM with the proposed method on the software, emulate fixed-point binary arithmetic operations, and train the RBM using the MNIST and Fashion MNIST datasets. Furthermore, we apply the chi-square goodness-of-fit test to evaluate the uniformity of the cut-off bits. Additionally, we compare hardware resource requirements and power consumption for the proposed method and some major RNGs, a linear feedback shift register (LFSR), and a xorshift. Experimental results showed that it was possible to use the cut-off bits for training the RBM using the datasets and clarified the properties of the cut-off bits using statistical analyses. Moreover, hardware implementation of the proposed method involved the lowest hardware resource requirements and power consumption among the RNGs compared in this study.

关键词： Hardware field programmable gate arrays Neural networks Power demand Generators Cloud computing Training field-programmable gate arrays neural networks random number generation restricted Boltzmann machines

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Intelligent Structure Control System Based on FPGA 12

Intelligent Structure Control System Based on FPGA

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IEEE 12th Data Driven Control and Learning Systems Conference (DDCLS)

作者： Qiu Ruikang Li Shengquan Cui Ronghua Zhang Lujin Li Juan Yangzhou Univ Coll Elect Energy & Power Engn Yangzhou 225127 Peoples R China

ISBN: (纸本)9798350321050

A linear active disturbance rejection control (LADRC) strategy is proposed to suppress the structural vibration caused by external excitations and internal uncertainties in intelligent structures under complex working conditions via an Anlu EG4S20B256 chip. First, the electromechanical coupling model of the whole vibration control system is obtained based on the dynamic equations of the all-clamped plate structure and the electromagnetic equations of the inertial actuator. Second, based on the system model, a third-order extended state observer (ESO) is designed to estimate the internal modelling errors and external excitation perturbations of the system in real time. In addition, the influence of internal and external disturbances on the control effect in the experiment is offset by a feedforward compensation. Finally, a vibration control platform based on the Anlu FPGA chip is built to verify the control effect of the proposed vibration active control strategy through physical real-time simulation.

关键词： All-clamped plate Active vibration control Linear active disturbance rejection control field-programmable gate arrays

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Accounting for Floorplan Irregularity and Configuration Dependence in FPGA Routing Delay Models 24

Accounting for Floorplan Irregularity and Configuration Depe...

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24th International Symposium on Quality Electronic Design (ISQED)

作者： Barajas, Gabriel Greene, Jonathan W. Li, Fei Tandon, James Microchip San Jose CA 95134 USA Cambios Comp LLC Palo Alto CA USA Calif State Univ East Bay Hayward CA USA

ISBN: (纸本)9798350334753

Accurate delay estimates for a user application implemented in a field-programmable gate Array (FPGA) are essential for a quality FPGA timing flow and to avoid leaving performance on the table. FPGA inter-cluster routing consists of wire segments of a limited number of types which repeat in a somewhat regular pattern, interconnected by configurable muxes. The delay at any fanout of a segment can be significantly impacted by configuration-dependent capacitive loading related to other fanouts. Also, the insertion of RAM and math blocks into the FPGA floorplan introduces irregular stretching of the wire segments, altering their delays. We explain why and how commercial FPGA software typically employs a parameterized model for the delay at each fanout of a segment, based on the configuration and the irregularities present, with the parameters determined by fitting SPICE simulation data for a representative sample of cases. We propose incorporating readily-computed common path resistance values into the model. This enables high accuracy with fewer parameters and without the large amounts of SPICE data that would otherwise be required to explore interactions between floorplan irregularities and the set of active fanouts. In combination with other features of our models, errors in segment delay are reduced by almost half.

关键词： field-programmable gate arrays FPGAs delay estimation Elmore delay common path resistance

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A Use Case of Iterative Logarithmic Floating-Point Multipliers: Accelerating Histogram Stretching on programmable SoC 56

A Use Case of Iterative Logarithmic Floating-Point Multiplie...

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56th IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Norris, Cameron James Kim, Sunwoong Univ Washington Div Engn & Math Bothell WA 98011 USA

ISBN: (纸本)9781665451093

programmable system-on-chip (SoC) platforms often have a hard-core processor and programmable logic for heterogeneous computing. A custom hardware design implemented with programmable logic accelerates specific operations in an application. This paper applies an area-efficient iterative logarithmic floating-point multiplier to histogram stretching on a programmable SoC platform. Specifically, the floating-point multiplier is implemented with programmable logic, and the hardcore processor on the same platform determines the accuracy and latency of the multiplier by changing the number of iterations used for error correction at runtime. To deploy many multiplier cores working in parallel and have the iterative architecture process streaming data, a higher-level pipelined architecture is proposed. The number of multipliers in this architecture is configurable by changing the maximum number of iterations. For 352x288 resolution videos, with 250 frames per video, the proposed histogram stretching design reduces the multiplication time by 78% and the total execution time by 13% compared to a design performing exact floating-point multiplications on a hard-core processor.

关键词： heterogeneous computing field-programmable gate arrays approximate computing floating-point multiplier histogram stretching

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Comparative Analysis of Neural Network Implementations for NILM Applications 38

Comparative Analysis of Neural Network Implementations for N...

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38th Conference on Design of Circuits and Integrated Systems (DCIS)

作者： Martin, Jorge de Diego, Laura Tapiador, Miguel Hernandez, Alvaro Nieto, Ruben Univ Alcala Elect Dept Alcala De Henares Spain Rey Juan Carlos Univ Elect Technol Dept Mostoles Spain

ISBN: (纸本)9798350303858

Non-Intrusive Load Monitoring (NILM) comprises a set of techniques that try to disaggregate the energy consumption in a household or building, based on the measurements coming from a single-point smart meter. In this process, a key step is the load identification of the different appliances that may switched on/off during a certain interval under analysis. For that purpose, machine-learning techniques, including deep neural networks, have recently been involved. These classification algorithms may often imply a high computational cost, that might compromise a possible edge-computing implementation on the local smart meters. In this context, this work presents a preliminary comparison between two different real-time implementations of both neural networks, a dense one and a convolutional one, applied to load classification. The implementations are based on a FPGA approach and on a processor. In general terms, preliminary results show that the FPGA solution provides lower latencies than the processor one, at the expense of requiring a higher design effort and a quantization error coming from the fixedpoint representation.

关键词： Neural Networks field-programmable gate arrays Non-Intrusive Load Monitoring

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Architecture and Application Co-Design for Beyond-FPGA Reconfigurable Acceleration Devices

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IEEE ACCESS 2022年 10卷 95067-95082页

作者： Boutros, Andrew Nurvitadhi, Eriko Betz, Vaughn Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada Intel Corp Programmable Solut Grp Santa Clara CA 95054 USA

In recent years, field-programmable gate arrays (FPGAs) have been increasingly deployed in datacenters as programmable accelerators that can offer software-like flexibility and custom-hardware-like efficiency for key datacenter workloads. To improve the efficiency of FPGAs for these new datacenter use cases and data-intensive applications, a new class of reconfigurable acceleration devices (RADs) is emerging. In these devices, the FPGA fine-grained reconfigurable fabric is a component of a bigger monolithic or multi-die system-in-package that can incorporate general-purpose software-programmable cores, domain-specialized accelerator blocks, and high-performance networks-on-chip (NoCs) for efficient communication between these system components. The integration of all these components in a RAD results in a huge design space and requires re-thinking the implementation of applications that need to be migrated from conventional FPGAs to these novel devices. In this work, we introduce RAD-Sim, an architecture simulator that allows rapid design space exploration for RADs and facilitates the study of complex interactions between their various components. We also present a case study that highlights the utility of RAD-Sim in re-designing applications for these novel RADs by mapping a state-of-the-art deep learning (DL) inference FPGA overlay to different RAD instances. Our case study illustrates how RAD-Sim can capture a wide variety of reconfigurable architectures, from conventional FPGAs to devices augmented with hard NoCs, specialized matrix-vector blocks, and 3D-stacked multi-die devices. In addition, we show that our tool can help architects evaluate the effect of specific RAD architecture parameters on end-to-end workload performance. Through RAD-Sim, we also show that novel RADs can potentially achieve 2.6x better performance on average compared to conventional FPGAs in the key DL application domain.

关键词： Deep learning field-programmable gate arrays hardware acceleration network-on-chip reconfigurable computing

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GNNHLS: Evaluating Graph Neural Network Inference via High-Level Synthesis 41

GNNHLS: Evaluating Graph Neural Network Inference via High-L...

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41st IEEE International Conference on Computer Design (ICCD)

作者： Zhao, Chenfeng Dong, Zehao Chen, Yixin Zhang, Xuan Chamberlain, Roger D. Washington Univ McKelvey Sch Engn St Louis MO 63110 USA

ISBN: (纸本)9798350342918

We present GNNHLS, an open-source framework to comprehensively evaluate GNN inference acceleration on FPGAs via HLS, containing a software stack for data generation and baseline deployment and FPGA implementations of 6 well-tuned GNN HLS kernels. Evaluating on 4 graph datasets with distinct topologies and scales, the results show that GNNHLS achieves up to 50.8x speedup and 423x energy reduction relative to the CPU baselines. Compared with the GPU baselines, GNNHLS achieves up to 5.16x speedup and 74.5x energy reduction.

关键词： field-programmable gate arrays graph neural networks high-level synthesis

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High-Performance Packet Routing Acceleration for Cloud Systems Using High Bandwidth Memory

IEEE OPEN JOURNAL OF THE COMMUNICATIONS SOCIETY

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IEEE OPEN JOURNAL OF THE COMMUNICATIONS SOCIETY 2022年 3卷 119-126页

作者： Shimizu, Takashi Hyoudou, Kazuki Murakawa, Hiroshi Ishihara, Tomohiro Fujitsu Ltd Infrastruct Syst Dept Kawasaki Kanagawa 2110053 Japan Fujitsu Labs Ltd ICT Syst Lab Kawasaki Kanagawa 2110053 Japan

Virtual routers (vRouters) in cloud systems are in great demand due to the ever-increasing network bandwidth. To meet this demand, hardware offload technologies are mandatory for vRouters. Furthermore, offload hardware needs new architecture to achieve a throughput of several hundred Gbps, because memories that store routing tables will create a bottleneck. Therefore, we propose a new hardware architecture using high bandwidth memories (HBMs) and an acceleration engine equipped with multi-pipeline processing. In this paper, we improved the performance of the random memory-accesses from multiple pipelines by distributing to the memory channels of HBMs. In our prototype, vRouter packet processing performances were achieved 320 M packet per second(pps) and 250 Gbit per second (bps). Moreover, the prototype showed low and stable latency of packet transfers that was not affected by background traffic.

关键词： Computer architecture Software Cloud computing Routing Hardware field programmable gate arrays Pipelines Accelerator architecture field-programmable gate arrays high bandwidth memory virtual router hardware offload

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ILAFD: Accuracy-Configurable Floating-Point Divider Using an Approximate Reciprocal and an Iterative Logarithmic Multiplier 23

ILAFD: Accuracy-Configurable Floating-Point Divider Using an...

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33rd Great Lakes Symposium on VLSI (GLSVLSI)

作者： Oelund, James Kim, Sunwoong Univ Washington Bothell WA 98011 USA

ISBN: (纸本)9798400701252

Approximate computing provides benefits in the logic area, latency, and/or power without significantly affecting the outputs of some applications. Various approximate computing techniques have been applied for floating-point (FP) dividers that are expensive compared to other FP operators. Since the accuracy requirement varies depending on the application, this paper proposes an accuracy-configurable approximate FP divider design. This design computes the reciprocal of a divisor in a hardware-friendly way. To correct approximation errors, multiple error biases are calculated based on error analysis and stored in a lookup table. The calculated reciprocal is multiplied by a dividend. For accuracy-configurability, an iterative logarithmic FP multiplier is adopted. Compared to previous approximate designs, our proposed design achieves a significantly higher level of accuracy by increasing the number of iterations, at the cost of a slight increase in hardware resources. Compared to the state-of-art Xilinx LogiCORE IP design for accurate FP division, the proposed approximate design reduces the number of lookup table blocks by 53% and the number of flip-flops by 90% in a field-programmable gate array. In JPEG compression, the conventional exact FP multiplier/divider and the proposed design with the number of iterations of 4 show almost the same peak signal-to-noise ratio values.

关键词： approximate computing field-programmable gate arrays floating-point iterative architecture logarithmic divider

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