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作者： Mehrabi, Atefeh Duke University

学位级别：Ph.D., Doctor of Philosophy

Hardware acceleration, which entails customizing datapath and control logic for a specific application, has led to remarkable performance and power efficiency. Hardware accelerators have emerged in various forms including specialized processors (e.g., graphics processing unit [GPU]), fixed function custom circuits (e.g., applicationspecific integrated circuit [ASIC]), and reconfigurable fabrics (e.g., field-programmable gate array [FPGA]). Though accelerators provide excellent gains, the development of efficient ones is time-consuming, costly, and complex. Various techniques such as high-level synthesis (HLS) and FPGAs have been employed to reduce acceleration costs. However, hardware acceleration remains challenging due to the effort required to understand and optimize the design, as well as the limited system support available for efficient run-time management. Inefficient design mechanisms and a lack of proper run-time management policies for emerging platforms limit the pace at which accelerators can scale. This dissertation investigates solutions to reduce the costs and complexities of developing and using hardware accelerators. We pursue these goals by applying intelligent design mechanisms and efficient run-time management policies. We present three pieces of research, each of which tackles a unique design or run-time challenge. First, designing hardware accelerators remains largely dependent on register-transfer level (RTL) design and writing hardware code (i.e., Verilog, VHDL), which is a tedious process. The growing demand for hardware accelerators has attracted more attention to faster solutions such as HLS. However, generating the optimal RTL with HLS requires tuning optimizations. This process can take days and is heavily reliant on designers. We build an automated framework called Prospector to further reduce the design effort with statistical learning. Prospector uses Bayesian optimization to tune optimizations intelligently and discover efficient des

关键词： Hardware accelerators Register-transfer level field-programmable gate arrays Sparse matrix multi-vector multiplication

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Post-Measurement Adjustment of the Coincidence Window in Quantum Optics Experiments

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IEEE ACCESS 2021年 9卷 94010-94016页

作者： Carine, Jaime Gomez, Santiago A. Obregon, Giannini F. Gomez, Esteban S. Figueroa, Miguel Lima, Gustavo Xavier, Guilherme B. Univ Catolica Santisima Concepcion Dept Ingn Elect Concepcion 2850 Chile Univ Concepcion Dept Elect Engn 160-C Concepcion Chile Univ Concepcion Millennium Inst Res Opt Millennium Sci Initiat Program ANID 160-C Concepcion Chile Univ Concepcion Dept Fis 160-C Concepcion Chile Linkopings Univ Inst Systemtekn S-58183 Linkoping Sweden

We report on an electronic coincidence detection circuit for quantum photonic applications implemented on a field-programmable gate array (FPGA), which records each the time separation between detection events coming from single-photon detectors. We achieve a coincidence window as narrow as 500 ps with a series of optimizations on a readily-available and affordable FPGA development board. Our implementation allows real-time visualization of coincidence measurements for multiple coincidence window widths simultaneously. To demonstrate the advantage of our high-resolution visualization, we certified the generation of polarized entangled photons by collecting data from multiple coincidence windows with minimal accidental counts, obtaining a violation of the Clauser-Horne-Shimony-Holt (CHSH) Bell inequality by more than 338 standard deviations. Our results have shown the applicability of our electronic design in the field of quantum information.

关键词： field programmable gate arrays Delays Photonics Image edge detection Detectors Clocks Logic gates field-programmable gate arrays quantum information coincidence counting

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Damping of Subsynchronous Control Interactions in Large-Scale PV Installations Through Faster-Than-Real-Time Dynamic Emulation

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IEEE ACCESS 2021年 9卷 128481-128493页

作者： Cao, Shiqi Lin, Ning Dinavahi, Venkata Univ Alberta Elect & Comp Engn Dept Edmonton AB T6G 2R3 Canada Powertech Labs Inc Surrey BC V3W 7R7 Canada

Large-scale photovoltaic (PV) power plant has witnessed a dramatic increase in the integration into transmission and distribution network, manifesting subsynchronous control interaction (SSCI) when the host grid is weak. In this work, the oscillation modes of a typical PV network are analyzed, and a faster-than-real-time (FTRT) emulation is proposed for predicting the SSCI and consequently mitigating its impacts on AC grid by taking the effective active/reactive power control action. The electromagnetic transient (EMT) simulation is utilized to model the PV panels and converter stations to reflect the actual dynamic process. Meanwhile, the AC grid undergoes transient stability (TS) simulation to obtain a high speed up over real-time, and consequently, a power-voltage interface is adopted for the coexistence of different simulation methods. The reconfigurability and parallelism of the field-programmable gate arrays (FPGAs) enable the EMT-TS co-emulation strategy to run concurrently. With a remarkable 122 FTRT ratio, the proposed hardware emulation can provide an effective solution before the SSCI causes serious disruption following its detection. The hardware emulation results are validated by the off-line simulation tool Matlab/Simulink(R) and TSAT(R) in the DSATools((TM)) suite.

关键词： Emulation Power system stability Inverters Damping Voltage control Oscillators Hardware AC DC grid dynamic simulation electromagnetic transient faster-than-real-time field-programmable gate arrays hardware emulation parallel processing predictive control PV generation

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Architecture and CAD Techniques for Efficient FPGA Implementation of Machine Learning and Other Applications

Architecture and CAD Techniques for Efficient FPGA Implement...

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作者： Kim, Jin Hee University of Toronto (Canada)

学位级别：Ph.D., Doctor of Philosophy

field-programmable gate arrays (FPGAs) offer an alternative to application-specific integrated circuits (ASICs) that is attractive in scenarios where flexibility may be required or where chip volumes are not sufficiently high enough to justify the costs of a custom chip. The flexibility of FPGAs offer users the power/performance benefits of a custom hardware implementation, compared to software running on a processor, without committing to one specific design. However, the flexibility can lead to inefficiencies in terms of development time, area, performance, and power. FPGAs are used for a variety of applications and different optimizations can be applied to increase efficiency of FPGA implementations. This thesis considers techniques that can be applied to achieve efficient implementation of machine learning and other applications on an FPGA from the perspectives of architecture and computer-aided design (CAD). We consider the use of a high-level synthesis (HLS) tool to synthesize an accelerator for deep convolutional neural networks (CNNs) on an FPGA. We implement a complete end-to-end system running on an Arria 10 SoC FPGA. The accelerator implements zero-skipping and reduced-precision convolution with minimal impact on accuracy. We evaluate various versions of the accelerator through software changes and tool constraints alone. Then, we propose architecture changes to the carry-chain architecture in FPGAs to improve the resource utilization of binarized CNNs (BNNs). We add additional carry-chain circuitry that propagates sum instead of the carry. We demonstrate that we are able to reduce FPGA resource utilization while keeping the additional circuit area small. Lastly, we propose to re-map some of the look-up-tables (LUTs) to use the existing carry-chain architecture in order to increase performance by adding a post-LUT mapping step to the FPGA CAD flow. Using a subject graph that closely matches the underlying hardware, we are able to select critical paths to

关键词： field-programmable gate array architecture field-programmable gate arrays Machine Learning Computer-aided design

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An algorithm/hardware co-optimized method to accelerate CNNs with compressed convolutional weights on FPGA

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2024年第11期36卷 e8011-e8011页

作者： Shang, Jiangwei Zhang, Zhan Zhang, Kun Li, Chuanyou Qian, Lei Liu, Hongwei Harbin Inst Technol Sch Comp Sci & Technol Harbin Peoples R China State Key Lab Math Engn & Adv Comp Wuxi Peoples R China Southeast Univ Sch Comp Sci & Engn Nanjing Peoples R China

Convolutional neural networks (CNNs) have shown remarkable advantages in a wide range of domains at the expense of huge parameters and computations. Modern CNNs still tend to be more complex and larger to achieve better inference accuracy. However, the complex and large structures of CNNs could slow down the inference speed. Recently, Compressing the convolutional weights to be sparse by pruning the unimportant parameters has been demonstrated as an efficient way to reduce the computations of CNNs. On the other hand, field-programmable gate arrays (FPGAs) have been a popular hardware platform to accelerate CNN inference. In this paper, we propose an algorithm/hardware co-optimized method for accelerating CNN inference on FPGAs. For the algorithm, we take advantage of unstructured and structured parameter sparsifying methods to achieve high sparsity and keep the regularity of convolutional weights. Correspondingly, hardware-friendly index representations of sparse convolutional weights are proposed. For the hardware architecture, we propose row-wise input-stationary dataflow, which is tightly coupled with the algorithm. A row-wise computing engine (RConv Engine) is proposed, which is based on the dataflow. Inside the RConv Engine, the scalar-vector structure is applied to implement the basic processing elements (PEs). To flexibly calculate the feature map with various sizes, the PEs are organized in a 2D structure with two work modes. The experimental results demonstrate that our co-optimized method implements high sparsity of convolutional weights, and the computing engine achieves high computation efficiency. Compared with other accelerators, our co-optimized method implements a 10.9x$$ \times $$ speedup on FPS at most with the highest sparsity of convolutional weights and negligible accuracy loss.

关键词： algorithm/hardware co-optimized convolutional neural network field-programmable gate arrays hardware accelerator sparsifying method

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The ReadoutCard Userspace Driver for the New Alice O² Computing System

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2021年第8期68卷 1876-1883页

作者： Alexopoulos, Konstantinos Costa, Filippo CERN European Org Nucl Res CH-1221 Geneva Switzerland

A large ion collider experiment (ALICE) experiment focuses on the study of the quark-gluon plasma as a product of heavy-ion collisions at the CERN large hadron collider (LHC). During the long shutdown 2 of the LHC in 2019-2020, a major upgrade is underway in order to cope with a hundredfold input data rate increase with peaks of up to 3.5 TB/s. This upgrade includes the new online-offline computing system called O-2. The O-2 readout chain runs on commodity Linux servers equipped with custom peripheral component interconnect express (PCIe) field-programmable gate array (FPGA)-based readout cards: the PCIe Gen 3 x 16, Intel Arria 10-based common readout unit (CRU), and the PCIe Gen 2 x 8, Xilinx Vertex 6-based Common ReadOut Receiver Card (CRORC). Access to the cards is provided through the O2 ReadoutCard userspace driver, which handles synchronization and communication for direct memory access (DMA) transfers, provides base address registers (BAR) access, and facilitates card configuration and monitoring. The ReadoutCard driver is the lowest level interface to the readout cards within O-2 and is in use by all central systems and detector teams of the ALICE experiment. This communication presents the architecture of the driver and the suite of tools used for card configuration and monitoring. It also discusses its interaction with the tangent subsystems within the O-2 framework.

关键词： Base address register (BAR) data acquisition systems direct memory access (DMA) drivers field-programmable gate arrays

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A Multiplier-Free Convolution Neural Network Hardware Accelerator for Real-Time Bearing Condition Detection of CNC Machinery

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SENSORS 2023年第23期23卷 9437-9437页

作者： Liang, Yu-Pei Hung, Ming-You Chung, Ching-Che Natl Chung Cheng Univ Adv Inst Mfg High Tech Innovat Dept Comp Sci & Informat Engn Chiayi 621301 Taiwan

In various industrial domains, machinery plays a pivotal role, with bearing failure standing out as the most prevalent cause of malfunction, contributing to approximately 41% to 44% of all operational breakdowns. To address this issue, this research employs a lightweight neural network, boasting a mere 8.69 K parameters, tailored for implementation on an FPGA (field-programmable gate array). By integrating an incremental network quantization approach and fixed-point operation techniques, substantial memory savings amounting to 63.49% are realized compared to conventional 32-bit floating-point operations. Moreover, when executed on an FPGA, this work facilitates real-time bearing condition detection at an impressive rate of 48,000 samples per second while operating on a minimal power budget of just 342 mW. Remarkably, this system achieves an accuracy level of 95.12%, showcasing its effectiveness in predictive maintenance and the prevention of costly machinery failures.

关键词： fault diagnosis convolution neural networks incremental network quantization fixed-point arithmetic real-time systems field-programmable gate arrays digital circuits

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Implementation of field-programmable gate Array Platform for Object Classification Tasks Using Spike-Based Backpropagated Deep Convolutional Spiking Neural Networks

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MICROMACHINES 2023年第7期14卷 1353-1353页

作者： Kakani, Vijay Li, Xingyou Cui, Xuenan Kim, Heetak Kim, Byung-Soo Kim, Hakil Inha Univ Integrated Syst Engn 100 Inharo Incheon 22212 South Korea Inha Univ Elect & Comp Engn 100 Inharo Incheon 22212 South Korea Inha Univ Informat & Commun Engn 100 Inharo Incheon 22212 South Korea Korea Elect Technol Inst Res & Dev 25 KETI Seongnam Si 13509 South Korea

This paper investigates the performance of deep convolutional spiking neural networks (DCSNNs) trained using spike-based backpropagation techniques. Specifically, the study examined temporal spike sequence learning via backpropagation (TSSL-BP) and surrogate gradient descent via backpropagation (SGD-BP) as effective techniques for training DCSNNs on the field programmable gate array (FPGA) platform for object classification tasks. The primary objective of this experimental study was twofold: (i) to determine the most effective backpropagation technique, TSSL-BP or SGD-BP, for deeper spiking neural networks (SNNs) with convolution filters across various datasets;and (ii) to assess the feasibility of deploying DCSNNs trained using backpropagation techniques on low-power FPGA for inference, considering potential configuration adjustments and power requirements. The aforementioned objectives will assist in informing researchers and companies in this field regarding the limitations and unique perspectives of deploying DCSNNs on low-power FPGA devices. The study contributions have three main aspects: (i) the design of a low-power FPGA board featuring a deployable DCSNN chip suitable for object classification tasks;(ii) the inference of TSSL-BP and SGD-BP models with novel network architectures on the FPGA board for object classification tasks;and (iii) a comparative evaluation of the selected spike-based backpropagation techniques and the object classification performance of DCSNNs across multiple metrics using both public (MNIST, CIFAR10, KITTI) and private (INHA_ADAS, INHA_KLP) datasets.

关键词： field-programmable gate arrays neuromorphic image processing object classification performance spiking neural networks

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Current status and applications of time-to-digital converters

Current status and applications of time-to-digital converter...

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作者： Hanzhi Huang School of science Hebei University of Technology

Time-to-Digital Converter(TDC) is widely used to realize time interval *** high-precision time measurement technique has important applications in the fields of laser ranging, particle identification, and radioactive nuclear medicine engineering. Based on the existing literature research and data, this paper studies the application areas of TDC in the present development and analyzes the future prospects of TDC applications. The research results showed that: TDC, based on signal screening, realizes time interval measurement as the ultimate purpose of building the system and, at the same time, completes the function of multi-pulse time interval measurement, which can meet the needs of more diversified measurements in the *** the circuit structure, it can identify the feedback output in the all-digital phase-locked loop(ADPLL) and the reference clock phase and frequency information between the feedback output and the reference clock in an ADPLL. It is also promising for use in other areas of high-precision time measurement and processing of circuit signals.

关键词： Time-to-digital Converters All Digital Phase-locked Loops field-programmable gate arrays Time Pulses

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A Multi-Memory field-programmable Custom Computing Machine for Accelerating Compute-Intensive Applications 12

A Multi-Memory Field-Programmable Custom Computing Machine f...

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12th IEEE Annual Ubiquitous Computing, Electronics and Mobile Communication Conference (UEMCON)

作者： Jadhav, Shrikant S. Gloster, Clay Naher, Jannatun Doss, Christopher Kim, Youngsoo San Jose State Univ San Jose CA 95192 USA North Carolina A&T State Univ Greensboro NC USA Bradley Univ Peoria IL 61625 USA

ISBN: (纸本)9781665406901

In this paper, we present an FPGA-based multi-memory controller for accelerating computationally intensive applications. Our architecture accepts multiple inputs and produces multiple outputs for each clock cycle. The architecture includes processor cores with pipelined functional units tailored for each application. Additionally, we present an approach to achieve one to two orders-of-magnitude speedup over a traditional software implementation executing on a conventional multi-core processor. Even though the clock frequency of the field-programmable Custom Computing Machine (FCCM) is an order-of-magnitude slower than a conventional multi-core processor, the FCCM is significantly faster. We used the Power function as an application to demonstrate the merits of our FCCM. In our experiments, we executed the Power function in software and compared the software execution times with the execution time of an FCCM. Additionally, we also compared FCCM execution time with the OpenMP implementation of the function. Our experiments show that the results obtained using our multi-memory architecture are 57X faster than software implementation and 17X faster than OpenMP implementation executing the Power function, respectively.

关键词： Reconfigurable Computing field-programmable gate arrays field-programmable Custom Computing Machines High Performance Computing Multi-Memory Architecture Multiple Memory Banks

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