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Experimental Validation of a Novel Method for Harmonic Mitigation for a Three-Phase Five-Level Cascaded H-Bridges Inverter

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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS 2019年第6期55卷 6089-6101页

作者： Schettino, Giuseppe Viola, Fabio Di Tommaso, Antonino Oscar Livreri, Patrizia Miceli, Rosario Univ Palermo Dept Engn I-90133 Palermo Italy

Inmodern high-power electrical drives, the efficiency of the system is a crucial constraint. Moreover, the efficiency of power converters plays a fundamental role in modern applications requiring also a limited weight, such as the electric vehicles and novel more electric aircraft. The reduction of losses pushes for systems with a dc bus and a high number of dc/ac converters, widespread in the vehicle, not burdened by a too expensive data processing system. The purpose of this article is to concur to reduce losses by proposing an innovative selective harmonic mitigation method based on the identification of the working areas where the reference harmonics present lower amplitudes. In particular, the main objective is to find a new way to calculate the control angles in real-time operation without solving nonlinear equations, whose resolution would require expensive controllers. Through a very simple approach, the polynomial equations, which drive the control angles, were detected for a three-phase five-level cascaded H-bridge inverter and implemented in a digital system to real-time operation with a low computational cost. As a result, a comparison between the simulation and experimental behavior is presented. In the last part of this article, a real electric machine is driven by considering the appropriate working areas and current harmonics are also evaluated.

关键词： Cascade systems field-programmable gate arrays inverters multilevel systems power conversion harmonics

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field-programmable gate Array-Based Multichannel Measurement System for Interrogating Fiber Bragg Grating Sensors

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IEEE SENSORS JOURNAL 2019年第15期19卷 6163-6172页

作者： Yamaguchi, Latsuya Ishihara, Keisuke Shinoda, Yukitaka Nihon Univ Dept Elect Engn Coll Sci & Technol Tokyo 1010062 Japan Nihon Univ Dept Elect Engn Grad Sch Sci & Technol Tokyo 1010062 Japan

We develop a field-programmable gate array (FPGA)-based multichannel measurement system for sensing multiplexed fiber Bragg gratings (FBGs), using a high-speed wavelength-swept laser. The wavelength-swept laser, operated with Fourier-domain mode locking (FDML), exhibits a sweep frequency of 50.7 kHz and sweep band of similar to 60 nm. A breakthrough in multichannel and real-time measurement is achieved by implementing an FPGA with unique parallel-processing circuits. This FPGA enables the implementation of a high-speed centroid-peak-detection circuit for FBG detection, which can be operated with a sampling frequency of 250 MHz. In multichannel measurement systems, the light propagating through each sensor path produces a delay, which reduces the measurement accuracy. This can be solved by implementing a delay-correction technique, which utilizes the time difference between two spectra obtained by a bidirectional scan of the FDML laser. The system is demonstrated to exhibit multichannel sensing and high measurement time resolution of 9.9 mu s, without being affected by the delay.

关键词： field-programmable gate arrays optical fiber sensors sensor systems system integration

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A novel high speed Artificial Neural Network-based chaotic True Random Number Generator on field programmable gate Array

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2019年第3期47卷 365-378页

作者： Alcin, Murat Koyuncu, Ismail Tuna, Murat Varan, Metin Pehlivan, Ihsan Afyon Kocatepe Univ Fac Technol Dept Mechatron Engn TR-03200 Afyon Turkey Afyon Kocatepe Univ Fac Technol Dept Elect & Elect Engn Afyon Turkey Kirklareli Univ Tech Sci Vocat Sch Dept Elect Kirklareli Turkey Sakarya Univ Fac Technol Dept Elect Elect Engn Sakarya Turkey

It is well observed that cryptographic applications have great challenges in guaranteeing high security as well as high throughput. Artificial neural network (ANN)-based chaotic true random number generator (TRNG) structure has not been unprecedented in current literature. This paper provides a novel type of high-speed TRNG based on chaos and ANN implemented in a Xilinx field-programmable gate array (FPGA) chip. The paper consists of two main parts. In the first part, chaos analyses of Pehlivan-Uyaroglu_2010 chaotic system (PUCS) have been accomplished to prove that PUCS operates in chaotic regime. So PUCS can be an efficient alternative to the entropy source for classical TRNGs. In the second part, the hardware design of the proposed TRNG has been created using VHDL in Xilinx platform. As a result, the implemented TRNG offers throughput up to 115.794 Mbps. Besides, the generated random numbers have been tested with the FIPS 140-1 and NIST 800.22 test suites. The high quality of generated true random numbers have been confirmed by passing all randomness tests. The results have shown that the proposed system can provide not only high throughput but also high quality random bit sequences for a wide variety of embedded cryptographic applications.

关键词： artificial neural networks chaotic systems field-programmable gate arrays true random number generators VHDL

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Scheduling configuration memory error checks to improve the reliability of FPGA-based systems

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IET COMPUTERS AND DIGITAL TECHNIQUES 2019年第3期13卷 154-165页

作者： Nguyen Tran Huu Nguyen Cetin, Ediz Diessel, Oliver Ho Chi Minh City Univ Technol VNU HCM Sch Comp Sci & Engn 268 Ly Thuong Kiet Ho Chi Minh City Vietnam Macquarie Univ Sch Engn Sydney NSW 2109 Australia UNSW Sydney Sch Comp Sci & Engn Sydney NSW 2052 Australia

field-programmable gate arrays are susceptible to radiation-induced single event upsets. These are commonly dealt with using triple modular redundancy (TMR) and module-based configuration memory error recovery (MER). By triplicating components and voting on their outputs, TMR helps localise configuration memory errors, and by reconfiguring faulty components, MER swiftly corrects them. However, the order in which TMR voters are checked inevitably impacts the overall system reliability. In this study, the authors outline an approach for computing the reliability of TMR-MER systems that consist of finitely many components. They demonstrate that system reliability is improved when the more vulnerable components are checked more frequently than when they are checked in round-robin order. They propose a genetic algorithm for finding a voter checking schedule that maximises the reliability of TMR-MER systems. Results indicate that the mean time to failure (MTTF) of these systems can be increased by up to 400% when variable-rate voter checking (VRVC) is used instead of round robin. They show that VRVC achieves 15-23% increase in MTTF with a 10x reduction in checking frequency to reduce system power. They also found that VRVC detects errors 44% faster on average than round robin.

关键词： fault tolerant computing field programmable gate arrays genetic algorithms reconfigurable architectures radiation hardening (electronics) scheduling configuration memory error checks FPGA-based systems field-programmable gate arrays radiation-induced single event upsets triple modular redundancy configuration memory error recovery localise configuration memory errors faulty components TMR voters system reliability TMR-MER systems vulnerable components voter checking schedule variable-rate voter checking system power

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A 47.14-$\mu\text{W}$ 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2019年第11期54卷 2991-3004页

作者： Natsui, Masanori Suzuki, Daisuke Tamakoshi, Akira Watanabe, Toshinari Honjo, Hiroaki Koike, Hiroki Nasuno, Takashi Ma, Yitao Tanigawa, Takaho Noguchi, Yasuo Yasuhira, Mitsuo Sato, Hideo Ikeda, Shoji Ohn, Hideo Endoh, Tetsuo Hanyu, Takahiro Tohoku Univ Res Inst Elect Commun Lab Brainware Syst Sendai Miyagi 9808577 Japan Tohoku Univ Ctr Spintron Integrated Syst Sendai Miyagi 9808577 Japan Tohoku Univ Ctr Innovat Integrated Elect Syst Sendai Miyagi 9808577 Japan Tohoku Univ Res Inst Elect Commun Sendai Miyagi 9808577 Japan Tohoku Univ Ctr Innovat Integrated Elect Syst Sendai Miyagi 9808572 Japan Tohoku Univ Ctr Spintron Integrated Syst Grad Sch Engn Sendai Miyagi 9808572 Japan Tohoku Univ Ctr Spintron Integrated Syst Sendai Miyagi 9808572 Japan Tohoku Univ Ctr Spintron Res Network Sendai Miyagi 9808572 Japan Tohoku Univ Res Inst Elect Commun Sendai Miyagi 9808572 Japan Tohoku Univ WPI Adv Inst Mat Res Sendai Miyagi 9808577 Japan Tohoku Univ Ctr Spintron Res Network Sendai Miyagi 9808577 Japan Tohoku Univ Grad Sch Engn Sendai Miyagi 9808572 Japan

The demand for energy-efficient, high-performance microcontroller units (MCUs) for the use in power-supply-critical Internet-of-Things (IoT) sensor-node applications has witnessed a substantial increase. In response, research concerning the development of several low-power-consuming MCUs has been actively pursued. The performance level of such MCUs, however, has not been sufficient, thereby rendering them non-feasible for the use in IoT sensor-node applications that process a large number of received signals immediately followed by extraction of valuable information from them to limit data transferred to a data center. To realize next-generation IoT systems based on intelligent sensor-node application, ultra-low-power high-performance MCUs need to be developed. This paper presents an ultra-low-power-consuming and high-performance MCU configuration based on the spintronics device technology, using which all modules are non-volatilized, and any wasteful power consumption is eliminated by controlling the power supplied independently to each module. By incorporating a reconfigurable accelerator module, for performing various signal-processing procedures in sensor-node applications, and a memory controller, which can speed up the entire system by relaxing the data-transfer bottleneck of logic and memory, the proposed MCU configuration achieves ultra-low power consumption and high-speed operation. As confirmed by the results obtained via measurements performed on a fabricated chip, the proposed MCU design, on average, consumed 47.14 $\mu \text{W}$ power at an operating frequency of 200 MHz. This corresponds to the world's highest signal-processing performance and energy efficiency of highly functional IoT sensor nodes powered by harvested energy

关键词： Nonvolatile memory Spintronics Performance evaluation Magnetic tunneling Central Processing Unit Memory management Standards Energy harvesting field-programmable gate arrays Internet of Things magnetic tunnel junction microcontroller unit (MCU) spin-transfer-torque magnetoresistive random access memory (STT-MRAM)

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Automatic illumination control for an endoscopy sensor

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MICROPROCESSORS AND MICROSYSTEMS 2020年第0期72卷 102920-000页

作者： Sousa, Ricardo M. Wanya, Martin Santos, Pedro Morgado-Dias, F. AMS Lda P-9020105 Funchal Portugal ITI Larsys & Madeira Interact Technol Inst P-9020105 Funchal Portugal Univ Madeira Rua Ferreiros P-9000082 Funchal Portugal

Endoscopy and small surgery can be performed with the support of small cameras. These cameras need to be minimal to reduce intrusion, require fast response and automatic illumination. The current work describes the world's smallest camera for endoscopy, NanEye, and the dynamic control algorithm for ROI developed for the illumination LED source coupled to the camera head that allows adjusting light, gain and exposure time. The obtained results show that it is capable of achieving correction speeds under 1 s while maintaining a static error below 3% relative to the total number of pixels of the image. The result of this work will allow the integration of high brightness LED sources of millimeter size on a very small camera enabling its use in endoscopic surgical robotic operations or minimal invasive surgery and NanEye is expected to be supplied at low prices for single time use. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Automatic Illumination Control CMOS image sensors LED lighting Medical Imaging field-programmable gate arrays

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Dynamic partial reconfiguration enchanced with security system for reduced area and low power consumption

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MICROPROCESSORS AND MICROSYSTEMS 2020年 76卷 103088-103088页

作者： Ram, R. Saravana Prabhaker, M. Lordwin Cecil Suresh, K. Subramaniam, Kamalraj Venkatesan, M. Anna Univ Univ Coll Engn Dindigul Dept ECE Dindigul Tamil Nadu India Vel Tech R Dr S R&D Inst Sci & Technol Dept ECE Chennai Tamil Nadu India Sree Vidyanikethan Engn Coll Dept EEE Tirupati Andhra Pradesh India Karpagam Acad Higher Educ Dept ECE Coimbatore Tamil Nadu India Vignans Lara Inst Technol & Sci Dept EEE Guntur Andhra Pradesh India

field-programmable gate arrays (FPGAs) have travelled far from just being utilized as glue logic to an entire system solution. This is mostly due to their generalized re-configurable nature, lower non-recurring engineering (NRE) expense, and also fast time to market. Owing to the reconfigurable nature of FPGA, a new field called reconfigurable computing that can change the circuit configuration after hardware production came into existence. Application of re-configurable computing for self-adaptive hardware allows hardware to get adapt to various environmental conditions and different needs by swapping or loading disparate computational modules. This work proposes an effectual design methodology (enhanced DPR security system (EDPRSS)) utilized to execute high performance FPGA device in respect of low power consumption along with security for the area reduction. In the proposed technique, hash code generation (HCG) and encryption hardware accelerators can well be dynamically produced on FPGA utilizing partial re-configuration as stated by the application requisites. The system is competent to swap in or swap out the equivalent hardware accelerator during run time, which in turn diminishes the power and area. Here, 2 re-configurable partitions are produced for encryption and also HCG algorithm. Experiential outcomes proved that the proposed technique proffers better performance when contrasted to the other conventional systems. (C) 2020 Elsevier B.V. All rights reserved.

关键词： field-programmable gate arrays Dynamic partial reconfiguration Reconfigurable parallel computing and security Data Encryption Standard (DES) HCG algorithm

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Hardware Root-of-Trust-based integrity for shared library function pointers in embedded systems

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MICROPROCESSORS AND MICROSYSTEMS 2020年 79卷 103270-103270页

作者： Coppock, Patrick H. Yacoub, Momen K. Qin, Bruce L. Daftardar, Alhad J. Tolaymat, Zayd Mooney, Vincent J., III Georgia Inst Technol Comp Engn Atlanta GA 30332 USA Georgia Inst Technol Atlanta GA 30332 USA Georgia Inst Technol Elect Engn Atlanta GA 30332 USA Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA Georgia Inst Technol Sch Comp Sci Atlanta GA 30332 USA

Many security measures designed for large-scale compute hardware (e.g., workstations and servers) are not optimized for embedded systems. One such measure, Relocation Read-Only (RelRO), protects binary relocation sections from tampering after dynamic linking;however, RelRO depends on the presence of memory management hardware that not all embedded systems include. More generally, the latest hardware modifications to processor architectures may not always be available to provide security in small-scale embedded systems. In this paper, we propose another solution for relocation protection for use in embedded systems that have a field programmable gate array (FPGA) on chip. Our solution prevents relocation section overwrites from diverting control flow as they would in an unprotected binary by implementing a hardware Root of Trust into which to store and out of which to retrieve shared library function pointers. We offer two system variations which provide designers with flexibility to choose a lighter or a more robust protection. We also demonstrate a proof of concept implemented on a popular FPGA development board and provide comparison with RelRO. Our work provides embedded system developers with a security measure like RelRO without requiring a customized memory management unit. Our work is useful on computer systems that include embedded reconfigurable logic on chip. The authors believe this is the first paper in which reconfigurable logic is used to provide security functionality previously implemented in a custom instruction set or other computer architecture modifications. Our work points toward a future where FPGA logic embedded on chip can be adapted to improve the security of software.

关键词： Computer security Embedded software field-programmable gate arrays Reconfigurable architectures Runtime environment Runtime library

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Maverick: A Stand-alone CAD Flow for Partially Reconfigurable FPGA Modules 27

Maverick: A Stand-alone CAD Flow for Partially Reconfigurabl...

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27th IEEE Annual International Symposium on field-programmable Custom Computing Machines (FCCM)

作者： Glick, Dallon Grigg, Jesse Nelson, Brent Wirthlin, Michael Brigham Young Univ Dept Elect & Comp Engn NSF Ctr Space High Performance & Resilient Comp S Provo UT 84602 USA

ISBN: (纸本)9781728111315

This paper presents Maverick, a proof-of-concept computer-aided design (CAD) flow for generating reconfigurable modules (RMs) which target partial reconfiguration (PR) regions in field-programmable gate array (FPGA) designs. After an initial static design and PR region are created with Xilinx's Vivado PR flow, the Maverick flow can then compile and configure RMs onto that PR region-without the use of vendor tools. Maverick builds upon existing open source tools (Yosys, RapidSmith2, and Project X-Ray) to form an end-to-end compilation flow. This paper describes the Maverick flow and shows the results of it running on a PYNQ-Z1's ARM processor to compile a set of HDL designs to partial bitstreams. The resulting bitstreams were configured onto the PYNQ-Z1's FPGA fabric, demonstrating the feasibility of a single-chip embedded system which can both compile HDL designs to bitstreams and then configure them onto its own programmable fabric.

关键词： field-programmable gate arrays Partial reconfiguration Electronic design automation and methodology RapidSmith

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Real-Time State Estimation and Voltage Stability Assessment of Power Grids: From Theoretical Foundations to Practical Applications

Real-Time State Estimation and Voltage Stability Assessment ...

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作者： Andreas Martin KETTNER ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE

学位级别：博士

The operators of power distribution systems strive to lower their operational costs and improve the quality of the power service provided to their customers. Furthermore, they are faced with the challenge of accommodating large numbers of Distributed Energy Resources (DERs) into their grids. It is expected that these problems will be tackled with a large-scale deployment of automation technology, which will enable the real-time monitoring and control of power distribution systems (i. e., similar to power transmission systems). For this purpose, real-time situation awareness w. r. t. the state and the stability of the system is needed. In view of the deployment of such automation functions into power distribution grids, there are two binding requirements. Firstly, the system models have to account for the inherent unbalances of power distribution systems (i. e., w. r. t. the components of the grid and the loads). Secondly, the analysis methods have to be real-time capable when deployed into low-cost embedded systems platforms, which are the cornerstones of automation. In other words, the analysis methods need to be computationally efficient. This thesis focuses on the modeling of unbalanced polyphase power systems, as well as the development, validation, and deployment of real-time methods for State Estimation (SE) and Voltage Stability Assessment (VSA) for such systems. More precisely, the following theoretical and practical contributions are made to the field of power system engineering. 1. Fundamental properties of the compound admittance matrix of polyphase power grids are identified. Specifically, theorems w. r. t. the rank of the compound admittance matrix, the feasibility of Kron Reduction (KR), and the existence of compound hybrid matrices are stated and formally proven. These theorems hold for generic polyphase power grids (i. e., which may be unbalanced, and have an arbitrary number of phases). 2. A Voltage Stability Index (VSI) for real-time VSA of polypha

关键词： power distribution systems automation active distribution networks microgrids polyphase power systems unbalanced power grids compound admittance matrix compound hybrid matrix Kron reduction state estimation sequential Kalman filter phasor measurement units voltage stability assessment voltage stability index L -index Thevenin equivalent polynomial load model embedded systems field-programmable gate arrays COMMELEC

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