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High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applications

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COMPUTATIONAL INTELLIGENCE 2021年第3期37卷 1056-1067页

作者： Sikka, Prateek Asati, Abhijit R. Shekhar, Chandra Birla Inst Technol & Sci Elect & Elect Engn Dept Vidya Vihar Campus Pilani Rajasthan India

Sobel edge detector is an algorithm commonly used in image processing and computer vision to extract edges from input images using derivative of image pixels in x and y directions against surrounding pixels. Most artificial intelligence and machine learning applications require image processing algorithms running in real time on hardware systems like field-programmable gate array (FPGAs). They typically require high throughput to match real-time speeds and since they run alongside other processing algorithms, they are required to be area efficient as well. This article proposes a high-speed and low-area implementation of the Sobel edge detection algorithm. We created the design using a novel high-level synthesis (HLS) design method based on application specific bit widths for intermediate data nodes. Register transfer level code was generated using MATLAB hardware description language (HDL) coder for HLS. The generated HDL code was implemented on Xilinx Kintex 7 field programmable gate array (FPGA) using Xilinx Vivado software. Our implementation results are superior to those obtained for similar implementations using the vendor library block sets as well as those obtained by other researchers using similar implementations in the recent past in terms of area and speed. We tested our algorithm on Kintex 7 using real-time input video with a frame resolution of 1920 x 1080. We also verified the functional simulation results with a golden MATLAB implementation using FPGA in the loop feature of HDL Verifier. In addition, we propose a generic area, speed, and power improvement methodology for different HLS tools and application designs.

关键词： field-programmable gate array hardware description language high-level synthesis MATLAB HDL coder register transfer language Sobel edge detection Vivado

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Modified artificial bee colony optimisation based FIR filter design with experimental validation using field-programmable gate array

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IET SIGNAL PROCESSING 2016年第8期10卷 955-964页

作者： Dwivedi, Atul Kumar Ghosh, Subhojit Londhe, Narendra D. NIT Raipur Dept Elect Engn Raipur Madhya Pradesh India

Optimisation based design of finite impulse response (FIR) filters has been an active area of research for quite some time. The various algorithms proposed for FIR filter design aim at meeting a set of desired specifications in the frequency domain. Evolutionary algorithms have been found to be very effective for FIR filter design because of the non-linear, non-differentiable and non-convex nature of the associated optimisation problem. The present work proposes two modified versions of a recently developed evolutionary technique i.e. artificial bee colony (ABC) algorithm for design of FIR filters. The applicability of the proposed approach has been evaluated by comparing its response with conventional reported filter design techniques. The proposed variants of ABC are found to outperform other non-convex algorithms in achieving the desired specifications. In addition to the simulation results, the designed filters have been implemented in hardware using Xilinx-xc7vx330t-3ffg1157 (Virtex-7) field programmable gate array. The hardware implementation allows validation of the proposed techniques for practical filtering applications by considering real time operation parameters.

关键词： FIR filters evolutionary computation modified artificial bee colony optimisation based FIR filter design field-programmable gate array finite impulse response filters frequency domain evolutionary algorithms real time operation parameters Xilinx-xc7vx330t-3ffg1157 FPGA

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Development of low-complexity all-digital frequency locked loop as 500 MHz reference clock generator for field-programmable gate array

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IET CIRCUITS DEVICES & SYSTEMS 2014年第2期8卷 73-81页

作者： Yuwono, Sigit Han, Seok-Kyun Yoon, Giwan Cho, Han-Jin Lee, Sang-Gug Korea Adv Inst Sci & Technol Dept Informat & Commun Engn Taejon 305701 South Korea Korea Adv Inst Sci & Technol Dept Elect Engn Taejon 305701 South Korea ETRI SW SoC Convergence Res Lab Taejon South Korea

The authors report the development of an on-chip 500 MHz reference clock generator as a part of a clock manager for a field-programmable gate array. The generator is implemented in the form of an all-digital frequency locked loop (ADFLL) in architecture of low complexity and high modularity. For the development of the ADFLL, they propose a new circuit that employs two under-sampled 1-bit Delta sigma frequency-to-digital converters to convert a frequency difference into a proportional distributed pulsewidth. By the combination of the proposed circuit with a conventional phase-and-frequency detector, a frequency comparator is implemented and can indicate its two input frequency conditions, that is, (i) equal to, (ii) lower than or (iii) higher than. The ADFLL which adopts the proposed frequency comparator is implemented in a 90 nm CMOS technology. Consuming 2.64 mW from a 1.2 V supply, the ADFLL shows about 50 mu s of locking time at the frequency accuracy of 99.2% while operating at 500 MHz and being driven by a 10 MHz reference clock.

关键词： phase-and-frequency detector ADFLL frequency 500 MHz phase detectors distributed pulsewidth word length 1 bit under-sampled Î”Î£ frequency-to-digital converters size 90 nm field-programmable gate array delta-sigma modulation on-chip reference clock generator CMOS technology frequency locked loops comparators (circuits) field programmable gate arrays reference circuits power 2.64 mW low-complexity all-digital frequency locked loop voltage 1.2 V frequency comparator CMOS logic circuits

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Low power 2D finite impulse response filter design using modified artificial bee colony algorithm with experimental validation using field-programmable gate array

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IET SCIENCE MEASUREMENT & TECHNOLOGY 2016年第6期10卷 671-678页

作者： Dwivedi, Atul Kumar Ghosh, Subhojit Londhe, Narendra D. NIT Raipur Dept Elect Engn Raipur Madhya Pradesh India

Motivated by the need of reducing power consumption (PC) in two dimensional (2D) finite impulse response (FIR) filters, in this work, the 2D FIR filter design task is formulated as an optimisation problem that seeks to attain the desired frequency response and reduces PC. The optimisation problem has been solved using the modified version of artificial bee colony algorithm. The applicability of the proposed approach has been evaluated by designing circular shaped 2D FIR filters for a set of specifications in frequency domain. The designed filters have been compared with other reported state of the art techniques. The evaluation is carried out in terms of pass band and stop band ripple minimisation, convergence profile and PC during filter execution in hardware. The proposed technique is found to outperform all other techniques in achieving minimum ripple for a given filter order. To prove the effectiveness of the proposed approach for PC reduction, the designed filters have been implemented in hardware using field-programmable gate array (xc7vx485t-2ffg1761). The PC computed using Xilinx X-power analyser shows that 23.53% power can be saved using the proposed approach as compared with conventional design approaches.

关键词： FIR filters field programmable gate arrays singular value decomposition band-pass filters band-stop filters minimisation low power 2D finite impulse response filter design modified artificial bee colony algorithm field-programmable gate array cooling maintenance power consumption PC low power two-dimensional FIR filter singular value decomposition Hamming distance optimisation problem circular shaped 2D FIR filter frequency domain analysis pass band ripple minimisation stop band ripple minimisation Xilinx X-power analyser

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Efficient field-programmable gate array implementation of CCSDS 121.0-B-2 lossless data compression algorithm for image compression

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JOURNAL OF APPLIED REMOTE SENSING 2015年第1期9卷 097499-1-097499-15页

作者： Kranitis, Nektarios Sideris, Ioannis Tsigkanos, Antonios Theodorou, Georgios Paschalis, Antonios Vitulli, Raffaele Univ Athens Dept Informat & Telecommun Digital Syst & Comp Architecture Lab Athens 15784 Greece European Space Agcy NL-2201 AZ Noordwijk Netherlands

The Consultative Committee for Space Data Systems (CCSDS) 121.0-B-2 lossless data compression standard defines a lossless adaptive source coding algorithm which is applicable to a wide range of imaging and nonimaging data. We introduce a field-programmable gate array (FPGA) implementation of CCSDS 121.0-B-2 as an intellectual property (IP) core with the following features: (a) it is enhanced with a two-dimensional (2-D) second-order predictor making it more suitable for image compression, (b) it is enhanced with near-lossless compression functionality, (c) its parallel, pipelined architecture provides high data-rate performance with a maximum achievable throughput of 205 Msamples/s (3.2 Gbps at 16 bit) when targeting the Xilinx Virtex-5QV FPGA, and (d) it requires very low FPGA resources. When mission requirements impose lossless image compression, the CCSDS 121.0-B-2 IP core provides a very low implementation cost solution. According to European Space Agency PROBA-3 Bridging Phase, the CCSDS 121.0-B-2 IP core will be implemented in a Microsemi RTAX2000 FPGA, hosted in the data processing unit of the Coronagraph Control Box, of the Association of Spacecraft for Polarimetric and Imaging Investigation of the Corona of the Sun Coronagraph System Payload. To the best of our knowledge, it is the fastest FPGA implementation of CCSDS 121.0-B-2 to date, also including a 2-D second-order predictor making it more suitable for image compression. (C) 2015 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： lossless data compression image compression Consultative Committee for Space Data Systems on-board payload data processing field-programmable gate array

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Remote web-based control laboratories using embedded Linux and field-programmable gate array

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PROCEEDINGS OF THE INSTITUTION OF MECHANICAL ENGINEERS PART I-JOURNAL OF SYSTEMS AND CONTROL ENGINEERING 2018年第9期232卷 1146-1154页

作者： Jaziri, Ibtihel Charaabi, Lotfi Jelassi, Khaled Univ Tunis El Manar Ecole Natl Ingn Tunis Lab Syst Elect LR11ES15 Tunis 1002 Tunisia

In this article, the authors present a new approach based on the hardware and software architecture using embedded Linux and field-programmable gate array for implementation of remote laboratories. It combines a set of software and hardware resources in the interest of offering a multidisciplinary low-cost open platform for engineering education. Thus, the proposed approach allows students to develop low-cost and easily programmable prototypes of electrical systems control, robotics, and other embedded devices that feature Internet connectivity, Input/output, networking, and operating systems. In the proposed work, the authors present a codesign solution with flexible hardware devices, providing characteristics of multipurpose use with many experimental devices, and fully configurable graphical user interface. The physical setup and communication principles of hardware architecture are based on two types of devices: the Beaglebone running embedded Linux operating system and the field-programmable logic gate array. The graphical user interface is designed as a web page based on HTML and PHP programming languages;this allows the teachers/students to control the system easily, parameterize, and observe the behavior of the controller/system remotely.

关键词： Remote laboratory control education embedded Linux field-programmable gate array embedded web server

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An efficient field-programmable gate array-based hardware oriented block motion estimation algorithm based on diamond adaptive rood pattern search algorithm for multi-standard video codec

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TRANSACTIONS OF THE INSTITUTE OF MEASUREMENT AND CONTROL 2021年第16期43卷 3672-3685页

作者： Balamurugan, S. M. Seshasayanan, R. Anna Univ Dept Elect & Commun Engn Chennai 600025 Tamil Nadu India

Motion estimation and motion compensation techniques are effectively used for removing temporal redundancy between adjacent frames during video compression, but video quality will be degraded with the traditional pixel-based matching algorithms. To overcome this issue, diamond adaptive rood pattern search algorithm-based block-matching motion estimation algorithms are proposed in this manuscript for multi-stranded codec hardware design, which provide a high compression rate with less computational complexity. In this work, a diamond adaptive rood pattern search algorithm is used, which is a combination of a diamond-search algorithm and adaptive rood pattern search. In addition, the proposed algorithm applies multiple search strategies and terminates unnecessary searching while reserving high data regularity. The proposed diamond adaptive rood pattern search algorithm-based block-matching motion estimation algorithm for multi-stranded codec hardware design provides good performance in terms of complex calculations reduction and reaches a high speed in comparison to traditional search algorithms. The proposed architecture is implemented in Xilinx ISE design 14.5 suite and the implemented results are compared to the existing motion estimation techniques on field-programmable gate array devices. Simulation results shows that the diamond adaptive rood pattern search algorithm for multi-stranded codec hardware design provides a very good improvement in terms of computations overhead reduction, with 96.4%, 97.3% latency and 98.7% throughput and achieves a high compression rate without video quality degradation.

关键词： Motion estimation block-based matching algorithms (BMAs) field-programmable gate array adaptive rood pattern search (ARPS) diamond search algorithm

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A Low-cost Reconfigurable field-programmable gate array Based Three-phase Shunt Active Power Filter for Current Harmonic Elimination and Power Factor Constraints

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ELECTRIC POWER COMPONENTS AND SYSTEMS 2014年第16期42卷 1811-1825页

作者： Siluvaimuthu, Charles Chenniyappan, Vivekanandan Sri Shakthi Inst Engn & Technol Dept Elect & Elect Engn Coimbatore 641062 Tamil Nadu India SNS Coll Engn Dept Elect & Elect Engn Coimbatore Tamil Nadu India

Non-linear loads, such as switched mode power supply, adjustable-speed drives, arc furnaces, etc., result in deterioration of power quality in terms of current harmonics and reactive power demand. Shunt active power filters are widely used to compensate the current harmonics, thereby improving power quality. Digital signal processors and microcontroller units used in digital control of shunt active power filters are constrained by a complex algorithm structure, adaptability, accuracy, the absence of feedback loop delays, and larger execution time. Shunt active power filters require a faster computation update rate to maintain the closed-loop bandwidth, accurate sensing of voltage and current, proper estimation of parameters, and a high frequency pulse-width modulation. In this article, a low-cost single all-on-chip field-programmable gate array implements the digital control of a three-phase shunt active power filter. This proposed implementation scheme has much less execution time and boosts the overall performance of the system. All required tasks of a typical shunt active power filter are implemented with a low-cost single all-on chip field-programmable gate array module that provides freedom to reconfigure for any other applications. Additional features, such as anti-windup, over-sampling, and time multiplexing, are also added to improve the overall performance. The proposed system is designed to meet IEEE 519 and IEC EN 61000-3 recommendations in terms of harmonic elimination and unity power factor requirements. The entire algorithm is coded, processed, and simulated using Xilinx 12.1 ISE Suite to estimate the advantages of the proposed system. This code is also defused on the low-cost single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype, and experimental results obtained match with simulated counterparts. The proposed control scheme for the shunt active power filter results in reduces current harmonics under dynamic and steady-state operatin

关键词： shunt active power filter reactive power synchronous reference frame harmonic compensation digital control field-programmable gate array

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A field-programmable gate array system for sonar image recognition based on convolutional neural network

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PROCEEDINGS OF THE INSTITUTION OF MECHANICAL ENGINEERS PART I-JOURNAL OF SYSTEMS AND CONTROL ENGINEERING 2021年第10期235卷 1808-1818页

作者： Wang, Chong Jiang, Yu Wang, Kai Wei, Fenglin Jilin Univ Coll Comp Sci & Technol Changchun 130012 Peoples R China

Subsea pipeline is the safest, most reliable, and most economical way to transport oil and gas from an offshore platform to an onshore terminal. However, the pipelines may rupture under the harsh working environment, causing oil and gas leakage. This calls for a proper device and method to detect the state of subsea pipelines in a timely and precise manner. The autonomous underwater vehicle carrying side-scan sonar offers a desirable way for target detection in the complex environment under the sea. As a result, this article combines the field-programmable gate array, featuring high throughput, low energy consumption and a high degree of parallelism, and the convolutional neural network into a sonar image recognition system. First, a training set was constructed by screening and splitting the sonar images collected by sensors, and labeled one by one. Next, the convolutional neural network model was trained by the set on the workstation platform. The trained model was integrated into the field-programmable gate array system and applied to recognize actual datasets. The recognition results were compared with those of the workstation platform. The comparison shows that the computational precision of the designed field-programmable gate array system based on convolutional neural network is equivalent to that of the workstation platform;however, the recognition time of the designed system can be saved by more than 77%, and its energy consumption can also be saved by more than 96.67%. Therefore, our system basically satisfies our demand for energy-efficient, real-time, and accurate recognition of sonar images.

关键词： Autonomous underwater vehicle field-programmable gate array convolutional neural network sonar image recognition

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A 16-NM MULTIPROCESSING SYSTEM-ON-CHIP field-programmable gate array PLATFORM

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IEEE MICRO 2016年第2期36卷 48-62页

作者： Ahmad, Sagheer Boppana, Vamsi Ganusov, Ilya Kathail, Vinod Rajagopalan, Vidya Wittig, Ralph Xilinx SoC Bangalore Karnataka India Xilinx Bangalore Karnataka India Xilinx Proc Syst Software & Applicat Engn Bangalore Karnataka India Xilinx Comp Platforms Bangalore Karnataka India

THE ZYNQ ULTRASCALE+ MPSOC INCREASES PERFORMANCE AND POWER EFFICIENCY, ADDS SYSTEM-WIDE COHERENCY AND SHARED VIRTUAL MEMORY BETWEEN THE SOC AND THE field-programmable gate array (FPGA), AND RAISES THE PROGRAMMING ABSTRACTION BY INTRODUCING A HETEROGENEOUS, SYSTEM-WIDE COMPILER. THE SDSOC ENVIRONMENT COMBINES THE ARM COMPILER WITH A HIGH-LEVEL SYNTHESIS TECHNOLOGY-BASED FPGA COMPILER AND A FULL-SYSTEM OPTIMIZING COMPILER TO TARGET ALL ELEMENTS OF THE HETEROGENEOUS SOC FROM A COMMON PROGRAM SOURCE.

关键词： field programmable gate arrays field-programmable gate array Memory management Microprocessors multiprocessor Random access memory Real-time systems Streaming media system on chip Zynq

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