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11th IEEE Annual Ubiquitous Computing, Electronics and Mobile Communication Conference (UEMCON)

作者： Lin, Xianghong Lu, Han Pi, Xiaomei Wang, Xiangwen Northwest Normal Univ Coll Comp Sci & Engn Lanzhou 730070 Peoples R China

ISBN: (纸本)9781728196565

In the innovative neural prostheses, the biological cell assemblies of the biological nervous system can be replaced by artificial organs, which makes the idea of dynamically interface biological neurons even more urgent. To mimic and investigate the activity of biological neural networks, many different architectures and technologies in the field of neuromorphic have been developed at present. When structuring simple neuron models, researchers use field programmable gate arrays (FPGAs) to obtain better accuracy and real-time performance. This paper uses FPGAs to achieve the circuit design of the neuron model, such that based on the biologically plausible the quadratic spiking neuron model, can simulate the neuron spiking behaviors of thalamus neurons and hippocampal CA1 pyramidal neurons. After the FPGA hardware architecture of the neuron model is designed and implemented, this model can better simulate the spiking behaviors observed in biological neurons.

关键词： quadratic spiking neuron model Neuromorphic field-programmable gate array hardware implementation

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Two-tone distortion products in hardware-efficient cochlea model based on asynchronous cellular automaton oscillator

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IEICE ELECTRONICS EXPRESS 2021年第18期18卷 20210310-20210310页

作者： Takeda, Kentaro Torikai, Hiroyuki Hosei Univ Grad Sch Sci & Engn 3-7-2 Kajino Sho Koganei Tokyo 1848584 Japan

In this paper, we present a cochlea model whose nonlinear dynamics are described by an asynchronous cellular automaton. Our proposed model is demonstrated to enable the reproduction of two-tone distortion products. The proposed model is implemented on a field-programmable gate array (FPGA). It is subsequently demonstrated that our proposed model can be implemented using fewer hardware resources than a conventional cochlea model, which is a Hopf-type cochlea model, implemented on a digital signal processor performing a numerical integration.

关键词： cochlea field-programmable gate array Hopf oscillator asynchronous cellular automaton

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ME-TCAM: Memory-Efficient Ternary Content Addressable Memory Based on Multipumping-Enabled LUTRAM on FPGA

ME-TCAM: Memory-Efficient Ternary Content Addressable Memory...

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International Conference on Intelligent Computing and Human-Computer Interaction (ICHCI)

作者： Shi, Zilin Yang, Hui Liu, Rulin Yan, Jinli Qiao, Peng Wang, Baosheng Natl Univ Def Technol Coll Comp Sci & Technol Changsha Peoples R China Natl Univ Def Technol Sci & Technol Parallel & Distributed Proc Lab PDL Changsha Peoples R China

ISBN: (纸本)9781665423168

Static random access memory (SRAM) on field programmable gate arrays (FPGAs) can be emulated to offer ternary content addressable memory (TCAM) functionality. However, SRAM-based TCAM wastes storage resources. This is due to the limited capacity of the physical addresses in the SRAM unit. This work proposes a LUTRAM-based TACM scheme on the FPGA called Memory-Efficient TCAM (ME-TCAM). ME-TCAM divides SRAM unit into multiple virtual blocks mapping to a portion of the TCAM table to store the more address information of the TCAM table. Operation on SRAM block means that increasing the overall emulated TCAM bits/SRAM. Moreover, ME-TCAM exploits Xilinx primitives to configure lookup tables (LUTs) as 32 x 2 lookup table RAMs (LUTRAMs). We implement ME-TCAM using LUTRAM with a size of 512 x 48 and 1024 x 144 on a Virtex-7 FPGA device. Compared with the state-of-the-art research DURE, ME-TCAM achieves at least 2.6 times more memory efficiency.

关键词： static random access memory ternary content addressable memory sram-based tcam field-programmable gate array multipumping technology

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Local Spatio-Temporal Propagation Based Adaptive Model Generation and Update for High Frame Rate and Ultra-Low Delay Foreground Detection 26

Local Spatio-Temporal Propagation Based Adaptive Model Gener...

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IEEE 26th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

作者： Cai, Peikun Du, Songlin Ikenaga, Takeshi Waseda Univ Grad Sch Informat Prod & Syst Kitakyushu Fukuoka Japan Southeast Univ Sch Automat Nanjing Peoples R China

ISBN: (纸本)9781728144030

High frame rate and ultra-low delay matching system plays an increasingly important role in human-machine interactive applications, which demands better experience and higher accuracy. Foreground detection is an indispensable preprocessing step to make the system suitable for complex scenes. Although many foreground detection algorithms have been proposed, few can achieve high speed in hardware due to their high complexity or high consumption. Based on the foreground detection algorithm ViBe, this paper proposes a local spatio-temporal propagation based adaptive model generation and update strategy for high frame rate and ultra-low delay foreground detection. Our algorithm predicts whether a region is a foreground by setting up detecting points, thereby adaptively adjusting the number of pixels that needs to be modeled. Secondly, the local linear illumination correlation is used to update models, which makes the algorithm more robust to illumination changes. The evaluation results show that the proposed algorithm successfully achieves real-time processing on the field-programmable gate array (FPGA) at a resolution of 640x480 pixels, with a delay of 0.908ms/frame.

关键词： foreground detection high frame rate ultra-low delay real-time processing field-programmable gate array

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Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks 16th

Improving Performance Estimation for FPGA-Based Accelerators...

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16th International Symposium on Applied Reconfigurable Computing

作者： Ferianc, Martin Fan, Hongxiang Chu, Ringo S. W. Stano, Jakub Luk, Wayne UCL Dept Elect & Elect Engn London England Imperial Coll London Dept Comp London England UCL Dept Comp Sci London England Swiss Fed Inst Technol Dept Informat Technol & Elect Engn Zurich Switzerland

ISBN: (纸本)9783030445331;9783030445348

field-programmable gate array (FPGA) based accelerators are being widely used for acceleration of convolutional neural networks (CNNs) due to their potential in improving the performance and reconfigurability for specific application instances. To determine the optimal configuration of an FPGA-based accelerator, it is necessary to explore the design space and an accurate performance prediction plays an important role during the exploration. This work introduces a novel method for fast and accurate estimation of latency based on a Gaussian process parametrised by an analytic approximation and coupled with runtime data. The experiments conducted on three different CNNs on an FPGA-based accelerator on Intel Arria 10 GX 1150 demonstrated a 30.7% improvement in accuracy with respect to the mean absolute error in comparison to a standard analytic method in leave-one-out cross-validation.

关键词： field-programmable gate array Deep learning Convolutional neural network Performance estimation Gaussian process

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An easy to implement logic analyzer for long-term precise measurements

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HARDWAREX 2021年 9卷 e00164页

作者： Romanov, Alexey M. MIREA Russian Technol Univ Moscow Russia

Most of market-available logic analyzers are designed for hardware debug purposes and cannot record continuous measurement in long-term while in different fields of scientific research it is necessary to make data acquisition within small periods (less then 1 ms) during several hours or even days. The common example is real-time communication worst-case jitter analysis. This paper introduces an easy to implement approach how to create a logic analyzer for such kind of task on a basis of a low-cost field-programmable gate array (FPGA) kit and a personal computer. The Author provides both sample FPGA design files compatible with an open-source toolchain and the approach how to collect data using standard software and Octave scripts to post-process the experimental result. Following the Author's guidelines even with minimal knowledge in FPGA design makes it easy to modify the introduced hardware for specific laboratory team needs. (C) 2020 The Author(s). Published by Elsevier Ltd.

关键词： Logic analyzer Jitter Long-term measurements field-programmable gate array

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Fast γ Photon Imaging for Inner Surface Defects Detecting

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SENSORS 2021年第23期21卷 8134页

作者： Yao, Min Luo, Guangdong Zhao, Min Guo, Ruipeng Liu, Jian Nanjing Univ Aeronaut & Astronaut Coll Automat Engn Nanjing 210016 Peoples R China Minist Ind & Informat Technolog Key Lab Nondestruct Detect & Monitoring Technol High Spee Nanjing 210016 Peoples R China

Only a few effective methods can detect internal defects and monitor the internal state of complex structural parts. On the basis of the principle of PET (positron emission computed tomography), a new measurement method, using gamma photon to detect defects of an inner surface, is proposed. This method has the characteristics of strong penetration, anti-corrosion and anti-interference. With the aim of improving detection accuracy and imaging speed, this study also proposes image reconstruction algorithms, combining the classic FBP (filtered back projection) with MLEM (maximum likelihood expectation Maximization) algorithm. The proposed scheme can reduce the number of iterations required, when imaging, to achieve the same image quality. According to the operational demands of FPGAs (field-programmable gate array), a BPML (back projection maximum likelihood) algorithm is adapted to the structural characteristics of an FPGA, which makes it feasible to test the proposed algorithms therein. Furthermore, edge detection and defect recognition are conducted after reconstructing the inner image. The effectiveness and superiority of the algorithm are verified, and the performance of the FPGA is evaluated by the experiments.

关键词： positron emission computed tomography field-programmable gate array iteration algorithm internal defect detection image reconstruction

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Dynamic correction of the laser beam distortion by 2000 Hz FPGA-based adaptive optical system 9

Dynamic correction of the laser beam distortion by 2000 Hz F...

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Conference on Laser Communication and Propagation through the Atmosphere and Oceans IX held at SPIE Optical Engineering + Applications Conference

作者： Nikitin, A. N. Starikov, F. A. Volkov, M. V. Bogachev, V. A. Khlebnikov, A. A. Rukosuev, A. L. Inst Geosphere Dynam IDG RAS Them Academician MA Moscow Russia Inst Laser Phys ILFI RFNC VNIIEF Sarov Russia

ISBN: (数字)9781510638198

ISBN: (纸本)9781510638198;9781510638181

The results of numerical simulations and experiments on the correction of turbulent distortions of a laser beam are presented. The experiments were carried out using an adaptive optical system with a bandwidth of 2000 Hz. It was shown that for effective correction the bandwidth of the adaptive optical system should be an order of magnitude larger than the bandwidth of turbulent distortions.

关键词： high-speed adaptive optical system laser wavefront deformable mirror turbulence field-programmable gate array

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Architecture Support for FPGA Multi-tenancy in the Cloud 31

Architecture Support for FPGA Multi-tenancy in the Cloud

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31st IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Mbongue, Joel Mandebi Shuping, Alex Bhowmik, Pankaj Bobda, Christophe Univ Florida ECE Dept Gainesville FL 32611 USA

ISBN: (纸本)9781728171470

Cloud deployments now increasingly provision FPGA accelerators as part of virtual instances. While FPGAs are still essentially single-tenant, the growing demand for hardware acceleration will inevitably lead to the need for methods and architectures supporting FPGA multi-tenancy. In this paper, we propose an architecture supporting space-sharing of FPGA devices among multiple tenants in the cloud. The proposed architecture implements a network-on-chip (NoC) designed for fast data movement and low hardware footprint. Prototyping the proposed architecture on a Xilinx Virtex Ultrascale+ demonstrated near specification maximum frequency for on-chip data movement and high throughput in virtual instance access to hardware accelerators. We demonstrate similar performance compared to single-tenant deployment while increasing FPGA utilization (we achieved 6x higher FPGA utilization with our case study), which is one of the major goals of virtualization. Overall, our NoC interconnect achieved about 2x higher maximum frequency than the state-of-the-art and a bandwidth of 25.6 Gbps.

关键词： Cloud field-programmable gate array Network-on-chip Multi-tenancy Elasticity

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Dual-loop Control Scheme with Optimized Type-III Controller based on Genetic Algorithm for 6-phase Interleaved Converter in Electric Vehicle Drivetrains 22

Dual-loop Control Scheme with Optimized Type-III Controller ...

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22nd European Conference on Power Electronics and Applications (EPE ECCE Europe)

作者： Tran, Dai-Duong Chakraborty, Sajib Geury, Thomas Van Mierlo, Joeri El Baghdadi, Mohamed Hegazy, Omar Vrije Univ Brussel Pleinlaan 2 B-1050 Brussels Belgium Flanders Make B-3001 Heverlee Belgium

ISBN: (纸本)9789075815368

This paper presents an optimization procedure using a genetic algorithm (GA) for the dual-loop control scheme based on type-III controllers in a 6-phase interleaved converter. Four different objective functions (i.e. integration of squared and absolute errors and their time-weighted variants) are selected as the fitness functions of the GA. Based on the optimization procedure, step and dynamic responses of current and voltage controllers are investigated for those objective functions in terms of overshoot and settling time. In this study, another approach called classical 'k-factor' is utilized as a benchmark for the proposed type-III controller. Furthermore, two experimental tests are performed on a 60kW SiC-based prototype to verify the controller performances. The obtained results have demonstrated that the optimized controller design exhibits better dynamic response compared to the conventional counterpart.

关键词： Non-isolated interleaved DC/DC converter Optimization algorithm Small-signal average model Genetic algorithm field-programmable gate array

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