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A hardware/software architecture dedicated to model predictive control law and implemented into an FPGA platform

INTERNATIONAL JOURNAL OF AUTOMATION AND CONTROL 2019年第3期13卷 301-323页

作者： Sirine, Telmoudi Brini Badreddine, Bouzouita Faouzi, Bouani Turns El Manar Univ Natl Engn Sch Tunis ENIT LR11ES20 Lab Anal Concept & Control Syst Tunis Tunisia Univ Sousse Natl Engn Sch Sousse Sousse Tunisia

Model predictive control (MPC) is an optimisation-based strategy for high-performance control engineering practice and real-time applications. This method needs to solve online a quadratic programming (QP) problem at each sample time to find optimal control sequence. In this paper, a new optimised MPC architecture is presented, for a gradient-based QP solver to implement linear MPC on a field-programmable gate array platform, which allows obtaining high-quality performances for the real-time control applications. It requires a manual programming of the high-level C/C ++ code in opposition to the other presented approaches, which automatically generates the code. The efficiency of this approach is completed with real time control of the water level of a single tank system running on a Nanoboard 3000XN chip using a conception environment (Altium Designer), while comparing between the MPC and PID controllers.

关键词： field-programmable gate array FPGA predictive control quadratic optimisation problem PID controller Altium designer model predictive control MPC

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CNN Acceleration With Hardware-Efficient Dataflow for Super-Resolution

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IEEE ACCESS 2020年 8卷 187754-187765页

作者： Lee, Sumin Joo, Sunghwan Ahn, Hong Keun Jung, Seong-Ook Yonsei Univ Sch Elect & Elect Engn Seoul 03722 South Korea

The convolutional neural network (CNN)-based super-resolution (SR) has shown outstanding performance in the field of computer vision. The implementation of inference hardware for CNN-based SR has suffered from the intensive computation with severely unbalanced computation load among layers. Various light-weighted SR networks have been researched with little performance degradation. However, the hardware-efficient dataflow is also required to efficiently accelerate inference hardware within limited resources. In this article, we propose the hardware-efficient dataflow of CNN-based SR that reduces computation load by increasing data reuse and increases process element (PE) utilization by balancing the computation load among layers for high throughput. In the proposed dataflow, row-wise pixels in the receptive field are computed by circularly shifting memory addresses to maximize data reuse. The partial convolution is exploited in a layer-based pipeline architecture to relieve intensive computation in a single pipeline stage. The delay-balancing with adjusting parallelism is employed for balancing computations precisely in the overall layers. Furthermore, the inference hardware of CNN-based SR is implemented for 4K ultrahigh definition at 60 fps on a field-programmable gate array (FPGA). For hardware-friendly computation, the quantization of activation and weight is adopted. The proposed hardware shows an average peak signal-to-noise ratio of 36.42 dB in the Set-5 dataset with a memory usage of 53 KB and an average PE utilization of 76.7% in the overall layers. Thus, it achieves the lowest memory usage and highest PE utilization compared with other inference hardware for CNN-based SR.

关键词： Convolutional neural network dataflow field-programmable gate array inference hardware 4K ultrahigh definition process element utilization super-resolution

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FPGA Implementation of Hardware-Oriented Chaotic Boltzmann Machines

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IEEE ACCESS 2020年 8卷 204360-204377页

作者： Kawashima, Ichiro Morie, Takashi Tamukoh, Hakaru Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Kitakyushu Fukuoka 8080196 Japan

Boltzmann machines (BMs) are useful in various applications but are limited by their requirement to generate random numbers. In contrast, chaotic Boltzmann machines (CBMs) are neural networks that imitate the stochastic behavior of BMs with the chaotic dynamics and deterministic behavior, without random numbers. CBMs can potentially require fewer hardware resources than the original algorithms due to the unnecessity of random number generators. In this study, hardware-oriented algorithms and a differential multiply-accumulation operation are proposed to overcome the difficulties of implementing CBMs on field-programmable gate arrays (FPGAs). A hardware-oriented algorithm for CBMs, which includes fixed-point operations and shift operations, is proposed to reduce hardware resource utilization in the implemented circuits. In particular, the differential multiply-accumulate operation allows us to implement the multiply-accumulate operation with block random access memory and digital signal processors to reduce the consumption of lookup tables and flip-flops in FPGAs without losing the calculation speed. Our proposed approach was evaluated in numerical simulations, logical synthesis, and FPGA implementation. The calculation speed of FPGA-implemented CBMs was compared with software-implemented CBMs, which resulted in 1 / 6,500 of calculation time reduction in a 300-neuron CBM. Moreover, 2,048 neurons of CBM were realized by the logical synthesis. Therefore, the proposed hardware implementation of CBMs was shown to be feasible. The proposed CBMs can solve combinatorial optimization problems at a larger scale with fewer resources.

关键词： Chaotic Boltzmann machines combinatorial optimization problems Ising model field-programmable gate array

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Design of an Ethernet-VLC adapter based on FPGA

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JOURNAL OF COMPUTATIONAL METHODS IN SCIENCES AND ENGINEERING 2019年第3期19卷 779-787页

作者： Ye, X. Sun, G. Zhao, W. Wang, R. Nankai Univ Coll Elect Informat & Opt Engn Tianjin Peoples R China

A design of Ethernet adapter for visible light communication (VLC) is proposed in this paper. Based on field-programmable gate array (FPGA) technology and Ethernet protocols, the design applies Ethernet to VLC channel, enabling two-way transmission between both channels, giving solution to the conversion of signal between different coding formats. 8B10B DC-balanced encoding/decoding is used for VLC transceivers to ensure reliable and stable communication. At 1000BASE-T duplex mode, the maximum real-time net data rate on the VLC channel is 300Mbps by sending and receiving Ethernet frames in point-to-point communication with optical transceivers using phosphorescent white light emitting diode (WLED).

关键词： Visible light communication Ethernet field-programmable gate array white light emitting diode

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Rethinking arithmetic for deep neural networks

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PHILOSOPHICAL TRANSACTIONS OF THE ROYAL SOCIETY A-MATHEMATICAL PHYSICAL AND ENGINEERING SCIENCES 2020年第2166期378卷 20190051-20190051页

作者： Constantinides, G. A. Imperial Coll London EEE Dept London England

We consider efficiency in the implementation of deep neural networks. Hardware accelerators are gaining interest as machine learning becomes one of the drivers of high-performance computing. In these accelerators, the directed graph describing a neural network can be implemented as a directed graph describing a Boolean circuit. We make this observation precise, leading naturally to an understanding of practical neural networks as discrete functions, and show that the so-called binarized neural networks are functionally complete. In general, our results suggest that it is valuable to consider Boolean circuits as neural networks, leading to the question of which circuit topologies are promising. We argue that continuity is central to generalization in learning, explore the interaction between data coding, network topology, and node functionality for continuity and pose some open questions for future research. As a first step to bridging the gap between continuous and Boolean views of neural network accelerators, we present some recent results from our work on LUTNet, a novel field-programmable gate array inference approach. Finally, we conclude with additional possible fruitful avenues for research bridging the continuous and discrete views of neural networks. This article is part of a discussion meeting issue 'Numerical algorithms for high-performance computational science'.

关键词： neural network computing accelerator field-programmable gate array

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76-2: Scalable Real-time Holography Processor Architecture

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SID Symposium Digest of Technical Papers 2023年第1期54卷

作者： Wonok Kwon Sanghoon Cheon Joongki Park Digital Holography Research Section Electronics and Telecommunications Research Institute

In this paper, we present a fast and efficient scalable holographic video processor using a layer-based method, which employs a modified inverse Fresnel transform. To verify the performance of the proposed architecture, we design a single-layered holography core using a fixed-point model and test its performance on a field-programmable gate array. The implemented real-time hologram processor features a 1k × 1k size fast Fourier transform and a 30 frames/sec conversion rate in 4K color spatial light modulators after applying 2× linear interpolation. All real-time images on computer screens, such as YouTube and movies, are converted into holograms within 22 ms.

关键词： Hologram Real-time holography processor Computer-generated hologram field-programmable gate array

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Conventional and machine learning approaches as countermeasures against hardware trojan attacks

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MICROPROCESSORS AND MICROSYSTEMS 2020年 79卷 103295-103295页

作者： Liakos, Konstantinos G. Georgakilas, Georgios K. Moustakidis, Serafeim Sklavos, Nicolas Plessas, Fotis C. Univ Thessaly Sch Engn Dept Elect & Comp Engn CAS Lab Grp Volos Hellas Greece AIDEAS Tallinn Estonia Univ Patras Dept Comp Engn & Informat Patras Hellas Greece

Every year, the rate at which technology is applied on areas of our everyday life is increasing at a steady pace. This rapid development drives the technology companies to design and fabricate their integrated circuits (ICs) in non-trustworthy outsourcing foundries to reduce the cost, thus, leaving space for a synchronous form of virus, known as Hardware Trojan (HT), to be developed. HTs leak encrypted information, degrade device performance or lead to total destruction. To reduce the risks associated with these viruses, various approaches have been developed aiming to prevent and detect them, based on conventional or machine learning methods. Ideally, any undesired modification made to an IC should be detectable by pre-silicon verification/simulation and post-silicon testing. The infected circuit can be inserted in different stages of the manufacturing process, rendering the detection of HTs a complicated procedure. In this paper, we present a comprehensive review of research dedicated to countermeasures against HTs embedded into ICs. The literature is grouped in four main categories;(a) conventional HT detection approaches, (b) machine learning for HT countermeasures, (c) design for security and (d) runtime monitor.

关键词： Hardware security Hardware trojans Integrated circuits Application-specific integrated circuit field-programmable gate array Artificial intelligence Machine learning Detection Prevention Facilitation Design for security Runtime monitor Literature review

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AHEAD: Automatic Holistic Energy-Aware Design Methodology for MLP Neural Network Hardware Generation in Proactive BMI Edge Devices

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ENERGIES 2020年第9期13卷 2180-2180页

作者： Huang, Nan-Sheng Chen, Yi-Chung Larsen, Jorgen Christian Manoonpong, Poramate Univ Southern Denmark Maersk Mc Kinney Moller Inst Embodied AI & Neurorobot Lab SDU Biorobot DK-5230 Odense Denmark Tennessee State Univ Dept Elect & Comp Engn Nashville TN 37209 USA

The prediction of a high-level cognitive function based on a proactive brain-machine interface (BMI) control edge device is an emerging technology for improving the quality of life for disabled people. However, maintaining the stability of multiunit neural recordings is made difficult by the nonstationary nature of neurons and can affect the overall performance of proactive BMI control. Thus, it requires regular recalibration to retrain a neural network decoder for proactive control. However, retraining may lead to changes in the network parameters, such as the network topology. In terms of the hardware implementation of the neural decoder for real-time and low-power processing, it takes time to modify or redesign the hardware accelerator. Consequently, handling the engineering change of the low-power hardware design requires substantial human resources and time. To address this design challenge, this work proposes AHEAD: an automatic holistic energy-aware design methodology for multilayer perceptron (MLP) neural network hardware generation in proactive BMI edge devices. By taking a holistic analysis of the proactive BMI design flow, the approach makes judicious use of the intelligent bit-width identification (BWID) and configurable hardware generation, which autonomously integrate to generate the low-power hardware decoder. The proposed AHEAD methodology begins with the trained MLP parameters and golden datasets and produces an efficient hardware design in terms of performance, power, and area (PPA) with the least loss of accuracy. The results show that the proposed methodology is up to a 4X faster in performance, 3X lower in terms of power consumption, and achieves a 5X reduction in area resources, with exact accuracy, compared to floating-point and half-floating-point design on a field-programmable gate array (FPGA), which makes it a promising design methodology for proactive BMI edge devices.

关键词： neural network edge device field-programmable gate array hardware acceleration high-level synthesis energy-aware design brain-machine interface

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Physical education image analysis based on virtual crowd simulation and FPGA

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MICROPROCESSORS AND MICROSYSTEMS 2020年 79卷 103319-103319页

作者： Leilei, Wang Huina, Cheng Huaihua Univ Inst Phys Educ & Hlth Huanhua 418000 Hunan Peoples R China HeBei Inst Commun Shijiazhuang 050071 Hebei Peoples R China

Physical Culture and Sports research are coordinated with the game (rational, educators, game director, and game theory from a specific or a general point) medicine sociology. They revolve around representatives, value theory, and modern games near parts. This journal is dedicated to humanists, social researchers, students, and practitioners, social analysts, research institutions, and professionals. To practice city models, company directors need to incorporate a large number of personnel for the legs, automobiles, and other powerful elements. Analysts use the same design of registration, i.e. more than 100 million long-distance race. To reproduce and become a member, they continue to be referring many inferences using the fluffy ground on the Graphical Process Unit (GPU). This is an element of PC Vision that is often used to extract the perspective of one of the computing where the histogram is used. Using this calculation requires a large amount of isolated bright spots in the image calculation. One approach, Adaptive speed from the games, for example to support calculations, a field- programmable gatearray (FPGA) is equal to the front door. First, an overview of the position and inclination calculation apparatus histogram is given. To implement the full classification, it only uses the equations of decision boundaries. This is to simplify the FPGA implementation through simple expressions, rather than the whole classification. At this point, will see how field-programmable front position has been used in the last decade, i.e. the slope of the histogram. The remainder of the beam is information including resolution, a large number of the task of the receptacle and the direction, progress, and standardized way of calculation. The third cluster is a first program which is a common computing device program, including the position angle dependence modemed histogram and highlights its execution apparatus implemented. The goal uses different pixel per clock cycle analy

关键词： Histogram of oriented gradients field-programmable gate array Hardware acceleration Hardware design

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Development and Application of Ion Current/Cylinder Pressure Cooperative Combustion Diagnosis and Control System

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ENERGIES 2020年第21期13卷 5656页

作者： Zhu, Denghao Deng, Jun Wang, Jinqiu Wang, Shuo Zhang, Hongyu Andert, Jakob Li, Liguang Tongji Univ Sch Automot Studies Shanghai 201804 Peoples R China Tongji Univ Chines Deutsch Hochschulkolleg Shanghai 201804 Peoples R China Rhein Westfal TH Aachen Mechatron Syst Combust Engines D-52074 Aachen Germany

The application of advanced technologies for engine efficiency improvement and emissions reduction also increase the occurrence possibility of abnormal combustions such as incomplete combustion, misfire, knock or pre-ignition. Novel promising combustion modes, which are basically dominated by chemical reaction kinetics show a major difficulty in combustion control. The challenge in precise combustion control is hard to overcome by the traditional engine map-based control method because it cannot monitor the combustion state of each cycle, hence, real-time cycle-resolved in-cylinder combustion diagnosis and control are required. In the past, cylinder pressure and ion current sensors, as the two most commonly used sensors for in-cylinder combustion diagnosis and control, have enjoyed a seemingly competitive relationship, so all related researches only use one of the sensors. However, these two sensors have their own unique features. In this study, the idea is to combine the information obtained from both sensors. At first, two kinds of ion current detection system are comprehensively introduced and compared at the hardware level and signal level. The most promising variant (the DC-Power ion current detection system) is selected for the subsequent experiments. Then, the concept of ion current/cylinder pressure cooperative combustion diagnosis and control system is illustrated and implemented on the engine prototyping control unit. One application case of employing this system for homogenous charge compression ignition abnormal combustion control and its stability improvement is introduced. The results show that a combination of ion current and cylinder pressure signals can provide richer and also necessary information for combustion control. Finally, ion current and cylinder pressure signals are employed as inputs of artificial neural network (ANN) models for combustion prediction. The results show that the combustion prediction performance is better when the inputs ar

关键词： Ion current cylinder pressure cooperative combustion diagnosis and control field-programmable gate array artificial neural network

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