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Flexible tunable optical transceiver based on field-programmable gate array for time and wavelength-division multiplexed passive optical network systems

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OPTICAL ENGINEERING 2016年第8期55卷 086110-1-086110-7页

作者： Hu, Sheng Yu, Yonglin Li, Cheng Zhu, Yao Han, Yu Huazhong Univ Sci & Technol Wuhan Natl Lab Optoelect Sch Opt & Elect Informat Luoyu Rd 1037 Wuhan 430074 Peoples R China Wuhan Huagong Genuine Opt Tech Co Ltd HG Genuine HUST Sci & Tech Pk Wuhan 430073 Peoples R China

Time-and wavelength-division multiplexed passive optical networks (TWDM-PONs) have been selected by the full services access network community as the most suitable technology for next-generation optical access networks. A key technology in TWDM-PON is the colorless optical network unit transceiver. This paper proposes a flexible, tunable optical transceiver that uses directly modulated tunable lasers. Using a field-programmable gate array (FPGA), programmable reconfigurations and testing capabilities can be embedded into the transceiver in order to implement wavelength control, signal generation, pre-emphasis for upstream, and a bit error rate (BER) test for the downstream. To ensure high-quality signal generation at different bitrates, impedance matching between the laser driver circuit and the laser diodes is optimized. Using the proposed transceiver, three-section-distributed Bragg reflector tunable lasers at or below 2.5 Gb/s direct modulation through a 40-km standard mode fiber transmission were successfully implemented. (C) 2016 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： tunable transceiver colorless optical network unit field-programmable gate array time-and wavelength-division multiplexed passive optical network

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Real-time power monitoring using field-programmable gate array with IoT technology

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IET SCIENCE MEASUREMENT & TECHNOLOGY 2019年第6期13卷 931-935页

作者： Lee, Kok Tong Mun, Hou Kit Southern Univ Coll Fac Engn & Informat Technol Skudai 81300 Johor Malaysia Taylors Univ Sch Engn 1 Jalan Taylors Subang Jaya 47500 Selangor Malaysia

Automation technologies are often impacted undesirably by downtime caused by machine failures. An approach to overcome machine failures is through failures prediction, achievable via the monitoring of power consumption. Unusual power consumption could serve as an alert for possible machines faults. Real-time power consumption monitoring is made possible with the deployment of Internet of Things (IoT), which brings together digital cloud computing and conventional automation technology to rapidly increase the efficiency of production. In this work, the authors have developed an IoT-based power monitoring system to detect unusual power consumption of machines and present the data to users remotely through Android application and cloud storage. The competent integration of Wi-Fi module ESP8266, CT sensor module and field-programmable gate array DE1-SoC board allows the system to accurately measure power consumption and instantaneously store the data in cloud storage. Performance of the developed system was characterised by current measurement of five different loads. The absolute errors, given by the difference between current measured by digital multimeter and the developed system, range from 0.01 to 0.26A. The close agreement between the two measurements endorses the accuracy and reliability of the real-time power monitoring system, on top of its easy-accessibility gifted by IoT.

关键词： system-on-chip wireless LAN power system measurement cloud computing field programmable gate arrays Internet of Things electric current measurement power consumption power engineering computing smart phones power system reliability field-programmable gate array cloud storage real-time power monitoring system IoT technology automation technologies machine failures failures prediction unusual power consumption possible machines faults real-time power consumption monitoring conventional automation technology IoT-based power monitoring system Internet of Things digital cloud computing Android application Wi-Fi module ESP8266 CT sensor module DE1-SoC board current measurement digital multimeter

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Delay performance due to thermal variation on field-programmable gate array via the adoption of a stable ring oscillator

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IET COMPUTERS AND DIGITAL TECHNIQUES 2019年第5期13卷 405-413页

作者： Jaafar, Anuar Soin, Norhayati Hatta, Sharifah Wan Muhamad Irwan, Salim Sani Univ Teknikal Malaysia Melaka UTeM FKEKK Ctr Telecommun Res & Innovat CeTRI Durian Tunggal 76100 Melaka Malaysia Univ Malaya Fac Engn Dept Elect Engn Kuala Lumpur 50603 Malaysia Univ Malaya Ctr Printable Elect Kuala Lumpur 50603 Malaysia

Thermal issues are rapidly evolving in the field-programmable gate arrays (FPGAs) and are being intensely studied as these issues appear to significantly affect the delay performance of FGPAs. A ring oscillator has been widely used as a digital temperature sensor to sense this thermal effect on FPGAs. The delay generated by the ring oscillator will vary depending on the temperature environment due to negative bias temperature instability, hot carrier injection and electromigration. It is therefore critical to adopt an accurate ring oscillator design to effectively measure the delay in FGPAs. In this study, a digital temperature sensor with a stable ring oscillator is proposed. Measurement periods of 512 and 4096 clock cycles have been implemented and the relationship between temperature, delay and total count has been established. The results show that as the temperature increases to 100 degrees C, the delay decreases by 3.99 and 33.98% for 512 and 4096 clock cycles, respectively. It has been found that in order to reduce the degradation effect on the Virtex-6 FPGA, adopting a measurement period of 512 clock cycles is the best method. The measured data is successfully validated through a set of simulations. Thus, it may benefit a system designer and industrial player, especially in designing temperature-based FPGAs.

关键词： field programmable gate arrays electromigration oscillators temperature sensors hot carriers clocks thermal variation field-programmable gate array stable ring oscillator thermal issues FGPAs digital temperature sensor thermal effect temperature environment negative bias temperature instability hot carrier injection electromigration accurate ring oscillator design measurement period degradation effect temperature-based FPGAs clock cycles

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Permanent magnet synchronous machines flux linkage estimation with zero steady-state error and its field-programmable gate array implementation

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IET ELECTRIC POWER APPLICATIONS 2015年第4期9卷 332-343页

作者： Zanuso, Giovanni Peretti, Luca Zigliotto, Mauro ABB Corp Res Dept Elect Syst S-72178 Vasteras Sweden Univ Padua Dept Tech & Management Ind Syst I-36100 Vicenza Italy

The paper analyses a combined current model-voltage model estimator for flux linkages in permanent magnet synchronous machines, with the capability of converging to exact flux estimation even in presence of mismatches because of magnetic saturation. As a trend in next-generation electric drives, the whole algorithm, including both the flux estimator and the standard field-oriented control, has been implemented in a field-programmable gate array (FPGA) chip. Simulations and experimental tests, along with some figures for the FPGA selection, have been included in the study.

关键词： permanent magnet machines synchronous machines field programmable gate arrays electric drives digital control machine vector control permanent magnet synchronous machines flux linkage estimation zero steady-state error field-programmable gate array combined current model-voltage model estimator magnetic saturation next-generation electric drives standard field-oriented control FPGA chip

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Monitoring field-programmable gate array-based processing engines of dependable computer systems

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IET COMPUTERS AND DIGITAL TECHNIQUES 2007年第6期1卷 661-668页

作者： Bartzoudis, N. Hopkins, A. B. T. McDonald-Maier, K. D. Univ Essex Dept Comp & Elect Syst Colchester CO4 3SQ Essex England

The integration of field-programmable gate array (FPGA) devices as co-processing elements in numerous dependable computer systems makes the real-time detection of errors a vital issue. The propagation of FPGA-based application errors can endanger the availability of the hosting computer. Embedded error detection mechanisms should enforce the operation of the FPGA-based systems, in order to prevent system failures. Such monitoring should not interfere with the host PC performance and must also ensure the timely detection of failures. Therefore an embedded error detection and recovery component was designed and implemented, which does not require manual intervention, in order to illustrate the benefits of this approach. A double FPGA board-layout was used to provide the forensic analysis of the dependable workstation's PCI bus activity. The monitor logic specifically targets PCI buses;it is tightly coupled with the PCI core located in a first FPGA device to check the protocol and application errors in PCI activity. Application circuits are configured in the second FPGA.

关键词： monitoring embedded error detection FPGA-based co-processing engine coprocessors peripheral interfaces system failure double FPGA board-layout forensic analysis dependable workstation PCI bus activity real-time error detection field programmable gate arrays dependable computer system field-programmable gate array

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Composition of magnetic tunnel junction-based magnetoresistive random access memory for field-programmable gate array

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CURRENT SCIENCE 2020年第1期119卷 119-123页

作者： Hamsa, S. Thangadurai, N. Ananth, A. G. Jain Deemed To Be Univ Elect & Commun Engn Dept Bengaluru 560112 India NMAMIT Elect & Commun Engn Dept Nitte 574110 Udupi India

In this study, the schematics for Magnetic Tunnel Junction-Magnetoresistive Random Access Memory (MTJ-MRAM) are designed and simulations are carried out in 45 and 90 nm Complementary Metal-Oxide Semiconductor (CMOS) Very Large Scale Integration (VLSI) technology using analog design environment. Other memory circuits like volatile Static Random Access Memory (SRAM) and non-volatile flash memory are designed and behavioural waveforms verified. The output behavioural characteristics of MTJ-MRAM are compared with that of SRAM and flash memory. The attributes like power and delay are calculated and compared with SRAM and flash memory circuits. The study was carried out in order to integrate the non-volatile memory with field-programmable gate array (FPGA) architecture and design a nonvolatile memory-based FPGA. MTJ-MRAM shows better performance than volatile SRAM and non-volatile flash memory in terms of power and delay parameters.

关键词： Behavioural waveforms field-programmable gate array magnetic tunnel junction memory circuits

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Digital model of TiO2 memristor for field-programmable gate array

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JOURNAL OF ENGINEERING-JOE 2014年第3期2014卷 90-92页

作者： Wang, Guangyi Bai, Dandan Wang, Xiaoyuan Hangzhou Dianzi Univ Sch Elect Informat Hangzhou 310037 Zhejiang Peoples R China

A digital model which imitates the behaviour of a TiO2 memristor as a new block in Alter DSP Builder is proposed in this Letter. The proposed model can be used as an independent memristor unit working with other units for designing memristor circuits based on field-programmable gate array. The accuracy of the digital model is confirmed not only by simulations, but also by hardwire experiments.

关键词： field programmable gate arrays digital signal processing chips titanium compounds memristors integrated circuit design digital model field-programmable gate array FPGA Alter DSP builder memristor circuits design TiO2

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Tuning of Channel Conductance of Au Nanowires Using Ultrafast Electromigration Controlled by a field-programmable gate array 5

Tuning of Channel Conductance of Au Nanowires Using Ultrafas...

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International Conference on Manipulation, Manufacturing and Measurement on the Nanoscale

作者： Katogi, Yu Kanamaru, Yuma Sato, Shusuke Saito, Takanari Shirakashi, Jun-ichi Tokyo Univ Agr & Technol Dept Elect & Elect Engn Koganei Tokyo 1848588 Japan

ISBN: (纸本)9781467396257

Feedback-controlled electromigration ( FCE) has been employed to control metal nanowires with quantized conductance and to create nanogaps. However, the formation of nanostructures by conventional FCE procedure using a microprocessor-based controller with a general purpose operating system ( GPOS) is considerably slow process. Therefore, we proposed an ultrafast FCE method using a field-programmable gate array ( FPGA) to immediately and precisely control the channel conductance of Au nanowires. In this report, we study the tuning of quantized conductance of Au nanowires by ultrafast FCE using FPGA-based control system with a constant-voltage ( CV) method. First, in the FCE procedure, preset values of quantized conductance of Au nanowires were defined as 25 G(0), 15 G(0), and 5 G(0) ( G(0) = 2e(2)/h). The conductance of the Au nanowires during FCE procedure decreased until the conductance reached the preset values within an order of a millisecond. Furthermore, the quantized conductance plateaus of the Au nanowires were precisely controlled by the CV procedure with the preset values of 15 G(0) and 5 G(0). These results imply that the combination of FCE and CV procedures with FPGA-based control system can precisely and stably tune the channel conductance of Au nanowires with millisecond-scale resolution.

关键词： electromigration field-programmable gate array feedback-controlled electromigration quantized conductance nanowire nanogap

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A field-programmable gate array Implementation of a Cognitive Radar Target Recognition System

A Field-Programmable Gate Array Implementation of a Cognitiv...

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IEEE Radar Conference (RadarConf)

作者： Sessions, Calvin A. Romero, Ric A. Fouts, Douglas J. Naval Postgrad Sch Elect & Comp Engn Monterey CA 93943 USA

ISBN: (纸本)9781728153681

In this paper, we design a field-programmable gate array (FPGA) implementation of a cognitive radar (CRr) target recognition system for electronic warfare applications. This study expands on the closed-loop adaptive matched waveform transmission technique called probability of weighted energy (PWE). This work also investigates the feasibility of applying the PWE technique in a functional digital hardware realization. Initially, a PWE Monte Carlo simulation model is developed in the Verilog hardware description language that is simulated in the Xilinx Vivado environment. The Verilog module components developed in the Monte Carlo model are then incorporated into a CRr target recognition system experiment utilizing the Xilinx VCU118 Evaluation Board. The VCU118 features the Virtex UltraScale+ high-performance FPGA to accomplish CRr adaptive waveform generation and transmission, digital signal processing requirements, and target classification. The Rohde & Schwarz SMW200A Vector Signal Generator and FSW Signal & Spectrum Analyzer function as the radar system transmitter and receiver, respectively, while the FPGA implementation enables the closed feedback loop used by the CRr.

关键词： cognitive radar probability of weighted energy field-programmable gate array target classification eigenwave-form CRr PWE FPGA

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Feasibility Analysis of Baseband Board Based on field programmable gate array 19

Feasibility Analysis of Baseband Board Based on Field Progra...

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5th International Conference on Computer and Technology Applications (ICCTA)

作者： Wang, Meile Zhang, Zhizhong Wang, Guangya Chongqing Univ Posts & Telecommun 2 Chongwen Rd Chongqing Peoples R China

ISBN: (纸本)9781450371810

The design of the baseband board for many types of instrumentation developed is limited to verify its feasibility by implementation. On this basis we propose a detailed feasibility analysis method before the design of the baseband board to prevent the waste of the manpower and time resources because of the shortage of chip resources, which provided a reference for the design of the baseband board. Firstly we determine the model of core processor based on LTE-A characteristics and baseband board requirements;then we focus on the storage capacity and bus capacity of the baseband board to ensure that the selected components have sufficient capacity and margin;fmally we prove the correctness of the feasibility analysis through the test on the baseband board, and it also provides the reference for other hardware chip selection.

关键词： field-programmable gate array feasibility LTE-A baseband board

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