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Wireless energy-harvesting circuit and system with error-correction ASK demodulator for body sensor network with ultra-high-frequency RFID healthcare system

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IET WIRELESS SENSOR SYSTEMS 2018年第1期8卷 36-44页

作者： Lee, Shuenn-Yuh Chen, Tsung-Yen Tsou, Chieh Chu, Yuan-Sun Natl Cheng Kung Univ Dept Elect Engn 1 Univ Rd Tainan Taiwan Natl Chung Cheng Univ Dept Elect Engn 168 Univ Rd Min Hsiung Chia Yi Taiwan

This study presents a low-power energy-harvesting circuit with error-correction demodulation for body sensor networks with radio-frequency identification (RFID) systems. The proposed circuit adopts a new structure that facilitates the demodulation of amplitude-shift-keying (ASK) signals, and it includes a power unit consisting of a wake-up circuit and a power-on-reset control circuit. The wireless bio-signal acquisition system and the digital processor are implemented on a field-programmable gate array to demonstrate the proposed RFID tag. The proposed energy-harvesting circuit can substantially decrease the capacitance used by the demodulator circuit and the wake-up circuit to as low as 14 pF. Moreover, a detection circuit and a correcting circuit are utilised to reduce the bit error rate of decoding. The wireless bio-signal acquisition scenario is also set up and the communication signal between reader and tag is measured to demonstrate the system that can be employed in body sensor network with the healthcare system. The chip was implemented in complementary metal-oxide-semiconductor 0.18 mu m technology. The sensitivity of this work is - 13 dBm. The pulse width error can be reduced to <1% by the error-correction demodulator to fit the EPC Gen-2 standard.

关键词： radiofrequency identification biomedical electronics energy harvesting error correction codes amplitude shift keying demodulators body sensor networks health care low-power electronics detector circuits CMOS integrated circuits field programmable gate arrays wireless energy-harvesting circuit wireless energy-harvesting system error-correction ASK demodulator body sensor network ultra-high-frequency RFID healthcare system radio-frequency identification system amplitude-shift-keying signal demodulation power unit wake-up circuit power-on-reset control circuit low-power energy-harvesting circuit wireless bio-signal acquisition system digital processor field-programmable gate array RFID tag detection circuit correcting circuit bit error rate decoding communication signal complementary metal-oxide-semiconductor technology pulse width error EPC Gen-2 standard size 0 18 mum

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Hardware-Accelerated Index Construction for Semantic Web 17

Hardware-Accelerated Index Construction for Semantic Web

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17th International Conference on field-programmable Technology (FPT)

作者： Blochwitz, Christopher Wolff, Julian Berekovic, Mladen Heinrich, Dennis Groppe, Sven Joseph, Jan Moritz Pionteck, Thilo Univ Lubeck Inst Comp Engn D-23562 Lubeck Germany Univ Lubeck Inst Informat Syst D-23562 Lubeck Germany Otto von Guericke Univ Inst Informat Technol & Commun D-39106 Magdeburg Germany

ISBN: (纸本)9781728102139

In this paper, an optimized data structure for managing triples used in a Semantic Web Database and a hardware engine for index construction are presented. We propose an FPGA-centric design, which we call Hardware-Triplestore. As part of the design, a scalable and parallel architecture for Triplestore construction is introduced. We propose a hybrid data structure consisting of three layers, one for every element of the semantic triple. The data structure is optimized for our hardware-centric design and is stored on an external DDR4-Memory. The Hardware-Triplestore is evaluated separately from the rest of the database system and achieves an insertion rate of 1.24 million triples per second, which is 17 times faster than one of the fastest software Triplestore-RDF-3X-.

关键词： Triplestore RDF-3X Semantic Web Database Hardware field-programmable gate array

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Hardware Architectures for Computing 8-Point Cosine Number Transform

Hardware Architectures for Computing 8-Point Cosine Number T...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： de Oliveira Neto, Jose R. Lima, Juliano B. Univ Fed Pernambuco Dept Elect & Syst Recife PE Brazil

ISBN: (纸本)9781538648810

The cosine number transform (CNT) is a cosine-like number-theoretic transform, which has been employed as the basis for multimedia security schemes. In this paper, we propose hardware architectures for computing an 8-point CNT. The architectures include a pipelined approach and are based on a recently introduced fast algorithm, which has been demonstrated to be more efficient than the direct computation of the CNT. We quantify such an efficiency by considering several aspects inherent to modular arithmetic and comparing metrics obtained from field-programmable gate array (FPGA) implementations of the proposed architectures.

关键词： Number-theoretic transforms cosine number transform hardware architectures pipeline field-programmable gate array

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Design of a Multichannel Time Interval Measurement Interface Box

Design of a Multichannel Time Interval Measurement Interface...

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作者： Don, M. L Pugh, K. E Kline, B. J Hallameyer, J. M CCDC Army Research Laboratory Aberdeen Proving Ground United States

Precise time interval measurement is required for a number of applications including clock stability analysis, time-of-flight measurements, and particle physics. Commercial time interval measurement devices can achieve picosecond resolution but are expensive, especially for multichannel applications. In previous research, the US Army Combat Capabilities Development Command Army Research Laboratory demonstrated 10-ns resolution on 10 channels using a low-cost field-programmable gate array (FPGA) suitable for pulse-per-second monitoring. This technical note details the design of an interface box for this FPGA device, enabling practical time interval measurement with a variety of input signals. The purpose of this note is twofold: 1) to document the interface box to allow for easy use and future modifications and 2) to provide a reference to facilitate the construction of other interface units, including design advice and lessons learned.

关键词： field programmable gate array Time intervals Measurement Monitoring Time interval measurement field-programmable gate array Pulse per second Test and measurement Electronic interface

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Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity 19

Embracing Systolic: Super Systolization of Large-Scale Circu...

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Proceedings of the 2019 ACM/SIGDA International Symposium on field-programmable gate arrays

作者： Jiafeng Xie Chiou-Yng Lee Villanova University Villanova PA USA Lunghwa University of Science and Technology Taoyuan Taiwan Roc

ISBN: (纸本)9781450361378

The recent advance in artificial intelligence (AI) technology has led to a new round of systolic structure innovation. Many AI accelerators have employed systolic structure to realize the core large-scale matrix-vector multiplication for high-performance processing, which has a complexity of $o(n^2)$ for matrix size of $n\times n$ (difficult to be implemented on the field-programmable gate array (FPGA) platform). To overcome this drawback, in this paper, we propose a super systolization strategy to implement the core circulant matrix-vector multiplication into a systolic structure with subquadratic space complexity. The proposed effort is carried out through two stages of coherent interdependent efforts: (i) a novel matrix-vector multiplication algorithm based on Toeplitz matrix-vector product (TMVP) approach is proposed to obtain subquadratic space complexity; (ii) a series of optimization techniques are introduced to map the proposed algorithm into desired systolic structure. Finally, detailed complexity analysis and comparison have been conducted to prove the efficiency of the proposed strategy. The proposed strategy is highly efficient and can be extended in many neural network based hardware implementation platforms.

关键词： field-programmable gate array systolic structure large-scale toeplitz matrix vector product circulant matrix-vector multiplication subquadratic space complexity

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Challenges in Large FPGA-based Logic Emulation Systems 18

Challenges in Large FPGA-based Logic Emulation Systems

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ACM International Symposium on Physical Design (ISPD)

作者： Hung, William N. N. Sun, Richard Synopsys Mountain View CA 94043 USA

ISBN: (纸本)9781450356268

Functional verification is an important aspect of electronic design automation. Traditionally, simulation at the register transfer-level has been the mainstream functional verification approach. Formal verification and various static analysis checkers have been used to complement specific corners of logic simulation. However, as the size of IC designs grow exponentially, all the above approaches fail to scale with the design growth. In recent years, logic emulation have gained popularity in functional verification, partly due to their performance and scalability benefits. There are two main approaches to logic emulation: ASIC and commercial field-programmable gate array (FPGA). In this paper, we focus on commercial FPGA based logic emulation and present various challenging problems in this area for the academic community.

关键词： Logic emulation field-programmable gate array

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FPGA Implementation Scheme of Mixed Logarithmic domain FFT-BP Decoding Algorithm Based on Non-binary LDPC codes 37

FPGA Implementation Scheme of Mixed Logarithmic domain FFT-B...

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37th Chinese Control Conference (CCC)

作者： Wang, Ziyong Meng, Jiahui Deng, Zhibin Zhang, Liang Gao, Jingpeng Wuhan Maritime Commun Res Inst Wuhan 430000 Hubei Peoples R China Harbin Engn Univ Coll Informat & Commun Engn Harbin 150001 Heilongjiang Peoples R China

ISBN: (纸本)9789881563958

In this paper, an improved decoding algorithm for Non-binary low density parity check (NB-LDPC) codes with low decoding complexity and suitable for field-programmable gate array (FPGA) implementation is proposed, which is a mixed logarithmic domain FFT-BP decoding algorithm (Mixed Log-FFT-BP) for the problem of high complexity of the existing decoding algorithms for Non-binary LDPC codes. The algorithm combines the traditional Log-BP algorithm with the FFT-BP algorithm, and simplifies the update of the check nodes in the iterative decoding process. A large number of convolution operations are converted into multiplication operations in frequency domain by using FFT transform and IFFT transform. The multiplication of the original FFT-BP algorithm is converted into the addition and look-up table operations in the logarithmic domain. Then, the logarithm of the probability information is directly solved, so that it can be decoded in the logarithmic domain, which saves the computation of the log likelihood ratio, and then reduces the complexity. Simulation results show that under the additive Gauss white noise channel, when the bit error rate is 10(-5), compared with BP algorithm, Log-BP algorithm and FFT-BP algorithm, the performance of Mixed Log-FFT-BP algorithm is not decreased, and all of them remain within the range of 0.1-0.2dB.

关键词： Non-binary low density parity check codes Mixed Log-FFT-BP decoding field-programmable gate array Complexity

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LDPC Codes Derived from Quasi-cyclic Code Design Suitable for Optical Communications 20

LDPC Codes Derived from Quasi-cyclic Code Design Suitable fo...

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20th International Conference on Transparent Optical Networks (ICTON)

作者： Sun, Xiaole Djordjevic, Ivan B. Univ Arizona Dept Elect & Comp Engn 1230 E Speedway Blvd Tucson AZ 85721 USA

ISBN: (纸本)9781538666050

We propose a rate-adaptive forward error correction (FEC) scheme based on spatially-coupled (SC) LDPC codes derived from quasi-cyclic (QC) LDPC codes with its field-programmable gate array (FPGA) architecture. By FPGA emulation, we show that, with comparable computational complexity, the proposed LDPC codes provide larger coding gain and smaller error floor compare to the QC-LDPC base code. As a result, due to its hardware friendly structure, they are presented to be a promising candidate for the next-generation intelligent optical communication systems such as long-haul optical transmission system.

关键词： forward error correction LDPC field-programmable gate array spatially coupling LDPC

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field-programmable gate array-based intelligent dynamic sliding-mode control using recurrent wavelet neural network for linear ultrasonic motor

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IET CONTROL THEORY AND APPLICATIONS 2010年第9期4卷 1511-1532页

作者： Lin, F. -J. Hung, Y. -C. Chen, S. -Y. Natl Cent Univ Dept Elect Engn Chungli 320 Taiwan

A field-programmable gate array (FPGA)-based intelligent dynamic sliding-mode control (IDSMC) using recurrent wavelet neural network (RWNN) estimator is proposed to control the mover position of a linear ultrasonic motor (LUSM) in this study. First, the structure and operating principles of the LUSM are introduced briefly. Then, the dynamics of LUSM mechanism with the introduction of a lumped uncertainty, which include the friction force, is derived. Since the dynamic characteristics and motor parameters of the LUSM are non-linear and time-varying, an IDSMC using RWNN estimator is designed to achieve robust control performance of the LUSM drive system. The RWNN estimator is employed to estimate the non-linear functions including the system parameters and external disturbance. Moreover, the adaptive learning algorithm trained the parameters of the RWNN online is derived using the Lyapunov stability theorem. Furthermore, an FPGA chip is adopted to implement the developed control and on-line learning algorithms for possible low-cost and high-performance industrial applications. The experimental results show that excellent positioning and tracking performance are achieved. In addition, the robustness to parameter variations and friction force can be obtained as well using the proposed control system.

关键词： linear motors friction force adaptive control Control of electric power systems intelligent dynamic sliding-mode control lumped uncertainty recurrent neural nets Multivariable control systems ultrasonic motors neurocontrollers Logic and switching circuits variable structure systems Stability in control theory control system synthesis Linear machines Control system analysis and synthesis methods control engineering electric machine analysis computing Logic circuits recurrent wavelet neural network robust control field programmable gate arrays Self-adjusting control systems Lyapunov methods Control engineering computing machine control Neurocontrol uncertain systems Piezoelectric motors field-programmable gate array adaptive learning algorithm Power engineering computing linear ultrasonic motor Lyapunov stability theorem

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field-programmable gate array-based functional link radial basis function network control for permanent magnet linear synchronous motor servo drive system

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IET ELECTRIC POWER APPLICATIONS 2010年第5期4卷 357-372页

作者： Lin, F. -J. Chou, P. -H. Hung, Y. -C. Wang, W. -M. Natl Cent Univ Dept Elect Engn Chungli 320 Taiwan Natl Dong Hwa Univ Dept Elect Engn Hualien 974 Taiwan

A field-programmable gate array (FPGA)-based functional link radial basis function network (FLRBFN) control is proposed in this study to control the mover of a permanent magnet linear synchronous motor (PMLSM) servo drive system to track periodic reference trajectories. First, the dynamics of the field-oriented control PMLSM servo drive with a lumped uncertainty, which contains parameter variations, external disturbances and non-linear friction force, is derived. Then, to achieve accurate trajectory tracking performance with robustness, an intelligent control approach using FLRBFN is proposed for the field-oriented control PMLSM servo drive system. The proposed FLRBFN is a radial basis function network (RBFN) embedded with a functional link neural network (FLNN). Moreover, the on-line learning algorithm of the FLRBFN, including the connective weights, the centres and the centres' width of the receptive field functions, are derived using back-propagation (BP) method. Furthermore, an FPGA chip is adopted to implement the developed control and on-line learning algorithms for possible low-cost and high-performance industrial applications using PMLSM. Finally, the effectiveness of the proposed control scheme and the robustness to parameter variations, external disturbances and friction force of the PMLSM servo drive system are verified by some experimental results.

关键词： field-oriented control linear motors machine vector control Control of electric power systems backpropagation method lumped uncertainty FPGA neurocontrollers permanent magnet linear synchronous motor servo drive system synchronous motor drives Linear machines Actuating and final control devices trajectory tracking performance RBFN functional link radial basis function network control field programmable gate arrays servomechanisms permanent magnet motors Synchronous machines Neurocontrol field-programmable gate array backpropagation radial basis function networks nonlinear friction force intelligent control approach Drives

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