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IEEE MICRO 2017年第2期37卷 40-51页

作者： Sadasivam, Satish Kumar Thompto, Brian W. Kalla, Ron Starke, William J. IBM Corp Armonk NY 10504 USA IBM Corp Power Syst Processor Team Armonk NY 10504 USA IBM Corp Power9 Armonk NY 10504 USA

THE IBM POWER9 PROCESSOR HAS AN ENHANCED CORE AND CHIP ARCHITECTURE OPTIMIZED FOR EMERGING WORKLOADS WITH SUPERIOR THREAD PERFORMANCE AND HIGHER THROUGHPUT TO SUPPORT NEXT-GENERATION COMPUTING. MULTIPLE VARIANTS OF SILICON TARGET THE SCALE-OUT AND SCALE-UP MARKETS. WITH A NEW CORE MICROARCHITECTURE DESIGN, ALONG WITH AN INNOVATIVE I/O FABRIC TO SUPPORT ACCELERATED COMPUTING REQUIREMENTS, THE POWER9 PROCESSOR MEETS THE DIVERSE COMPUTING NEEDS OF THE COGNITIVE ERA AND PROVIDES A PLATFORM FOR ACCELERATED COMPUTING.

关键词： accelerator cache CAPI Computer architecture field programmable gate arrays field-programmable gate array FPGA GPU Graphics processing units I/O Instruction sets interconnects memory microarchitecture multicore Multicore processing Multiprocessing systems POWER9 processor simultaneous multithreading SMP SMT Switched mode power supplies symmetric multiprocessor

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Subnanosecond time-to-digital converter implemented in a Kintex-7 FPGA

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NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT 2017年 874卷 50-56页

作者： Sano, Y. Horii, Y. Ikeno, M. Sasaki, O. Tomoto, M. Uchida, T. Nagoya Univ Chikusa Ku Nagoya Aichi 4648602 Japan High Energy Accelerator Res Org KEK Tsukuba Ibaraki 3050801 Japan

Time-to-digital converters (TDCs) are used in various fields, including high-energy physics. One advantage of implementing TDCs in field-programmable gate arrays (FPGAs) is the flexibility on the modification of the logics, which is useful to cope with the changes in the experimental conditions. Recent FPGAs make it possible to implement TDCs with a time resolution less than 10 ps. On the other hand, various drift chambers require a time resolution of O(0.1) ns, and a simple and easy-to-implement TDC is useful for a robust operation. Herein an eight-channel TDC with a variable bin size down to 0.28 ns is implemented in a Xilinx Kintex-7 FPGA and tested. The TDC is based on a multisampling scheme with quad phase clocks synchronised with an external reference clock. Calibration of the bin size is unnecessary if a stable reference clock is available, which is common in high-energy physics experiments. Depending on the channel, the standard deviation of the differential nonlinearity for a 0.28 ns bin size is 0.13-0.31. The performance has a negligible dependence on the temperature. The power consumption and the potential to extend the number of channels are also discussed. (C) 2017 Elsevier B.V. All rights reserved.

关键词： Time-to-digital converter field-programmable gate array

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FPGAS VERSUS GPUS IN DATACENTERS

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IEEE MICRO 2017年第1期37卷 60-72页

作者： Falsafi, Babak Dally, Bill Singh, Desh Chiou, Derek Yi, Joshua J. Sendag, Resit Ecole Polytech Fed Lausanne Dept Comp & Commun Sci Lausanne Switzerland Stanford Univ Comp Sci & Elect Engn Stanford CA 94305 USA Amazon Software Dev Toronto ON Canada Microsoft Redmond WA USA Dechert Philadelphia PA USA Univ Rhode Isl Elect & Comp Engn Kingston RI 02881 USA

THIS ARTICLE PRESENTS POSITION STATEMENTS AND A QUESTION-AND-ANSWER SESSION BY PANELISTS AT THE FOURTH WORKSHOP ON COMPUTER ARCHITECTURE RESEARCH DIRECTIONS. THE SUBJECT OF THE DEBATE WAS THE USE OF field-programmable... 详细信息

关键词： Bandwidth allocation CARD computer architecture Data centers datacenter debate field programmable gate arrays field-programmable gate array FPGA GPU Graphics processing units Programming research directions Servers

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Hybrid analytical model of switched reluctance machine for real-time hardware-in-the-loop simulation

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IET ELECTRIC POWER APPLICATIONS 2017年第6期11卷 1114-1123页

作者： Xu, Fengqiu Dinavahi, Venkata Xu, Xianze Wuhan Univ Elect Informat Sch Wuhan Hubei Province Peoples R China Univ Alberta Dept Elect & Comp Engn 9107-116 St Edmonton AB T6G 2V4 Canada

Applications of switched reluctance machine (SRM) are increasing in the industry due to their many desirable features. This study proposes a hybrid analytical model (HAM) of the SRM for the hardware-in-the-loop (HIL) simulation. To obtain satisfactory accuracy, the phase flux linkage is solved by the magnetic equivalent circuit (MEC) method when the stator and rotor poles overlap, and by the space harmonic method (SHM) when the poles do not overlap. The backward Euler and Newton-Raphson methods are used to calculate the exciting current, while the Gaussian quadrature is used to compute the electromagnetic torque in the HIL simulation. The digital hardware implementation of computation components are developed on the field-programmable gate array by exploiting the parallel hardware architecture and fully pipelined arithmetic processing. To highlight the performance of the HAM, the captured real-time results are compared with the off-line transient solution obtained through the co-simulation of Ansys Maxwell((R)), Ansys Simplorer((R)), and Simulink((R)), which model the SRM, drive circuit, and control system, respectively.

关键词： reluctance machines hardware-in-the loop simulation electric machine analysis computing machine theory magnetic circuits magnetic flux equivalent circuits stators rotors harmonic analysis Newton-Raphson method Gaussian processes integration field programmable gate arrays parallel architectures pipeline arithmetic Ansys Simplorer simulation Simulink simulation drive circuit control system Ansys Maxwell simulation offline transient solution pipelined arithmetic processing parallel hardware architecture field-programmable gate array digital hardware implementation electromagnetic torque computation Gaussian quadrature exciting current calculation Newton-Raphson method backward Euler method SHM space harmonic method rotor pole stator pole MEC method magnetic equivalent circuit method phase flux linkage HIL simulation hybrid analytical model HAM SRM hardware-in-the-loop simulation switched reluctance machine

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Development of Compact, Cost-effective, FPGA-Based Data Acquisition System for the iPET System

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JOURNAL OF MEDICAL AND BIOLOGICAL ENGINEERING 2017年第6期37卷 858-866页

作者： Min, Eungi Kim, Kwangdon Lee, Hakjae Kim, Hyun-Il Chung, Yong Hyun Kim, Yongkwon Joung, Jinhun Kim, Kyeong Min Joo, Sung-Kwan Lee, Kisung Korea Univ Dept IT Convergence Seoul South Korea Korea Univ Dept Bioconvergence Engn Seoul South Korea Korea Univ Sch Biomed Engn Seoul South Korea Yonsei Univ Dept Radiat Convergence Engn Wonju South Korea Korea Inst Nucl Safety Daejeon South Korea NuCare Inc Incheon South Korea Korea Inst Radiol & Med Sci Div Med Radiat Equipment Seoul South Korea Korea Univ Sch Elect Engn Seoul South Korea

Positron emission tomography (PET) is a nuclear medicine imaging technology used to analyze physiological processes. An in-beam PET is used to verify the delivered dose during ion-beam therapy. Our group investigates the prototype C-shaped PET system, which is called the iPET system. In this study, we develop an expendability-enhanced field-programmable gate array (FPGA)-based data acquisition system for the iPET. We organize this data acquisition (DAQ) system using only one DAQ board, to ensure a compact and cost-effective DAQ system. We design the FPGA using modular functions, which include synchronization, deserialization, pulse height analysis, and data packaging functions. As a result, energy spectra and well-separated 9 x 9 flood images of the entire detector module are achieved. We obtain reconstructed PET images of point source (4 mm diameter), three cylindrical phantoms (3 cm diameter), and four sphere phantoms (3.0, 2.2, 1.3 and 1.0 cm diameter). We achieve approximately 300 kcps of maximum single count rate. The obtained results prove the compactness and cost-effectiveness of the proposed DAQ system.

关键词： In-beam PET Data acquisition system field-programmable gate array Modular function

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MIPSfpga: using a commercial MIPS soft-core in computer architecture education

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IET CIRCUITS DEVICES & SYSTEMS 2017年第4期11卷 283-291页

作者： Harris, Sarah L. Harris, David M. Chaver, Daniel Owen, Robert Kakakhel, Zubair L. Sedano, Enrique Panchul, Yuri Ableidinger, Bruce Univ Nevada Dept Elect & Comp Engn Las Vegas NV 89154 USA Harvey Mudd Coll Dept Engn Claremont CA 91711 USA Univ Complutense Madrid Dept Comp Architecture & Automat Madrid Spain Imaginat Technol Ltd Kings Langley WD4 8LZ Herts England

In this study, the authors introduce MIPSfpga and its accompanying set of learning materials. MIPSfpga is a teaching infrastructure that offers access to the non-obfuscated Register-Transfer Level (RTL) source code of the MIPS microAptiv UP processor. The core is made available by Imagination Technologies for academic use and is targeted to a field-programmable gate array (FPGA), making it ideal for both the classroom and research. The supporting materials and labs focus on hands-on learning that emphasises computer architecture, system on chip (SoC) design and hardware-software codesign. Among other things, students learn to set up the MIPS soft-core processor on an FPGA, run and debug programs on the core in simulation and in hardware, add new peripherals to the system, understand the microarchitecture and extend it to support new features, experiment with different cache sizes and content management policies, add new instructions using the CorExtend interface available in MIPS processors, and understand SoCs in embedded systems and how they are designed and built up in layers to run complex software such as Linux.

关键词： field programmable gate arrays microprocessor chips computer science education computer architecture learning (artificial intelligence) source code (software) system-on-chip hardware-software codesign electronic engineering education MIPSfpga commercial MIPS soft-core processor computer architecture education learning materials teaching infrastructure nonobfuscated RTL source code MIPS microAptiv UP processor Imagination Technologies academic use field-programmable gate array hands-on learning system on chip SoC hardware-software codesign program debugging cache sizes content management policies CorExtend interface Linux

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Evolutionary design of hash function pairs for network filters

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APPLIED SOFT COMPUTING 2017年 56卷 173-181页

作者： Dobai, Roland Korenek, Jan Sekanina, Lukas Brno Univ Technol Fac Informat Technol Ctr Excellence IT4Innovat Brno Czech Republic

Network filtering is a challenging area in high-speed computer networks, mostly because lots of filtering rules are required and there is only a limited time available for matching these rules. Therefore, network filters accelerated by field-programmable gate arrays (FPGAs) are becoming common where the fast lookup of filtering rules is achieved by the use of hash tables. It is desirable to be able to fill-up these tables efficiently, i.e. to achieve a high table-load factor in order to reduce the offline time of the network filter due to rehashing and/or table replacement. A parallel reconfigurable hash function tuned by an evolutionary algorithm (EA) is proposed in this paper for Internet Protocol (IP) address filtering in FPGAs. The EA fine-tunes the reconfigurable hash function for a given set of IP addresses. The experiments demonstrate that the proposed hash function provides high-speed lookup and achieves a higher table-load factor in comparison with conventional solutions. (C) 2017 Elsevier B.V. All rights reserved.

关键词： Evolutionary algorithm Hash function Network filter field-programmable gate array Cuckoo

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Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches

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IEEE MICRO 2017年第5期37卷 44-51页

作者： Tokusashi, Yuta Matsutani, Hiroki Keio Univ Tokyo Japan Keio Univ Dept Informat & Comp Sci Tokyo Japan

Key-value store accelerators based on field-programmable gate arrays (FPGAs) have been proposed to achieve higher performance per watt than software-based processing. However, both their cache capacity and application domains are limited. The authors' proposed multilevel NoSQL cache architecture utilizes both an FPGA-based hardware cache and a complementary in-kernel software cache. Their design reduces the cache miss ratio and improves throughput compared to the nonhierarchical design.

关键词： Accelerators field programmable gate arrays field-programmable gate array FPGA key-value store NoSQL Random access memory

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CONFIGURABLE CLOUDS

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IEEE MICRO 2017年第3期37卷 52-61页

作者： Caulfield, Adrian M. Chung, Eric S. Putnam, Andrew Angepat, Hari Firestone, Daniel Fowers, Jeremy Haselman, Michael Heil, Stephen Humphrey, Matt Kaur, Puneet Kim, Joo-Young Lo, Daniel Massengill, Todd Ovtcharov, Kalin Papamichael, Michael Woods, Lisa Lanka, Sitaram Chiou, Derek Burger, Doug Microsoft Redmond WA 98052 USA Microsoft Azure Networking Host SDN Team Redmond WA 98052 USA

The Configurable Cloud datacenter architecture introduces a layer of reconfigurable logic between the network switches and servers. The authors deploy the architecture over a production server bed and show how it can accelerate applications that were explicitly ported to field-programmable gate arrays, support hardware-first services, and accelerate applications without any application-specific FPGA code being written.

关键词： accelerators datacenter distributed computing field-programmable gate array FPGA hyperscale

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A review of demodulation techniques for amplitude-modulation atomic force microscopy

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BEILSTEIN JOURNAL OF NANOTECHNOLOGY 2017年第1期8卷 1407-1426页

作者： Ruppert, Michael G. Harcombe, David M. Ragazzon, Michael R. P. Moheimani, S. O. Reza Fleming, Andrew J. Univ Newcastle Sch Elect Engn & Comp Callaghan NSW 2308 Australia Norwegian Univ Sci & Technol NTNU Dept Engn Cybernet Trondheim Norway Univ Texas Dallas Dept Mech Engn Richardson TX 75083 USA

In this review paper, traditional and novel demodulation methods applicable to amplitude-modulation atomic force microscopy are implemented on a widely used digital processing system. As a crucial bandwidth-limiting component in the z-axis feedback loop of an atomic force microscope, the purpose of the demodulator is to obtain estimates of amplitude and phase of the cantilever deflection signal in the presence of sensor noise or additional distinct frequency components. Specifically for modern multifrequency techniques, where higher harmonic and/or higher eigenmode contributions are present in the oscillation signal, the fidelity of the estimates obtained from some demodulation techniques is not guaranteed. To enable a rigorous comparison, the performance metrics tracking bandwidth, implementation complexity and sensitivity to other frequency components are experimentally evaluated for each method. Finally, the significance of an adequate demodulator bandwidth is highlighted during high-speed tapping-mode atomic force microscopy experiments in constant-height mode.

关键词： amplitude estimation atomic force microscopy amplitude modulation digital signal processing field-programmable gate array

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