检索结果-内蒙古大学图书馆

ON-State Reliability of Cu Atom Switch Under Current-Temperature Stress

IEEE TRANSACTIONS ON ELECTRON DEVICES 2015年第9期62卷 2992-2997页

作者： Tada, Munehiro Okamoto, Koichiro Sakamoto, Toshitsugu Hada, Hiromitsu NEC Corp Ltd Tsukuba Ibaraki 3058501 Japan

The dc current-stress tolerance of the ON-state Cu atom switch is evaluated at elevated temperature. It is revealed that the reset-direction current stress causes time-dependent failures, which originate from the E-field-driven diffusion of Cu in the conducting bridge. A new empirical lifetime estimation model, including the Joule heating effect, gives an allowable maximum current per atom switch of I-max = 115 mu A, which is large enough to satisfy the requirements for signal routing under currents that are average (18 mu A) and peak (63 mu A) in the reconfigurable switch block operated at 500 MHz at 125 degrees C.

关键词： Atom switch field-programmable gate array nonvolatile memory programmable logic device polymer reconfigurable logic solid electrolyte

来源：评论

学校读者我要写书评

暂无评论

A compact hardware architecture for digital image stabilization using integral projections

引用

MICROPROCESSORS AND MICROSYSTEMS 2015年第8期39卷 987-997页

作者： Araneda, Luis Figueroa, Miguel Univ Concepcion Dept Elect Engn Concepcion Chile Univ Concepcion Ctr Opt & Photon CEFOP Concepcion Chile

We present a hardware architecture for real-time digital video stabilization for high-performance embedded systems. The stabilization algorithm analyzes the current and past video frames and obtains a motion estimation vector, which is then filtered to isolate unwanted camera movements from intentional panning. The vector is then used to correct the output video frame. The paper describes our hardware architecture for motion estimation, filtering and correction and its implementation on a Xilinx Spartan-6 LX45 FPGA. We evaluate our results on several benchmark video sequences, both visually and using the Inter-frame Transformation Fidelity index (ITF). Running on the 640 x 480-pixel video output of an infrared camera, our FPGA implementation successfully compensates involuntary camera motion at a maximum throughput of 104.15 frames per second with a 100 MHz clock. The power consumption added to the FPGA by the image stabilization core is only 24.16 mW. (C) 2015 Elsevier B.V. All rights reserved.

关键词： Embedded video processing field-programmable gate array Digital image stabilization Integral projections

来源：评论

学校读者我要写书评

暂无评论

High-resolution detection of sustained ventricular and supraventricular tachycardia through FPGA-based fuzzy processing of ECG signal

引用

MEDICAL & BIOLOGICAL ENGINEERING & COMPUTING 2015年第10期53卷 1037-1047页

作者： Chowdhury, Shubhajit Roy Indian Insitute Technol Mandi Sch Comp & Elect Engn Mandi 175005 Himachal Prades India

The paper presents a field-programmable gate array (FPGA)-based fast processing system with 12-channel high-resolution (24 bits) front-end for ECG signal processing. The implemented high-resolution data conversion makes the system suitable for recording of late potentials of the QRS complex in patients prone to sustained ventricular tachycardia. The system accepts ECG signals through 12 channels and then filtered to minimize baseline wander and power-line interference. The filter outputs are connected to 12 delta-sigma ADCs. The whole ADCs work synchronously at 8 kHz sampling frequency, and their output data are transferred to an FPGA that computes online on the digitized sample values in real time and ascertains whether the patient under study suffers from ventricular tachycardia or not. In order to ascertain the QRS complex accurately in the noisy ECG signal, fuzzy entropy of the sample values has been computed and provided as an input to inverse multiquadratic radial basis function neural network. Using the standard CSE ECG database, the algorithm performed highly effectively. The performance of the algorithm in respect of QRS detection with sensitivity of 99.83 % and accuracy of 99.7 % is achieved when tested using single-channel ECG with entropy criteria. The performance of the QRS detection system has been compared and found to be better than most of the QRS detection systems available in the literature. Using the system, 200 patients have been diagnosed with an accuracy of 99 %.

关键词： field-programmable gate array ECG Ventricular tachycardia Differential diagnosis

来源：评论

学校读者我要写书评

暂无评论

In-Memory Data Rearrangement for Irregular, Data-Intensive Computing

引用

COMPUTER 2015年第8期48卷 18-25页

作者： Lloyd, Scott Gokhale, Maya Lawrence Livermore Natl Lab Livermore CA 94550 USA

The data rearrangement engine (DRE) performs in-memory data restructuring to accelerate irregular, data-intensive applications. An emulation on a field-programmable gate array shows how the DRE could improve speedup, ... 详细信息

关键词： field programmable gate arrays DRE data rearrangement engine energy consumption improvement field-programmable gate array in-memory data rearrangement in-memory data restructuring irregular-data-intensive application acceleration memory bandwidth improvement speedup improvement Computer applications Emulation field programmable gate arrays Memory management Stacked memory 3D stacked memory FPGA emulation active memory data rearrangement engine data-intensive computing irregular applications processing in memory

来源：评论

学校读者我要写书评

暂无评论

Multi-core DSP-based Vector Set Bits Counters/Comparators

引用

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2015年第3期80卷 309-322页

作者： Sklyarov, Valery Skliarova, Iouliia Univ Aveiro Dept Elect Telecommun & Informat IEETA P-3810193 Aveiro Portugal

The paper shows that fast counting non-zero components (Hamming weights) and comparing the results (Hamming distances) in large sets of data items is important for numerous practical applications and this problem has been broadly investigated by software and hardware designers. It is frequently referenced as population or vector set bits count (or simply popcount). This paper is dedicated to multi-core FPGA-based accelerators that compute Hamming weights/distances and compare the results with fixed thresholds and variable bounds. It is shown that widely available in contemporary FPGAs digital signal processing slices may be used efficiently and they provide the fastest and the less resource consuming solutions. A thorough analysis and comparison with the best known alternatives both in hardware and in software is presented and supported by numerous experiments in the recent Nexys-4, ZedBoard and ZyBo prototyping systems. Complete hardware description language (VHDL) specifications for core components are given ready to be synthesized, implemented, tested and evaluated. Experiments with the proposed designs clearly demonstrate significant speed-up comparing to known hardware/software alternatives.

关键词： Hamming weight/population/vector setbits counter Hamming weight comparator field-programmable gate array Digital signal processing slice Hardware accelerator On-chip architecture

来源：评论

学校读者我要写书评

暂无评论

Design of Handheld Oscilloscope Based on FPGA and Dual A/D

Design of Handheld Oscilloscope Based on FPGA and Dual A/D

引用

2016 4th International Conference on Electrical&Electronics Engineering and Computer Science(ICEEECS 2016)

作者： Hu Yang Yuduo Wang School of Information & Communication Engineering Beijing Information Science & Technology Univerdity

ISBN: (纸本)9781510835429

Handheld oscilloscope because of its portability, wide application range and other characteristics, has drawn more and more attention in the engineering practice. Anolog-todigital conversion circuit plays an important role in the design of digital oscilloscope. It directly determines the maximum frequency of digital oscilloscope can be measured. This paper focuses on the analysis of three methods of improving the sampling rate, eventually adopts double anolog-to-digital converter sampling approach to the design of a handheld oscilloscope, sampling frequency can reach two times the maximum sampling frequency of anolog-to-digital converter, so as to improve the accuracy of frequency measurement range of oscilloscope and the waveform display, and without significant increase in cost and easy to realize. The oscilloscope with embedded processor STM32 as control core, using field-programmable gate array(FPGA) for data processing. The signal collected by automatic gain control, dual anolog-digital converter sampling,data cache, digitalto-anolog conversion process, displayed on the screen. At the same time,the oscilloscope realizes the functions of test signal's display, measurement and the corresponding parameter adjustment.

关键词： Handheld oscilloscope field-programmable gate array STM32 Double Anologto-Digital sampling Sampling frequency

来源：评论

学校读者我要写书评

暂无评论

Optical Transceiver with Deficit Round Robin and RS232 Interface for Synchronous Optical Networking

Optical Transceiver with Deficit Round Robin and RS232 Inter...

引用

IEEE International Conference on Systems, Man, and Cybernetics

作者： Guo-Ming Sung Wen-Duen Chou Tzu-Hsuan Chiu Department of Electrical Engineering National Taipei University of Technology Taiwan

ISBN: (纸本)9781509018987

This paper presents an optical transceiver, whose packet process is completed with deficit round robin (DRR) and RS232 interface, for optical synchronous optical networking (SONET) which can service on both asymmetric digital subscriber line (ADSL) and optical packet switching (OPS). To resolve the clock jitter, not only the cycle decision but also the reset function are used to synchronize the clock waveform. In the proposed DRR, it performs the packet process with low delay and low loss. Moreover, the RS232 interface, which is integrated with the field-programmable gate array (FPGA) board, is adopted due to its easy implementation. The processing data will be queued with DRR and be sent to electrical/optical (E/O) converter from the RS232 port on FPGA board (Transmitter). Passing through the optical fiber, the packet from transmitter is sent to the O/E converter and then received at the RS232 port on another FPGA board. The received electrical packet will be displayed on the seven-segment display of FPGA board to verify the transceiver function for SONET. Note that the proposed architecture is designed with Verilog hardware describe language (Verilog HDL). According to the measured results, the data transfer rate is 115, 200 bps with the FPGA operating frequency of 50 MHz and the fiber distance of 5 km.

关键词： field-programmable gate array defict round robin RS232 interface transceiver synchronous optical netwoking asymmetric digital subscriber line hardware describe language

来源：评论

学校读者我要写书评

暂无评论

A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis

引用

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2015年第2期31卷 207-215页

作者： Pereira, Igor Gadelha Dias, Leonardo Alves de Souza, Cleonilson Protasio Fed Univ Paraiba UFPB Dept Elect Engn Joao Pessoa Paraiba Brazil

This paper describes the implementation of a shift-register based Built-In Self-Test (BIST) architecture for FPGA global interconnection resources testing. Through this, it is possible to configure FPGA resources that need to be tested in order to obtain high reliability FPGA-based systems. The proposed BIST approach takes advantage of FPGA low-level resources in order to generate cyclic test patterns, analyse testing response and store test results in a simple way. Additionally, the same BIST configuration set is capable of diagnosing the tested interconnection resources with no additional configurations thereby reducing time requirements. This paper presents the proposed BIST architecture and its diagnosis scheme, its implementation on a Xilinx FPGA, and experimental results.

关键词： Built-in self-test field-programmable gate array Global interconnection resource testing FPGA testing and diagnosis

来源：评论

学校读者我要写书评

暂无评论

EFFICIENT DIGITAL IMPLEMENTATION OF SIGNAL PROCESSING ALGORITHMS IN STATE-OF-THE-ART field-programmable gate arrayS FOR GAMMA-RAY SPECTROSCOPY

引用

NUCLEAR TECHNOLOGY 2014年第1期187卷 69-81页

作者： Fahiman, Fateme Kafaee, Mahdi Moussavi-Zarandi, Alt Fahiman, Meisam Amirkabir Univ Technol Dept Energy Engn & Phys Tehran Iran Iran Univ Sci & Technol Dept Comp Engn Tehran Iran

In this work, a board based on a Spartan-3 field-programmable gate array was designed as a hardware prototyping platform for development of a multichannel digital gamma spectrometer. The device is compatible with various detectors like high-purity germanium, NaI, and CsI detectors. Before implementing the hardware, the method for digital signal processing for gamma spectroscopy was developed. The aim of this paper is to introduce a robust tool suitable for optimizing the design of complicated systems. The characteristics of this method, such as its ability to implement adaptive shaping, are investigated. The optimum conditions for digital filtering were determined using MATLAB/Simulink. This scheme can be useful for commercial production. Simulation was used to examine each processing unit in the whole signal processing procedure including cusplike shaping. The proposed method can be used as a computer design tool for optimizing digital multichannel analyzers or digital nuclear spectrometers.

关键词： digital pulse spectrometer system simulation field-programmable gate array

来源：评论

学校读者我要写书评

暂无评论

DESIGN AND OPTIMIZATION OF A HORIZONTALLY PARTITIONED, HIGH-SPEED, 3D TREE-BASED FPGA

引用

IEEE MICRO 2015年第6期35卷 48-59页

作者： Pangracious, Vinod Marrakchi, Zied Mehrez, Habib Univ Paris 06 Elect Engn F-75252 Paris 05 France Flexras Technol St Denis France Univ Paris 06 Syst Chip Dept F-75252 Paris 05 France

The authors explore and design the traditional field-programmable gate array (fpga) interconnect topologies and architectures that can play an important role in improving performance and density. they address long wire length issues associated with tree-based programmable interconnects using 3d design and manufacturing technologies. using their dedicated 3d design and optimization methodology, the authors show that 3d tree-based architecture is 1.5 times faster than the mesh-based counterpart.

关键词： 3D integration BFT butterfly fat tree Computer architecture Delays field programmable gate arrays field-programmable gate array FPGA Integrated circuit interconnections mesh Routing Three-dimensional displays through silicon via Through-silicon vias tree-based FPGA TSV

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：