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A multiprocessor-on-a-programmable-chip reconfigurable system for matrix operations with power-grid case studies

INTERNATIONAL JOURNAL OF COMPUTATIONAL SCIENCE AND ENGINEERING 2015年第1-2期10卷 181-191页

作者： Wang, Xiaofang Ziavras, Sotirios G. Villanova Univ Dept Elect & Comp Engn Villanova PA 19085 USA New Jersey Inst Technol Dept Elect & Comp Engn Newark NJ 07102 USA

Recent advances in field-programmable gate array (FPGA) technologies have made feasible the implementation of low-cost parallel computing platforms for high-performance matrix computations. Compared to conventional multiprocessor systems, the resulting multiprocessors-on-a-programmable-chip (MPoPC) can provide unique advantages and opportunities in both software and hardware. It is shown in this paper that the performance of an MPoPC can be improved dramatically by adapting slightly intellectual property (IP)-based processing elements, and customising the memory and the interconnection network. The parallel LU factorisation of large, sparse doubly-bordered block diagonal (DBBD) matrices is employed as an application example. To enhance further the performance by software techniques, a run-time load balancing strategy for this algorithm is proposed and analysed. Extensive experimental results on benchmark matrices of size up to 7,917 x 7,917 for power networks demonstrate the effectiveness of our effort.

关键词： field-programmable gate array FPGA multiprocessors-on-a-programmable-chip MPoPC parallel LU factorisation doubly-bordered block diagonal DBBD dynamic load balancing

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Design and analysis of a dual mode CMOS field programmable analog array

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Journal of Semiconductors 2014年第10期35卷 152-162页

作者：程小燕杨海钢尹韬吴其松张洪锋刘飞 Institute of Electronics Chinese Academy of Sciences University of Chinese Academy of Sciences

This paper presents a novel field-programmable analog array （FPAA） architecture featuring a dual mode including discrete-time （DT） and continuous-time （CT） operation modes, along with a highly routable connection boxes （CBs） based interconnection lattice. The dual mode circuit for the FPAA is capable of achieving targeted op- timal performance in different applications. The architecture utilizes routing switches in a CB not only for the signal interconnection purpose but also for control of the electrical charge transfer required in switched-capacitor circuits. This way, the performance of the circuit in either mode shall not be hampered with adding of programmability. The proposed FPAA is designed and implemented in a 0.18 μm standard CMOS process with a 3.3 V supply voltage. The result from post-layout simulation shows that a maximum bandwidth of 265 MHz through the interconnection network is achieved. The measured results from demonstrated examples show that the maximum signal bandwidth of up to 2 MHz in CT mode is obtained with the spurious free dynamic range of 54 dB, while the signal processing precision in DT mode reaches 96.4%.

关键词： field-programmable gate array field-programmable analog array configurable analog block rail-to- rail biquadratic filters

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Enhanced Architecture of FIR Filters Using Block Memories 13

Enhanced Architecture of FIR Filters Using Block Memories

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13th IFAC and IEEE Conference on programmable Devices and Embedded Systems

作者： Pristach, Marian Dvorak, Vojtech Fujcik, Lukas Brno Univ Technol FEEC Dept Microelect CS-61090 Brno Czech Republic

The paper presents an enhanced architecture of finite impulse response digital filters. The proposed architecture contains one multiply-accumulate unit and random access men-wiry to store data. The architecture utilizes serial calculation to achieve minimum requirements on area. Time architecture is suitable for implementation in application specific integrated circuits and field programmable gate arrays. The main advantages of the architecture are higher operating frequency, lower power consumption and smaller area utilization in particular cases. (C) 2015, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： Digital signal processing digital filter structures finite impulse response application specific integrated circuit field-programmable gate array

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A digital architecture for striping noise compensation in push-broom hyperspectral cameras 38

A digital architecture for striping noise compensation in pu...

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Conference on Applications of Digital Image Processing XXXVIII

作者： Valenzuela, Wladimir E. Figueroa, Miguel Pezoa, Jorge E. Meza, Pablo Univ Concepcion Dept Elect Engn Concepcion Chile Univ Concepcion Ctr Opt & Photon Concepcion Chile Univ La Frontera Dept Elect Engn Temuco Chile

ISBN: (纸本)9781628417654

We present a striping noise compensation architecture for hyperspectral push-broom cameras, implemented on a field-programmable gate array (FPGA). The circuit is fast, compact, low power, and is capable of eliminating the striping noise in-line during the image acquisition process. The architecture implements a multi dimensional neural network (MDNN) algorithm for striping noise compensation previously reported by our group. The algorithm relies on the assumption that the amount of light impinging at the neighboring photo-detectors is approximately the same in the spatial and spectral dimensions. Under this assumption, two striping noise parameters are estimated using spatial and spectral information from the raw data. We implemented the circuit on a Xilinx ZYNQ XC7Z2010 FPGA and tested it with images obtained from a NIR N17E push-broom camera, with a frame rate of 25fps and a band-pixel rate of 1.888 MHz. The setup consists of a loop of 320 samples of 320 spatial lines and 236 spectral bands between 900 and 1700 nanometers, in laboratory condition, captured with a rigid push-broom controller. The noise compensation core can run at more than 100 MHZ and consumes less than 30mW of dynamic power, using less than 10% of the logic resources available on the chip. It also uses one of two ARM processors available on the FPGA for data acquisition and communication purposes.

关键词： striping noise compensation custom hardware architecture field-programmable gate array FPGA hardware/software codesign neural network

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Real-Time Digital Signal Processing for Coherent Optical Systems 17

Real-Time Digital Signal Processing for Coherent Optical Sys...

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17th International Conference on Transparent Optical Networks (ICTON)

作者： Pinto, Armando N. Amado, Sofia B. Martins, Celestino S. Ziaie, Somayeh Muga, Nelson Ferreira, Ricardo Teixeira, Antonio L. Guiomar, Fernando P. Univ Aveiro Dept Elect Telecommun & Informat Campus Univ Santiago P-3810193 Aveiro Portugal Inst Telecomunicacoes P-3810193 Aveiro Portugal

ISBN: (纸本)9781467378802

Digital signal processing (DSP) is nowadays a key enabling technology in coherent optical transmission systems, triggering an increasing research effort on the development and optimization of DSP subsystems. The first DSP development step is often based on the use of simulation tools and offline processing of experimental data. Complementarily, real-time implementation is a critical implementation step to assess the performance and feasibility of advanced DSP subsystems. In this work, we address both the offline and real-time stages of development, supported by an experimental optical testbed. Real-time demonstration is enabled by an FPGA processing platform and 1.25 Gsample/s analog-to-digital conversion.

关键词： optical communications coherent detection digital signal processing analog-to-digital converters real-time hardware implementation field-programmable gate array

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FPGA based Multiprocessor Embedded System for Real-Time Image Processing 15

FPGA based Multiprocessor Embedded System for Real-Time Imag...

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15th International Conference on Control, Automation and Systems (ICCAS)

作者： Masud, Nauman Nasir, Jahanzeb Nazir, Muhammad Shahid Aqil, Muhammad Pakistan Inst Engn & Appl Sci Dept Elect Engn PO 45650 Islamabad Pakistan

ISBN: (纸本)9788993215090

In this paper, a field-programmable gate array (FPGA) based multiprocessor architecture is proposed for real-time image processing. The system is developed based on a hardware-software co-design philosophy. A total of five soft-core MicroBlaze processors are configured in master-slave topology and furnished with BRAM cores. A frame grabbing and a serial port cores are developed for camera and PC interfacing, respectively. Each processor can be configured to perform a certain task and all processors operate in parallel, hence providing high speed computing desirable for real -time image processing. The validity of the proposed embedded platform, realized on an XtremeDSP Development Kit-IV, is demonstrated by grabbing and processing real-time images.

关键词： Embedded system field-programmable gate array image processing real-time multicore processing

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FPGA Implementation of Second-Order Difference Plot for Epileptic Seizure Detection in EEG Signals 12

FPGA Implementation of Second-Order Difference Plot for Epil...

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12 IEEE Int C Elect Energy Env Communications Computer Control

作者： Singh, Ardra Prince, A. Amalin Birla Inst Technol & Sci Pilani Elect & Elect Engn Dept KK Birla Goa Campus Pilani Goa India

ISBN: (纸本)9781467365406

field-programmable gate arrays (FPGAs) are being extensively used for a wide range of digital applications due to their flexibility and reprogrammability. This paper presents a FPGA implementation of the second -order difference plot (SODP) technique which can be used for the classification of ictal and seizure -free electroencephalogram (EEG) signals. Empirical mode decomposition (EMD) can break down an EEG signal into simple oscillatory modes called intrinsic mode functions (IMFs). The hardware design developed takes a sampled IMF of an EEG signal as input and generates its SODP while simultaneously calculating the 95 percent confidence ellipse area of the SODP. The ellipse area can be used as a parameter for detecting epileptic seizures in EEG signals. The digital circuit was designed in the Vivado integrated development environment (IDE) using Verilog hardware description language (HDL) and a Xilinx Artix-7 xc7a100tcsg324 FPGA was used to verify operation of the physical implementation. The hardware was tested on EEG data made publicly available by the University of Bonn and the results were found to be consistent with MATLAB simulations.

关键词： field-programmable gate array epileptic seizure electroencephalogram signal second-order difference plot 95% confidence ellipse area

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The Conversion Algorithm of Voltage Source Inverter Control Signals for Operating Current Source Inverter 16

The Conversion Algorithm of Voltage Source Inverter Control ...

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16th International Conference of Young Specialists on Micro/Nanotechnologies and Electron Devices

作者： Volkov, Alexander G. Makarov, Denis V. Zharkov, Maksim A. Balagurov, Maxim V. Novosibirsk State Tech Univ Novosibirsk Russia

ISBN: (纸本)9781467367196

This paper considers one of the methods for controlling the current source inverter, which uses previously generated control signals for the voltage source inverter. Describes the instructional method for converting these signals with minimization of switching losses. Analysis results are verified with simulation modeling of control systems in the software PowerSIM, as well as experimental investigations of microprocessor control system based on field-programmable gate array.

关键词： currents source inverter voltage source inverter control algorithm field-programmable gate array

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A Review of Embedded Systems Used in WMR for the Trajectory Tracking Task

A Review of Embedded Systems Used in WMR for the Trajectory ...

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IEEE International Conference on Mechatronics, Electronics and Automotive Engineering (ICMEAE)

作者： Marquez-Sanchez, C. Silva-Ortigoza, R. Antonio-Cruz, M. Sosa-Cervantes, C. Y. Hernandez-Guzman, V. M. Inst Politecn Nacl CIDETEC Area Mecatron Unidad Profes Adolfo Lopez Mateos Mexico City 07700 DF Mexico Univ Autonoma Queretaro Fac Ingn Queretaro 76150 Qro Mexico

ISBN: (纸本)9781467383295

In this work a review of the more outstanding contributions, carried out in the automatic control context, that deal with the trajectory tracking task in autonomous wheeled mobile robots (WMR) by using an embedded system is presented. In this direction, with the intention of describing an embedded system, some definitions of such a system and also the parts integrating it are introduced. The contributions related to the trajectory tracking task in WMR are grouped according to the used hardware, namely, microcontroller, field-programmable gate array, and digital signal processor. Additionally, works that use an embedded system in the implementation of the trajectory tracking task for a WMR, but they do not give importance to such a system are included. Moreover, studies using personal computers and laptops to execute some control problems associated with WMR are considered. In general, this paper points the works dealing with the use of embedded systems in WMR, identifying a wide variety of embedded systems models.

关键词： Robotics Mechatronics Wheeled Mobile Robots Trajectory Tracking Task Embedded Systems Microcontroller field-programmable gate array Digital Signal Processor

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Reactive and Harmonic Compensation Using the Conservative Power Theory 10

Reactive and Harmonic Compensation Using the Conservative Po...

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10th International Conference on Ecological Vehicles and Renewable Energies (EVER)

作者： Haugan, Thomas S. Tedeschi, Elisabetta Norwegian Univ Sci & Technol NTNU Dept Elect Power Engn OS Bragstads Plass 2E N-7491 Trondheim Norway

ISBN: (纸本)9781467367851

This paper explores the use of the conservative power theory for active shunt compensation, and provides experimental validation of reactive compensation and harmonic filtering. It is aimed to provide a more in-depth review of how the conservative power theory operates as a control algorithm for a shunt compensator. Also there is discussion on some of the challenges associated to practical implementation of active filters.

关键词： Active power filtering conservative power theory field-programmable gate array non-linear loads rapid-control prototyping reactive compensation harmonic filtering

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