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22nd European Signal Processing Conference (EUSIPCO)

作者： Zhou, Qi Ma, Xiaoli Ratrix Technol Atlanta GA 30308 USA Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA

ISBN: (纸本)9780992862619

Because of their lower complexity and better error performance over K-best detectors, lattice-reduction (LR)-aided K-best detectors have recently proposed for large-scale multi-input multi-output (MIMO) detection. Among existing LR-aided K-best detectors, complex LR-aided K-best detector is more attractive compared to its real counterpart due to its potential lower latency and resources. However, one main difficulty in hardware implementation of complex LR-aided K-best is to efficiently find top K children of each layer in complex domain. In this paper, we propose and implement an LR-aided K-best algorithm that efficiently finds top K children in each layer when K is relatively small. Our implementation results on Xilinx VC707 FPGA board show that, with the aid of LR, the proposed LR-aided K-best implementation can support 3 Gbps transmissions for 16x16 MIMO systems with 1024-QAM with about 2.7 dB loss to the maximum likelihood detector at bit-error rate 10(-4).

关键词： Lattice reduction large-scale MIMO K-best algorithm field-programmable gate array very-large-scale integration

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High Performance FPGA Implementation of Elliptic Curve Cryptography over Binary fields 13

High Performance FPGA Implementation of Elliptic Curve Crypt...

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13th IEEE International Conference on Trust Security and Privacy in Computing and Communications (TrustCom)

作者： Liu, Shuai Ju, Lei Cai, Xiaojun Jia, Zhiping Zhang, Zhiyong Shandong Univ Sch Comp Sci & Technol Jinan Peoples R China

ISBN: (纸本)9781479965137

In this paper, we propose a high performance hardware implementation architecture of elliptic curve scalar multiplication over binary fields. The proposed architecture is based on the Montgomery ladder method and uses polynomial basis for finite field (FF) arithmetic. A single Karatsuba multiplier runs with no idle cycle significantly increases the performance of FF multiplication while spending small amount of hardware resources, and other FF operations performed in parallel with the FF multiplier. The optimized circuits lead to a lesser area requirement compared to other high performance implementations. An implementation for the National Institute of Standards and Technology (NIST) recommended curve with degree 163 is shown, the proposed design can reach 121 MHz with 10,417 slices when implemented on Xilinx Virtex-4 XC4VLX200 FPGA device, the total time required for one elliptic curve scalar multiplication is 9.0 mu s.

关键词： elliptic curve cryptography field-programmable gate array binary fields polynomial basis

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FPGA-Based Quantum Circuit Emulation: A Case Study on Quantum Fourier Transform 14

FPGA-Based Quantum Circuit Emulation: A Case Study on Quantu...

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14 International Symposium on Integrated Circuits (ISIC)

作者： Lee, Y. H. Khalil-Hani, M. Marsono, M. N. Univ Teknol Malaysia Fac Elect Engn VeCAD Res Lab Utm Skudai 81310 Johor Bahru Malaysia

ISBN: (纸本)9781479948338

Hardware emulation based on field programmable gate array (FPGA) platform is vital to harness the power of quantum parallelism. As resource requirement grows exponentially in classical modeling quantum system, an optimum hardware architecture is crucial to emulate practical quantum circuits. Quantum Fourier transform (QFT) finds application in several critical quantum algorithms. In this work, experiments are conducted based on QFT to identify suitable qubit representation and hardware design technique. Experimental results show that 24-bit fixed point representation and serial architecture achieve optimal computation accuracy and resource utilization in QFT circuit emulation.

关键词： quantum circuit hardware emulation quantum Fourier transform field-programmable gate array

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An All Digital Speed Adaptive Maximum Power Point Tracker for Automotive Photovoltaic Applications 3

An All Digital Speed Adaptive Maximum Power Point Tracker fo...

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3rd International Conference on Renewable Energy Research and Application (ICRERA)

作者： Strache, Sebastian Wunderlich, Ralf Heinen, Stefan Rhein Westfal TH Aachen Integrated Analog Circuits & RF Syst Lab Aachen Germany

ISBN: (纸本)9781479937950

This paper proposes an all digital speed and step size adaptive maximum power point tracker (MPPT) for photovoltaic (PV) power generation, supporting the power supply of vehicles. To harvest significant amounts of energy in this application the MPPT has to deal with fast changing irradiance and severe shading. It has to achieve high tracking speed while maintaining tracking errors below 1 %. The presented modified perturb and observe (P&O) MPPT algorithm meets these requirements by applying digital filtering to detect the settling of the input voltage automatically. This enables minimal sampling time for each situation and, hence, very fast convergence to the maximum power point (MPP). The developed algorithm has been implemented on a field-programmable gate array (FPGA) and verified with an experimental setup. It achieves about 9 kHz average switching frequency while maintaining a tracking accuracy above 99.8 %.

关键词： automotive electrics convergence digital filters field programmable gate arrays maximum power point trackers perturbation techniques solar powered vehicles FPGA P and O MPPT algorithm PV power generation all digital speed adaptive maximum power point tracker automotive photovoltaic application digital filtering field-programmable gate array irradiance perturb and observe MPPT algorithm sampling time switching frequency tracking error vehicle power supply Accuracy Convergence Current measurement field programmable gate arrays Maximum power point trackers Time-frequency analysis Voltage measurement

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2014 International Symposium on Computer Architecture Influential Paper Award

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IEEE MICRO 2014年第6期34卷 94-95页

作者： Keckler, Stephen W. Nvidia University of California San Diego

This column discusses two awards given in 2014: the International Symposium on Computer Architecture Influential Paper Award, which was given to the authors of the paper 'PipeRench: A Coprocessor for Streaming Mul... 详细信息

关键词： Awards field-programmable gate array FPGA influential paper award ISCA Maurice Wilkes Award PipeRench Ravi Rajwar reconfigurable logic virtualization

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End-to-End Adaptive Packet Aggregation for High-Throughput I/O Bus Network Using Ethernet 22

End-to-End Adaptive Packet Aggregation for High-Throughput I...

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22nd IEEE Annual Symposium on High-Performance Interconnects (HOTI)

作者： Suzuki, Jun Hayashi, Yuki Kan, Masaki Miyakawa, Shinya Yoshikawa, Takashi NEC Corp Ltd Green Platform Res Labs Tokyo Japan

ISBN: (纸本)9781479958603

Input/output (I/O) bus networks using Ethernets transfer a PCI Express (PCIe) I/O packet between a host and an I/O device by encapsulating it into an Ethernet frame. Because the size of PCIe packets is generally small in such systems, the overhead to individually encapsulate them into Ethernet frames lowers the PCIe throughput provided by Ethernet connections. This decrease in throughput directly degrades the performance of I/O devices, which transmit high-throughput PCIe traffic. Examples of such devices include PCIe solid-state drives and graphics processing units. We propose a method of aggregating multiple PCIe packets into a single Ethernet frame in an end-to-end manner to provide a high-throughput PCIe connection. The aggregation is performed at the bottleneck-link rate of the Ethernet path through which those packets are transferred. The number of aggregated PCIe packets is adaptively determined by aggregating ones that reside in a transmission queue when it is scheduled to transmit packets. This enables low-latency throughput enhancement because the proposed method does not increase the transmission latency of PCIe packets by waiting for more packets to aggregate. In addition, it does not require individual configuration of operation parameters, such as aggregation threshold and time out value, depending on the rate of the PCIe traffic of I/O devices. We implemented our method in a PCIe-to-Ethernet bridge prototype using a field-programmable gate array. As a result, I/O performance improved up to 41%.

关键词： field programmable gate arrays graphics processing units local area networks telecommunication links telecommunication traffic Ethernet Ethernet frames PCI express I-O packet PCIe packets PCIe solid-state drives PCIe-to-Ethernet bridge prototype bottleneck-link rate end-to-end adaptive packet aggregation field-programmable gate array high-throughput I-O bus network high-throughput PCIe traffic low-latency throughput enhancement transmission queue Adaptive systems Aggregates Bridges Encapsulation Performance evaluation Standards Throughput field programmable gate arrays Ethernet networks Packet IO Graphics Processing Unit Telecommunication links Throughput Local Area Networks Adaptive systems telecommunication traffic bridges Performance Evaluation encapsulation Bus networks end-to-end

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Application of Polyphase Filter Banks to Wideband Monitoring Tasks

Application of Polyphase Filter Banks to Wideband Monitoring...

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IEEE North West Russia Young Researchers in Electrical and Electronic Engineering Conference (ElConRusNW)

作者： Kaplun, D. I. Klionskiy, D. M. Voznesenskiy, A. S. Gulvanskiy, V. V. St Petersburg Electrotech Univ LETI Dept Comp Sci St Petersburg 197376 Russia

ISBN: (纸本)9781479925940

The present paper discusses wideband monitoring and application of polyphase digital filter banks to dealing with practical tasks in this field. Various ways of classifying digital filter banks are provided including uniform DFT-modulated filter banks (direct and polyphase forms) and we also compare these banks by their performance. A particular polyphase filter bank with given characteristics is investigated in the time and frequency domains. Experimental research illustrates influence of white Gaussian noise on the quality of signal detection in filter bank channels. Experiments have been carried out on the basis of computer simulation in MATLAB and signal generation with the help of functions from standard MATLAB toolboxes. Experimental results contain plots of error of the first and second kinds versus signal-to-noise ratio at the input of a filter bank. Issues of polyphase filter bank implementation using CPU and CUDA are also considered in the paper.

关键词： wideband monitoring filter bank direct form polyphase form DFT-modulated filter bank field-programmable gate array CPU CUDA MATLAB

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Clock and carrier recovery in high-speed coherent optical communication systems 2

Clock and carrier recovery in high-speed coherent optical co...

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2nd International Conference on Applications of Optics and Photonics

作者： Amado, Sofia B. Ferreira, Ricardo Costa, Pedro S. Guiomar, Fernando P. Ziaie, Somayeh Teixeira, Antonio L. Muga, Nelson J. Pinto, Armando N. Univ Aveiro Dept Elect Telecommun & Informat Aveiro Portugal Inst Telecomun P-3810193 Aveiro Portugal Portugal Telecom PT Desenvolvimento Sistemas Rede Inovac Sistemas Aveiro Portugal

ISBN: (纸本)9781628413618

In this paper, the implementations of clock and carrier recovery in digital domain are analyzed. Hardware implementation details, resources estimation and real-time results are presented. Analog-to-Digital Converters (ADC), operating at 1.25Gsa/s, and a Virtex-6 field-programmable gate array (FPGA), have been used, allowing the implementation of a real-time Quadrature Phase Shift Keying (QPSK) system operating at 1.25Gb/s. The real-time mode operation is successfully demonstrated over 80 km of Standard Single Mode Fiber (SSMF).

关键词： Coherent detection digital signal processing analog-to-digital converters field-programmable gate array clock recovery carrier-recovery real-time

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Application of FPGA based PLL in a CSI fed induction heating prototype

Application of FPGA based PLL in a CSI fed induction heating...

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IEEE International Conference on Power Electronics, Drives, and Energy Systems (PEDES)

作者： Roy, Molay Sengupta, Mainak Indian Inst Engn Sci & Technol Dept Elect Engn Howrah 711103 WB India

ISBN: (纸本)9781479963737

Modern induction heating (IH) power converters operate marginally above resonant frequency to supply power to the targeted work-piece at near unity power factor (upf). The resonant frequency continuously increases as the work-piece gets heated up. A possible method of dynamically detecting the resonant frequency may be to calculate the phase-shift between current and voltage continuously during the process. The phase-shift between voltage and current is ideally zero at resonance. So resonant frequency may be identified by varying the frequency until the phase-shift is zero. For this some controllers use a phase-locked loop (PLL) strategy. In this paper, the dynamic tracking of resonant frequency, using a field-programmable gate array (FPGA) based digital-PLL, is presented. The scheme is first simulated off-line. Finally, the logic is implemented on controller hardware and practically tested in a laboratory made experimental set-up of 2kW at around 10kHz.

关键词： field programmable gate arrays induction heating invertors phase locked loops CSI fed induction heating prototype FPGA IH power converters PLL dynamic tracking field-programmable gate array induction heating power converters phase-locked loop resonant frequency Coils Electromagnetic heating field programmable gate arrays Frequency conversion Phase locked loops Prototypes Resonant frequency Phase locked loops field programmable gate arrays resonant frequencies Prolymphocytic Leukemia dynamic tracking Induction heating Electromagnetic heating Inventors Frequency conversion Coils Phase shift PROTOTYPE unity power factor

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VLSI Architecture of a High-Performance Neural Spiking Activity Simulator Based on Generalized Volterra Kernel 14

VLSI Architecture of a High-Performance Neural Spiking Activ...

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14 International Symposium on Integrated Circuits (ISIC)

作者： Li, Will X. Y. Xin, Yao Song, Dong Berger, Theodore W. Cheung, Ray C. C. City Univ Hong Kong Dept Elect Engn Hong Kong Hong Kong Peoples R China Univ So Calif Ctr Neural Engn Dept Biomed Engn Los Angeles CA 90089 USA

ISBN: (纸本)9781479948338

It is well known that information is represented and transmitted among neuronal units by a series of all-or-none "neural codes". In neuroinformatics study, this coding process, also termed as "spiking activity", is not straightforward for prediction. It is owing to the high nonlinearity and dynamic property involved in generation of the neuronal spikes. In this paper, a novel generalized Volterra kernel-based neural spiking activity simulator is introduced for prediction of the neural codes in mammalian hippocampal region. High-performance VLSI architecture is established for the simulator based on high-order Volterra kernels involving cross terms. The effectiveness and efficiency of the simulator are proven in experimental settings. This simulator has the potential to serve as a core functional unit in future hippocampal cognitive neural prosthesis.

关键词： neural spiking activity neural simulator field-programmable gate array neural prosthesis

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