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Slant transform applied to electric power quality detection with field programmable gate array design enhanced

INTERNATIONAL JOURNAL OF ELECTRICAL POWER & ENERGY SYSTEMS 2010年第5期32卷 428-432页

作者： Hsieh, Cheng-Tao Lin, Jeu-Min Huang, Shyh-Jier Natl Cheng Kung Univ Dept Elect Engn Tainan 70101 Taiwan Kun Shan Univ Dept Elect Engn Tainan Taiwan Far E Univ Dept Elect Engn Tainan Taiwan

In this paper, a slantlet transform is proposed with the field-programmable gate array (FPGA) hardware realization for electrical power system disturbance detection. By embedding the slantlet functions into wavelet basis, the method is anticipated to increase the capability of signal discrimination, hence improving the grasping the disturbance intrusion. Furthermore, with the hardware realization of FPGA chip, the practicality of the method can be better ensured. In order to validate the effectiveness of the proposed approach, several scenarios have been considered and verified with good agreement. (C) 2009 Elsevier Ltd. All rights reserved.

关键词： Electrical power system disturbances Slantlet transform field-programmable gate array

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A Soft Computing Approach to Crack Detection and Impact Source Identification with field-programmable gate array Implementation

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ADVANCES IN FUZZY SYSTEMS 2013年第unknown期2013卷

作者： Dixit, Arati M. Singh, Harpreet Def Inst Adv Technol DU Dept Comp Engn Pune 411025 Maharashtra India Wayne State Univ Dept Elect & Comp Engn Detroit MI 48202 USA

The real-time nondestructive testing (NDT) for crack detection and impact source identification (CDISI) has attracted the researchers fromdiverse areas. This is apparent fromthe current work in the literature. CDISI has usually been performed by visual assessment of waveforms generated by a standard data acquisition system. In this paper we suggest an automation of CDISI for metal armor plates using a soft computing approach by developing a fuzzy inference system to effectively deal with this problem. It is also advantageous to develop a chip that can contribute towards real time CDISI. The objective of this paper is to report on efforts to develop an automated CDISI procedure and to formulate a technique such that the proposedmethod can be easily implemented on a chip. The CDISI fuzzy inference system is developed using MATLAB's fuzzy logic toolbox. A VLSI circuit for CDISI is developed on basis of fuzzy logic model using Verilog, a hardware description language (HDL). The Xilinx ISE WebPACK9.1i is used for design, synthesis, implementation, and verification. The CDISI field-programmable gate array (FPGA) implementation is done using Xilinx's Spartan 3 FPGA. SynaptiCAD's Verilog Simulators-VeriLogger PRO andModelSim-are used as the software simulation and debug environment.

关键词： Hardware description language Soft computing Nondestructive testing Crack field-programmable gate array Fuzzy logic

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Spiking neural networks on FPGA: A survey of methodologies and recent advancements

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NEURAL NETWORKS 2025年 186卷 107256页

作者： Karamimanesh, Mehrzad Abiri, Ebrahim Shahsavari, Mahyar Hassanli, Kourosh van Schaik, Andre Eshraghian, Jason Shiraz Univ Technol Dept Elect Engn Shiraz Iran Radboud Univ Nijmegen Donders Inst Brain Cognit & Behav AI Dept Nijmegen Netherlands Western Sydney Univ MARCS Inst Int Ctr Neuromorph Syst Sydney Australia Univ Calif Santa Cruz Dept Elect Engn Santa Cruz CA USA

The mimicry of the biological brain's structure in information processing enables spiking neural networks (SNNs) to exhibit significantly reduced power consumption compared to conventional systems. Consequently, these networks have garnered heightened attention and spurred extensive research endeavors in recent years, proposing various structures to achieve low power consumption, high speed, and improved recognition ability. However, researchers are still in the early stages of developing more efficient neural networks that more closely resemble the biological brain. This development and research require suitable hardware for execution with appropriate capabilities, and field-programmable gate array (FPGA) serves as a highly qualified candidate compared to existing hardware such as central processing unit (CPU) and graphics processing unit (GPU). FPGA, with parallel processing capabilities similar to the brain, lower latency and power consumption, and higher throughput, is highly eligible hardware for assisting in the development of spiking neural networks. In this review, an attempt has been made to facilitate researchers' path to further develop this field by collecting and examining recent works and the challenges that hinder the implementation of these networks on FPGA.

关键词： Spiking neural network Neuromorphic computing field-programmable gate array Brain-inspired computing Accelerator

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DyRecMul: Fast and Low-Cost Approximate Multiplier for FPGAs using Dynamic Reconfiguration

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2025年第1期18卷 1-22页

作者： Vakili, Shervin Vaziri, Mobin Zarei, Amirhossein Langlois, J. M. Pierre Inst Natl Rech Sci Energie Mat Telecommun Ctr Montreal PQ Canada Polytech Montreal Montreal PQ Canada

Multipliers are widely-used arithmetic operators in digital signal processing and machine learning ( ML ) circuits. Due to their relatively high complexity, they can have high latency and be a significant source of power consumption. One strategy to alleviate these limitations is to use approximate computing. This article thus introduces an original FPGA-based approximate multiplier specifically optimized for ML computations. It utilizes dynamically reconfigurable lookup table (LUT) primitives in AMD-Xilinx technology to realize the core part of the computations. The article provides an in-depth analysis of the hardware architecture, implementation outcomes, and accuracy evaluations of the multiplier proposed in INT8 precision. The article also facilitates the generalization of the proposed approximate multiplier idea to other datatypes, providing analysis and estimations for hardware cost and accuracy as a function of multiplier parameters. Implementation results on an AMD-Xilinx Kintex Ultrascale+ FPGA demonstrate remarkable savings of 64% and 67% in LUT utilization for signed multiplication and multiply-and-accumulation configurations, respectively when compared to the standard Xilinx multiplier core. Accuracy measurements on four popular deep learning (DL) benchmarks indicate a minimal average accuracy decrease of less than 0.29% during post-training deployment, with the maximum reduction staying less than 0.33%. The source code of this work is available on GitHub.

关键词： Approximate multiplier field-programmable gate array dynamic reconiguration artificial intelligence hardware

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Laser Linewidth Measurement Using an FPGA-Based Delay Self-Homodyne System

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PHOTONICS 2025年第3期12卷 203-203页

作者： Bu, Fanqi Zhao, Zhongan Li, Longfei Zhang, Cunwei Li, Tie Qi, Yaoyao Ding, Jie Yan, Bingzheng Zhao, Chen Wang, Yulei Lu, Zhiwei Ding, Yu Bai, Zhenxu Hebei Univ Technol Ctr Adv Laser Technol Tianjin 300401 Peoples R China Hebei Key Lab Adv Laser Technol & Equipment Tianjin 300401 Peoples R China Natl Key Lab Electromagnet Space Secur Tianjin 300401 Peoples R China

Narrow-linewidth lasers play a crucial role in nonlinear optics, atomic physics, optical metrology, and high-speed coherent optical communications. Precise linewidth measurement is essential for assessing laser noise characteristics;however, conventional methods are often bulky, costly, and unsuitable for integrated applications. This paper presents a compact and cost-effective delay self-homodyne system for laser linewidth measurement, leveraging a field-programmable gate array (FPGA)-based data acquisition circuit. By employing fast Fourier transform (FFT) analysis, the system achieves high-precision linewidth measurement in the kHz range. Additionally, by optimizing the fiber length, the system effectively suppresses low-frequency and 1/f noise, providing an integrated and efficient solution for advanced laser characterization with enhanced performance and reduced cost.

关键词： narrow linewidth delay self-homodyne field-programmable gate array fast Fourier transform 1/f noise

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Optimized theory-guided convolutional neural network for lung cancer classification using CT images with advanced FPGA implementation

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BIOMEDICAL SIGNAL PROCESSING AND CONTROL 2025年 106卷

作者： Manikandan, S. Karthigaikumar, P. Karpagam Coll Engn Dept Elect & Telecommun Engn Coimbatore Tamil Nadu India Karpagam Coll Engn Dept Elect & Commun Engn Coimbatore Tamil Nadu India

Lung carcinoma, commonly referred to as lung cancer is a severe disease with higher global mortality rate. The uncontrolled growth of cells in lung tissues is the reason for it. Detecting and treating lung cancer early is important for curing it, and diagnostic methods commonly include Computed Tomography (CT) scans and blood tests. However, accurately detecting and classifying pulmonary nodules in CT images remains a challenge due to the complexity of the data, higher computational demands,require for real-time processing. Existing systems often face limitations, such as high power consumption, prolonged processing times, and scalability issues, reducing their effectiveness in clinical environments. To overcome these challenges, this manuscript proposes an Optimized Theory-Guided Convolutional Neural Network for Lung Cancer Classification utilizing CT Images with Advanced FPGA Implementation (OTCNN-LCT-FPGA). Computed Tomography Image (CTI) from the LIDC-IDRI dataset are pre-processed using Variational Bayesian Robust Adaptive Filtering (VBRAF) technique, which removes noise and converts RGB images into binary format. The pre-processed images are classified as benign or malignant using Theory-Guided Convolutional Neural Network (TCNN). The Polar Coordinate Bald Eagle Search Algorithm (PBESA) is introduced to enhance the weight parameters of TCNN method while reducing resource utilization and increasing processing speed. The TCNN classifier is executed on field-programmable gate array (FPGA) to further decrease the computation time. The proposed OTCNN-LCT-FPGA method demonstrates significant improvements. How if, it achieves 6.26 %, 7.22 %, and 5.27 higher specificity and 2.96 %, 3.46 %, and 5.80 % higher F1-Score when compared to the existing methods, such as FCFNN-LCC, ISNeT-DLC-CT and DNNLCC-EOS respectively.

关键词： CT images field-programmable gate array Lung cancer Variational based Bayesian robust Adaptive Filtering Polar Coordinate Bald Eagle Search Algorithm Theory-guided Convolutional Neural Network

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Research on Spaceborne Neural Network Accelerator and Its Fault Tolerance Design

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REMOTE SENSING 2025年第1期17卷 69-69页

作者： Shao, Yingzhao Wang, Junyi Han, Xiaodong Li, Yunsong Li, Yaolin Tao, Zhanpeng Xidian Univ State Key Lab Integrated Serv Networks Xian 710071 Peoples R China China Acad Space Technol Xian Xian 710100 Peoples R China Xidian Univ Sch Comp Sci & Technol Xian 710071 Peoples R China

To meet the high-reliability requirements of real-time on-orbit tasks, this paper proposes a fault-tolerant reinforcement design method for spaceborne intelligent processing algorithms based on convolutional neural networks (CNNs). This method is built on a CNN accelerator using field-programmable gate array (FPGA) technology, analyzing the impact of Single-Event Upsets (SEUs) on neural network computation. The accelerator design integrates data validation, Triple Modular Redundancy (TMR), and other techniques, optimizing a partial fault-tolerant architecture based on SEU sensitivity. This fault-tolerant architecture analyzes the hardware accelerator, parameter storage, and actual computation, employing data validation to reinforce model parameters and spatial and temporal TMR to reinforce accelerator computations. Using the ResNet18 model, fault tolerance performance tests were conducted by simulating SEUs. Compared to the prototype network, this fault-tolerant design method increases tolerance to SEU error accumulation by five times while increasing resource consumption by less than 15%, making it more suitable for spaceborne on-orbit applications than traditional fault-tolerant design approaches.

关键词： spaceborne computing single-event upset convolutional neural network field-programmable gate array fault-tolerant design

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High-speed and reduced energy delay product TCAM on FPGA for network routers

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ETRI JOURNAL 2025年第0期

作者： Vadivel, Sridhar Raj Sankara Ramapackiam, Shantha Selvakumari Mepco Schlenk Engn Coll Dept Elect & Commun Engn Sivakasi India

Ternary content-addressable memory (TCAM) is widely used in the design of high-speed search engines such as network routers and artificial-intelligence-based applications. However, traditional TCAM designs suffer from two major drawbacks. Static random access memory (RAM)-based TCAMs do one operation at a time, causing the search operation to be suspended while the update operation is in progress, rendering them unsuitable for applications with high-frequency updates. Moreover, during the implementation of wider TCAMs, when the match results are transferred from one slice to another, the last look-up table (LUT) in the slice is always set to logic one, which results in resource wastages. This research aims to overcome the problems associated with traditional TCAM design. The proposed work used six-input (RAM64X1S) LUTs in field-programmable gate arrays by allowing both search and update operations to be performed simultaneously during the data update in a particular LUT. To overcome resource wastage, the proposed design used four RAM64X1S blocks instead of RAM64M blocks. Moreover, the proposed TCAM architecture was considerably simpler, comprising LUTs with AND slicing, thus reducing FPGA resources such as slice registers and slice logic. For TCAM sizes of 512 x 36 and 1024 x 144, the slice utilization was reduced by 17% and 29%, respectively, with their speed being increased by 17% and 26%, respectively. Moreover, the lookup rate and the update rate of the designed TCAMs also improved considerably. The proposed architecture employed high-speed single-cycle searches, making it ideal for fast search applications.

关键词： data compression field-programmable gate array routers static random-access memory ternary content-addressable memory translation lookaside buffers

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Development of a proof-of-principle PET system using multi-time-over-threshold and FPGA without ADC or TDC

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NUCLEAR ENGINEERING AND TECHNOLOGY 2025年第5期57卷

作者： Kim, Kyu Bom Kim, Kyuseok Jeong, Hyun-Woo Kim, Yeonkyeong Lee, Su Hwan Yonsei Univ Coll Hlth Sci Dept Radiat Convergence Engn Wonju South Korea Eulji Univ Dept Biomed Engn Songnam South Korea Yonsei Univ Severance Hosp Dept Internal Med Div Pulm & Crit Care MedColl Med Seoul South Korea 2TS Corp 211 Hwarang Ro Seoul 08393 South Korea

The goal of this study was to extend a multi-time-over-threshold (MToT) based multi-channel front-end circuit and field-programmable gate array only data acquisition (DAQ) without analog-to-digital converter or time-todigital converter for the development of a proof-of-principle positron emission tomography (PET) system. The proposed system was configured with two detector modules, each having a 4 x 2 detector block (128 ch/detector module). The performance of the PET system using a 256-channel analog circuit and a DAQ system was evaluated by measuring energy resolution and time resolution. These values were 20 % and 1.5 ns, respectively. The calculated data packet containing energy, time, and position information was formed into 64-bit single event data package and sent to the host computer using USB 3.0 control interface. Experiment results revealed that the spatial resolution was 2.1 mm at the center and 2.2 mm at 20 mm from the center. The Derenzo Phantom based experiment showed sufficient distinguish for Hod-rod of various radius, confirming the viability of the proposed proof-of-principle system.

关键词： Multi-time-over-threshold method field-programmable gate array Analog and digital signal processing Positron emission tomography Proof-of-principle system

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Software and hardware synergy for accelerated plant disease identification

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APPLIED SOFT COMPUTING 2025年 174卷

作者： Wen, Hongxing Li, Chuandong Wang, Xinpei Chen, Ling Southwest Univ Coll Elect Informat & Engn Chongqing Key Lab Nonlinear Circuits & Intelligent Chongqing 400715 Peoples R China

Plant diseases are one of the main causes of reduced crop yields. Therefore, it is necessary to adopt timely and effective identification methods and take corresponding measures. Some physical and biological detection methods have been proposed by researchers, but these methods require specialized techniques and expensive detection costs. Furthermore, the limited number of skilled technicians means that disease identification is not always timely or effective. To achieve real-time identification of plant diseases in remote areas where network and circuit are not well connected, We adopted a hardware and software co-acceleration approach to implement the design. First, we designed a lightweight convolutional neural network (CNN) and trained this network using a knowledge distillation approach. Then, we quantified the model parameters into int8 type using a method of model quantization to further compress the model size. After compression, the model size of the network is 0.035 MB and the recognition accuracy is 94.06% on the test set of the experiment. In order to deploy the proposed network on resource constrained field-programmable gate array (FPGA) devices, we used time-division multiplexing and feature map segmentation to deploy the network. Finally, our design is implemented on ZYNQ7020 with an inference speed of 35.73ms/frame and a power consumption of 1.97 W. The experimental results show that our design has the advantages of consuming less FPGA resources, low power consumption, high speed and portability. It can be used for disease recognition in multiple plant classes.

关键词： Convolutional neural network field-programmable gate array Acceleration Plant disease

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