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Proceedings of the 2023 ACM/SIGDA International Symposium on field programmable gate arrays

作者： Ruiqi Chen Haoyang Zhang Yuhanxiao Ma Enhao Tang Shun Li Yanxiang Zhu Jun Yu Kun Wang Fudan University Shanghai China New York University New York NY USA Fuzhou University Fuzhou China VeriMake Innovation Lab Nanjing China

ISBN: (纸本)9781450394178

Graph Neural Networks (GNNs) have outstanding performance on graph-structured data and have been extensively accelerated by field-programmable gate array (FPGA) in various ways. However, existing accelerators significantly lack flexibility, especially in the following two aspects: 1) Many FPGA-based accelerators only support one GNN model. 2) The processes of re-synthesizing and bitstream re-generating are very time-consuming for new GNN models. To this end, we propose a highly integrated FPGA-based overlay processor for general GNN accelerations named Graph-OPU. Regarding the data structure and operation irregularity, we customize the instruction sets to support irregular operation patterns in the inference process of GNN models. Then, we customize our datapath and optimize the data format in the microarchitecture to take full advantage of high bandwidth memory (HBM). Moreover, we design the computation module to ensure a unified and fully-pipelined process of sparse matrix multiplication (SpMM) and general matrix multiplication (GEMM). Users can avoid the process of FPGA reconfiguration or RTL regeneration for the newly invented GNN models. We implement the hardware prototype on Xilinx Alveo U50 and test the mainstream GNN models with 9 datasets. Graph-OPU can achieve an average of 435× and 18× speedup, while 2013× and 109× better energy efficiency, compared with the Intel I7-12700KF processor and NVIDIA RTX3090 GPU, respectively. To the best of our knowledge, Graph-OPU is the first in-depth study on FPGA-based general processors for GNN acceleration with high speedup and energy efficiency.

关键词： high bandwidth memory graph neural network field-programmable gate array overlay processor

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DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only) 18

DATuner: An Extensible Distributed Autotuning Framework for ...

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Proceedings of the 2018 ACM/SIGDA International Symposium on field-programmable gate arrays

作者： Gai Liu Ecenur Ustun Shaojie Xiang Chang Xu Guojie Luo Zhiru Zhang Cornell University Ithaca NY USA IBM Research China Beijing China Peking University Beijing China

ISBN: (纸本)9781450356145

Mainstream FPGA tools contain an extensive set of user-controlled compilation options and internal optimization strategies that significantly impact the design quality. These compilation and optimization parameters create a complex design space that human designers may not be able to effectively explore in a time-efficient manner. In this work we describe DATuner, an open-source extensible distributed autotuning framework for optimizing FPGA designs and design automation tools using an ensemble of search techniques managed by multi-armed bandit algorithms. DATuner is designed for a distributed environment that uses parallel searches to amortize the significant runtime overhead of the CAD tools. DATuner provides convenient interface for extension to user-supplied tools, which enables the end users to apply DATuner to design tools/flows of their interest. We demonstrate the effectiveness and extensibility of DATuner using three case studies, which include clock frequency optimization for FPGA compilation, fixed-point optimization, and autotuning logic synthesis transformations.

关键词： field-programmable gate array design automation distributed autotuning

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Design of Vehicle License Plate Positioning System Based on FPGA

Design of Vehicle License Plate Positioning System Based on ...

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第37届中国控制会议

作者： Yandong Jia Chunyang Wang Jilin Province Advanced Control Technology and Intelligent Automation Equipment Research Engineering Lab Changchun University of Science and Technology

Traditional License Plate Positioning(LPP) systems always utilize complex structures, resulting in low processing speed. In this paper, we propose an identification system for vehicle license plates based on field-programmable gate array(FPGA). The improved Sobel edge detection algorithm is applied to conduct image preprocessing, and the watershed algorithm is used to identify the plates. This leads to a simplified system structure and a higher speed for the plates identification. This system uses a camera to collect image information, the FPGA to conduct image reception and processing, and a monitor to display the identification results. After debugging and executing, the design is proved to be of high performance, and is capable of applying to practical engineering projects.

关键词： License Plate Positioning field-programmable gate array image preprocessing

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Extending High-Level Synthesis for Task-Parallel Programs 21

Extending High-Level Synthesis for Task-Parallel Programs

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The 2021 ACM/SIGDA International Symposium on field-programmable gate arrays

作者： Yuze Chi Licheng Guo Young-kyu Choi Jie Wang Jason Cong University of California Los Angeles Los Angeles CA USA

ISBN: (纸本)9781450382182

C/C++/OpenCL-based high-level synthesis (HLS) becomes more and more popular for field-programmable gate array (FPGA) accelerators in many application domains in recent years, thanks to its competitive quality of result (QoR) and short development cycle compared with the traditional register-transfer level (RTL) design approach. Yet, limited by the sequential C semantics, it remains challenging to adopt the same highly productive high-level programming approach in many other application domains, where coarse-grained tasks run in parallel and communicate with each other at a fine-grained level. While current HLS tools support task-parallel programs, the productivity is greatly limited in the code development, correctness verification, and QoR tuning cycles, due to the poor programmability, restricted software simulation, and slow code generation, respectively. Such limited productivity often defeats the purpose of HLS and hinder programmers from adopting HLS for task-parallel FPGA *** this paper, we extend the HLS C++ language and present a fully automated framework with programmer-friendly interfaces, universal software simulation, and fast code generation to overcome these limitations. Experimental results based on a wide range of real-world task-parallel programs show that, on average, the lines of kernel and host code are reduced by 22% and 51%, respectively, which considerably improves the programmability. The correctness verification and the iterative QoR tuning cycles are both greatly accelerated by 3.2× and 6.8×, respectively.

关键词： high-level synthesis task-parallel program field-programmable gate array

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Elimination of the Background of Electron Microscope Images by Using FPGA

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ACTA CYBERNETICA 2013年第1期21卷 123-134页

作者： Fazekas, Adam Daimon, Hiroshi Matsuda, Hiroyuki Toth, Ladszlo Univ Debrecen Fac Informat Dept Informat Syst & Networks Kassai Ut 26 H-4028 Debrecen Hungary Nara Inst Sci & Technol Ikoma Nara 6300192 Japan

The purpose of our development is to design an FPGA based hardware acceleration system that is able to be used for analyzing photoemission electron microscope (PEEM) images or improving their quality. Even though a usual PEEM has an energy filter unit, which is able to eliminate certain disturbing signals, a post processing computation can also be useful to improve the image quality. Here we propose an FPGA based hardware acceleration system for the computation of a certain image background component. It has uniquely designed hardware modules that perform the computations in parallel, resulting in less calculation time. The system shown here is a prototype which was only used for testing and experimental purposes.

关键词： photoelectron spectra Shirley background field-programmable gate array hardware acceleration

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Emerging application domains: research challenges and opportunities for FPGAs 09

Emerging application domains: research challenges and opport...

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Proceedings of the ACM/SIGDA international symposium on field programmable gate arrays

作者： Jason H. Anderson University of Toronto Toronto ON Canada

ISBN: (纸本)9781605584102

Communications infrastructure, data processing and industrial electronics are the cornerstone application areas for programmable logic today. But what are the application domains of tomorrow? What nascent application areas could explode the growth of programmable logic usage and expand the programmable market? In this workshop, we will hear speakers from industry and academia talk about the emerging application areas for FPGAs and the challenges and opportunities in these areas. We will consider how programmable hardware and the associated tools should be enhanced to become better-suited to tomorrow's applications. The overarching aim of the workshop is to seed ideas in the research community by giving an applications perspective of the fertile topics for future research on FPGA architecture, CAD and applications.

关键词： high-performance computing field-programmable gate array applications performance power fpga reconfigurable computing

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ACPU-FPGAheterogeneous approach for biological sequence comparison using high-level synthesis

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2021年第4期33卷 e6007-e6007页

作者： Jorge, Carlos A. C. Nery, Alexandre S. Melo, Alba C. M. A. Goldman, Alfredo Univ Brasilia Dept Comp Sci Brasilia DF Brazil Univ Brasilia Dept Elect Engn Brasilia DF Brazil Univ Sao Paulo Inst Math & Stat Sao Paulo Brazil

This article presents a high-level synthesis implementation of the longest common subsequence (LCS) algorithm combined with a weighted-based scheduler for comparing biological sequences prioritizing energy consumption or execution time. The LCS algorithm has been thoroughly tailored using Vivado High-Level Synthesis tool, which is able to synthesize register transfer level (RTL) from high-level language descriptions, such as C/C++. Performance and energy consumption results were obtained with a CPU Intel Core i7-3770 CPU and an Alpha-Data ADM-PCIE-KU3 board that has a Xilinx Kintex UltraScale XCKU060 FPGA chip. We executed a batch of 20 comparisons of sequences on 10k, 20k, and 50k sizes. Our experiments showed that the energy consumption on the combined approach was significantly lower when compared to the CPU, achieving 75% energy reduction on 50k comparisons. We also used the tool proposed in this article to do a case study on Covid-19, with real SARS-CoV-2 sequences, comparing their LCS scores.

关键词： biological sequence comparison dynamic programming field-programmable gate array high-level synthesis longest common subsequence

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Design of Handheld Oscilloscope Based on FPGA and Dual A/D

Design of Handheld Oscilloscope Based on FPGA and Dual A/D

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2016 4th International Conference on Electrical&Electronics Engineering and Computer Science(ICEEECS 2016)

作者： Hu Yang Yuduo Wang School of Information & Communication Engineering Beijing Information Science & Technology Univerdity

ISBN: (纸本)9781510835429

Handheld oscilloscope because of its portability, wide application range and other characteristics, has drawn more and more attention in the engineering practice. Anolog-todigital conversion circuit plays an important role in the design of digital oscilloscope. It directly determines the maximum frequency of digital oscilloscope can be measured. This paper focuses on the analysis of three methods of improving the sampling rate, eventually adopts double anolog-to-digital converter sampling approach to the design of a handheld oscilloscope, sampling frequency can reach two times the maximum sampling frequency of anolog-to-digital converter, so as to improve the accuracy of frequency measurement range of oscilloscope and the waveform display, and without significant increase in cost and easy to realize. The oscilloscope with embedded processor STM32 as control core, using field-programmable gate array(FPGA) for data processing. The signal collected by automatic gain control, dual anolog-digital converter sampling,data cache, digitalto-anolog conversion process, displayed on the screen. At the same time,the oscilloscope realizes the functions of test signal's display, measurement and the corresponding parameter adjustment.

关键词： Handheld oscilloscope field-programmable gate array STM32 Double Anologto-Digital sampling Sampling frequency

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Transmission of Subcarrier Square Wave in Radio over Fiber Communication System Based on FPGA

Transmission of Subcarrier Square Wave in Radio over Fiber C...

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作者： Mao Xinrong Wang Leyi Kou Zhaofei Chen Rong Xi'an University of Science & Technology

To avoid the disadvantages of Radio over Fiber(RoF) communication system in optical domain modulation,subcarrier modulation in electrical domain using fieldprogrammable gate array(FPGA) is proposed to generate baseband subcarrier square *** the subcarrier signal is modulated to optical signal using optical fiber experimental box,which can be transmitted through optical *** waveform of the original square wave can be observed on the oscilloscope after the transmission through the optical fiber system with good *** experimental results show that subcarrier modulation can be done in electrical domain,which prove the feasibility of subcarrier modulation in the electrical domain using FPGA,and providing another way of subcarrier modulation.

关键词： Radio over Fiber Subcarrier Modulation Square Wave field-programmable gate array

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Design of a Multichannel Time Interval Measurement Interface Box

Design of a Multichannel Time Interval Measurement Interface...

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作者： Don, M. L Pugh, K. E Kline, B. J Hallameyer, J. M CCDC Army Research Laboratory Aberdeen Proving Ground United States

Precise time interval measurement is required for a number of applications including clock stability analysis, time-of-flight measurements, and particle physics. Commercial time interval measurement devices can achieve picosecond resolution but are expensive, especially for multichannel applications. In previous research, the US Army Combat Capabilities Development Command Army Research Laboratory demonstrated 10-ns resolution on 10 channels using a low-cost field-programmable gate array (FPGA) suitable for pulse-per-second monitoring. This technical note details the design of an interface box for this FPGA device, enabling practical time interval measurement with a variety of input signals. The purpose of this note is twofold: 1) to document the interface box to allow for easy use and future modifications and 2) to provide a reference to facilitate the construction of other interface units, including design advice and lessons learned.

关键词： field programmable gate array Time intervals Measurement Monitoring Time interval measurement field-programmable gate array Pulse per second Test and measurement Electronic interface

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