As silicon photomultiplier (SiPM)-based time-of-flight (TOF) positron emission tomography (PET) becomes popular, the need for sophisticated PET data acquisition (DAQ) systems is increasing. One promising solution to t...
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As silicon photomultiplier (SiPM)-based time-of-flight (TOF) positron emission tomography (PET) becomes popular, the need for sophisticated PET data acquisition (DAQ) systems is increasing. One promising solution to this challenge is the adoption of a field-programmable gate array (FPGA)-only signal digitization method. In this paper, we propose a new approach to efficiently implement an FPGA-only digitizer. We configured the input/output (IO) port of the FPGA to function as a dual-threshold voltage comparator through the use of simple passive circuitry and heterogeneous IO standards. This configuration overcomes the limitations of existing methods by allowing different threshold voltages for adjacent IO pins, effectively reducing routing complexity and lowering manufacturing costs. An FPGA-only digitizer was implemented by integrating the dual-threshold voltage comparator and FPGA-based time-to-digital converter. By combining the dual-threshold time-over-threshold (TOT) method and curve fitting, precise energy information could be obtained. The performance of the FPGA-only digitizer was assessed using a detector setup comprising a 3 x 3 x 20 mm3 LYSO scintillation crystal and a single pixel SiPM. Using the configured evaluation setup, an energy resolution of 12.5% and a time resolution of 146 +/- 9 ps were achieved for a 20 mm scintillation crystal. The dual-threshold TOT implemented using the proposed method showed consistent linearity across an energy range of 100 keV to 600 keV. The proposed method is well-suited for the development of cost-effective DAQ systems in highly integrated TOF PET systems.
This article investigates the design and control of the parallel-hybrid converter (PHC), which consists of parallel connection of a silicon insulated gate bipolar transistor (IGBT) bridge and a partially rated silicon...
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This article investigates the design and control of the parallel-hybrid converter (PHC), which consists of parallel connection of a silicon insulated gate bipolar transistor (IGBT) bridge and a partially rated silicon carbide (SiC) MOSFETs bridge with a shared dc bus. The IGBT bridge processes the bulk of the power, while switching at a low frequency to maximize efficiency, while the SiC MOSFETs bridge's lower relative switching loss is exploited to filter low-order harmonics from the IGBT bridge. A finite-set model predictive controller is detailed that allows IGBT switching frequencies down to 1 kHz to be achieved while also tightly controlling the magnitude of current in the SiC bridge. A genetic algorithm is utilized to automatically tune the control and investigate the design of the output filter as well as the influence of the controller time-step and horizon length on the performance. Power loss estimates of a 1.5MWapplication case are made showing potential for significant power-loss reductions. Experimental tests validate an field-programmable gate array (FPGA) implementation of the controller and topologies performance, with IGBT bridge frequencies below 1.2 kHz and grid-current total harmonic distortion below 3% achieved. The ability of converter to switch operation between a high-current and a low-current mode and dynamic performance is also verified.
Human activity recognition (HAR) technology is related to human safety and convenience, making it crucial for it to infer human activity accurately. Furthermore, it must consume low power at all times when detecting h...
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Human activity recognition (HAR) technology is related to human safety and convenience, making it crucial for it to infer human activity accurately. Furthermore, it must consume low power at all times when detecting human activity and be inexpensive to operate. For this purpose, a low-power and lightweight design of the HAR system is essential. In this paper, we propose a low-power and lightweight HAR system using point-cloud data collected by radar. The proposed HAR system uses a pillar feature encoder that converts 3D point-cloud data into a 2D image and a classification network based on depth-wise separable convolution for lightweighting. The proposed classification network achieved an accuracy of 95.54%, with 25.77 M multiply-accumulate operations and 22.28 K network parameters implemented in a 32 bit floating-point format. This network achieved 94.79% accuracy with 4 bit quantization, which reduced memory usage to 12.5% compared to existing 32 bit format networks. In addition, we implemented a lightweight HAR system optimized for low-power design on a heterogeneous computing platform, a Zynq UltraScale+ ZCU104 device, through hardware-software implementation. It took 2.43 ms of execution time to perform one frame of HAR on the device and the system consumed 3.479 W of power when running.
In this work, we implemented a short-reach real-time optical communication system using MLP for pre-distortion. Lookup table (LUT) algorithms are commonly employed for pre-distortion in intensity modulation and direct...
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In this work, we implemented a short-reach real-time optical communication system using MLP for pre-distortion. Lookup table (LUT) algorithms are commonly employed for pre-distortion in intensity modulation and direct detection (IM/DD) systems. However, storage limitations typically restrict the LUT pattern length to 9, limiting its effectiveness in compensating for nonlinear effects. A multilayer perceptron (MLP) can overcome this limitation by predicting errors and generating pre-distorted signals, thus replacing the extensive storage requirements of LUTs with minimal computational resources. The MLP-based digital pre-distortion (MLP-DPD) technique enables the creation of long-pattern LUTs for improved nonlinear compensation. In this work, an MLP-DPD scheme was implemented on a field-programmable gate array (FPGA). The FPGA was used to generate a 14.7456 GBaud pre-distorted pulse amplitude modulation 4-level (PAM4) signal. This signal was then transmitted over 20 km of standard single-mode fiber (SSMF). At the receiver, the parallel constant modulus algorithm (PCMA) was applied for signal processing. The bit error rate (BER) achieved met the 2.4 x 10-2 threshold for soft-decision forward error correction (SD-FEC), enabling a net transmission bit rate of 24.576 Gbit/s. This approach demonstrates the feasibility of using MLP-DPD for effective nonlinear compensation in high-speed optical communication systems with limited resources.
In this paper, a comparative study is conducted on two nonlinear control techniques: state feedback control through backstepping and computed torque control. The study focuses on their application to the industrial ro...
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In this paper, a comparative study is conducted on two nonlinear control techniques: state feedback control through backstepping and computed torque control. The study focuses on their application to the industrial robot PUMA 560. The primary goal is to assess the trajectory tracking accuracy and speed achieved by these methods. To achieve this objective, both control techniques are employed on the Zed board Zynq FPGA platform, encompassing both simulation and hardware systems. Subsequently, the experimental results are thoroughly analysed and compared, aiming to accentuate the unique advantages and constraints associated with each method.
A fundamental aspect in the evolution of Time-to-Digital Converters (TDCs) implemented within field-programmable gate arrays (FPGAs), given the increasing demand for detection channels, is the optimization of resource...
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A fundamental aspect in the evolution of Time-to-Digital Converters (TDCs) implemented within field-programmable gate arrays (FPGAs), given the increasing demand for detection channels, is the optimization of resource utilization. This study reviews the principal methodologies employed for implementing low-resource TDCs in FPGAs. It outlines the foundational architectures and interpolation techniques utilized to bolster TDC performances without unduly burdening resource consumption. Low-resource Tapped Delay Line, Vernier Ring Oscillator, and Multi-Phase Shift Counter TDCs, including the use of SerDes, are reviewed. Additionally, novel low-resource architectures are scrutinized, including Counter Gray Oscillator TDCs and interpolation expansions using Process-Voltage-Temperature stable IODELAYs. Furthermore, the advantages and limitations of each approach are critically assessed, with particular emphasis on resolution, precision, non-linearities, and especially resource utilization. A comprehensive summary table encapsulating existing works on low-resource TDCs is provided, offering a comprehensive overview of the advancements in the field.
In the radiation work environment of nuclear power plants and similar facilities, radiation can induce Single Event Upsets (SEUs) and even Multiple Bit Upsets (MBUs) in field-programmable gate arrays (FPGAs) and relat...
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In the radiation work environment of nuclear power plants and similar facilities, radiation can induce Single Event Upsets (SEUs) and even Multiple Bit Upsets (MBUs) in field-programmable gate arrays (FPGAs) and related devices. The hardware reinforcement techniques for FPGAs have strict material requirements and high costs, making implementation challenging. In contrast, FPGA software reinforcement techniques utilize error control coding to strengthen FPGA memory and combine with FPGA dynamic reconfiguration technology to reinforce the encoding and decoding modules. In this study, a BRAM fault injection experimental system is designed using Vivado to compare the reinforcement measures such as Hamming code, interleaved Hamming code, interleaved cyclic code, BCH code, and triple modular redundancy. Mathematical methods are employed to calculate their reliability performance indicators. The conclusion is that BCH (31,16,3) code exhibits the highest reliability, consumes the most resources, and can correct all errors of three bits or fewer. On the other hand, matrix interleaved code (28,16) can address the majority of MBUs, correcting all burst errors of four bits or fewer and some sporadic errors while utilizing relatively fewer resources.
Tight integration between classical and quantum networking requires strict synchronization of events between the classical and quantum portions of the network. Time-Sensitive Networking (TSN) as defined by IEEE 802.1Q...
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Tight integration between classical and quantum networking requires strict synchronization of events between the classical and quantum portions of the network. Time-Sensitive Networking (TSN) as defined by IEEE 802.1Q is limited to accuracy on the order of microseconds due to limitations in time synchronization performance;TSN gate control is thus similarly limited. This work presents a new High-Precision TSN that enables greater accuracy and resolution toward sub-nanosecond TSN gate control and can directly support entanglement distribution, a key component in a software-designed quantum network architecture where classical control can reach deep into the quantum network and directly control time critical operations.
A spiking neural network of ergodic sequential logic neuron models is presented. It is shown that the presented network is capable of reproducing various biologically plausible spatio-temporal phenomena (e.g., basic s...
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A spiking neural network of ergodic sequential logic neuron models is presented. It is shown that the presented network is capable of reproducing various biologically plausible spatio-temporal phenomena (e.g., basic synchronization and complicated chimera phenomenon) observed in the brain. Moreover, it is revealed that the presented network is able to operate with lower power compared to a standard digital -processor -based spiking neural network. It is then discussed that the presented network will be a useful building block in a brain prosthetic device.
In December 2021, we presented a prototype of a fast ionosonde for vertical sounding based on the usage of publicly available radio-electronic components. This approach led to a major reduction in the cost of the crea...
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In December 2021, we presented a prototype of a fast ionosonde for vertical sounding based on the usage of publicly available radio-electronic components. This approach led to a major reduction in the cost of the created device. We called our development ION-FAST, which characterizes the key feature of the ionosonde: the possibility of continuous operation at a speed of one ionogram per second, which is required to study the rapid processes of redistribution of the electron concentration during heating experiments. In May 2022, an ionosonde for vertical sounding of the ionosphere, developed at the Radiophysical Research Institute of Nizhni Novgorod (NIRFI), was put into continuous operation at the SURA facility. This report provides a description of the improvements made to the prototype over the last year and the path to be passed from idea to implementation. The results of the first months of the prototype's operation (especially the results of the supporting optic experiment in August 2022), as well as prospects for further use and modernization, are provided. In addition, the realization of the oblique chirp-sounding receiver prototype as an extension of the proposed diagnostic platform's functionality, including the first results, is presented.
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