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Design methodology of digital sensors for detecting laser fault injection attacks in FPGAs

Journal of Cryptographic Engineering 2025年第2期15卷 1-16页

作者： Hayashi, Shungo Sakamoto, Junichi Matsumoto, Tsutomu Cyber Physical Security Research Institute National Institute of Advanced Industrial Science and Technology 2-3-26 Aomi Tokyo Koto-ku 135-0064 Japan Environment and Information Science Yokohama National University Tokiwadai 79-7 Kanagawa Hodogayaku Yokohama 240-8501 Japan

Laser fault injection (LFI) refers to a serious attack that modifies programs and data in embedded systems by introducing specific errors into a device in operation. As a countermeasure, in addition to duplication and optical sensors, the detection of LFIs using a sensor composed of digital circuits has recently been proposed. However, the research on the physical layout of these sensors is limited. In this work, we profile the laser irradiation position and its effect on the surrounding circuits by laser-scanning experiments on field-programmable gate arrays (FPGAs). Studies have shown that digital sensors with conventional designs have low-sensitivity areas with regard to LFIs. To improve LFI detection in FPGAs, we propose a design method for digital sensors and apply it to a ring oscillator (RO)-based digital sensor and a time-to-digital converter-based sensor. Experimental results show that the RO-based sensor based on the proposed method increased the area detecting LFI to about twice that of the conventional method, and detect 99.8% of the effective faults at the target register under protection. Furthermore, we extend the application of the RO-based sensor based on the proposed method to the protection of cryptographic circuits. The results of the laser-scanning experiment show that the proposed sensor detected 98.3% of the LFIs that caused effective faults in the cryptographic circuit. © The Author(s) 2025.

关键词： Digital sensor Fault injection attack field-programmable gate array Laser fault injection Ring oscillator Time-to-digital converter

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A Fast and Accurate Fault Tree Analysis Based on Stochastic Logic Implemented on field-programmable gate arrays

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IEEE TRANSACTIONS ON RELIABILITY 2013年第1期62卷 13-22页

作者： Aliee, Hananeh Zarandi, Hamid Reza Amirkabir Univ Technol Tehran Polytech Dept Comp Engn & Informat Technol Tehran 15914 Iran

This paper presents a method based on stochastic logic to analyse fault trees. This method supports both static and dynamic gates, and can be applied to any type of fault trees. In this paper, static and dynamic gates would be translated into stochastic logic templates, and a hardware implementation for each gate would be achieved. Based on these hardware templates, it is possible to implement the whole logic on a field-programmable gate array (FPGA). Utilizing the stochastic logic for implementing a given fault tree on FPGA, the analysis would outperform the following parameters compared to traditional methods: 1) Speed-up, 2) Simplicity, 3) Reliability, and 4) Accuracy. Experimental results illustrate that using stochastic logic for modeling fault trees results in fast convergence of Monte Carlo simulation. Moreover, on average, our FPGA approach takes 50% of the time required by previous emulation approaches. Simplicity is an additional advantage of the proposed approach, achieved because of simplicity behind stochastic logic. Also, the stochastic logic is more reliable compared to traditional logic because any faults like SEUs in stochastic logic have less impact on the whole results compared to traditional arithmetic logic. To evaluate the proposed technique, the analysis is performed on several standard benchmarks composed of static and dynamic gates. The results obtained using this approach agree with those obtained from an analytical approach, which proves that the method is an accurate tool for system reliability modeling.

关键词： Fault tree analysis field-programmable gate array single event upset static and dynamic gates stochastic logic

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Spaceborne synthetic aperture radar signal processing using field-programmable gate arrays

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JOURNAL OF APPLIED REMOTE SENSING 2018年第3期12卷

作者： Sugimoto, Yohei Ozawa, Satoru Inaba, Noriyasu Japan Aerosp Explorat Agcy Res & Dev Directorate Tsukuba Ibaraki Japan

Synthetic aperture radar (SAR) imagery requires image reproduction through the successive signal processing of received data before browsing images and extracting information. The received signal data records of ALOS-2/PALSAR-2 are stored in the onboard mission data storage and transmitted to the ground. To compensate for storage usage and transmission data capacity through the mission data communication network, the operation duty of PALSAR-2 is limited. This balance strongly relies on network availability. The observation operations of current spaceborne SAR systems are rigorously planned by simulating the mission data balance, given conflicting user demands. This problem should be solved so that we need not compromise the operations and potential of next-generation spaceborne SAR systems. One of the solutions is to compress the SAR data through onboard image reproduction and information extraction from the reproduced images. This is also beneficial for fast delivery of information products and event-driven observations by constellation. The Emergence Studio (Sohatsu kobo in Japanese) of the Japan Aerospace Exploration Agency has been developing evaluation models of the image processing system with the field-programmable gate array for onboard SAR image reproduction. The first model called the "Fast L1 Processor (FLIP)" can reproduce a 10-m resolution, single-look complex image (level 1.1) from ALOS/PALSAR raw signal data (level 1.0). FLIP processing speed at 200 MHz results in processing about five times faster than CPU-based computing at 3.7 GHz, corresponding to 50% real-time processing capability for ALOS/PALSAR. The FLIP'S image is almost identical to the image reproduced by 32-bit simulation in MATLAB. (C) 2018 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： synthetic aperture radar image reproduction onboard processing real-time processing field-programmable gate array

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Design and Xilinx Virtex-fieldprogrammable gate array for hardware in the loop of sensorless second-order sliding mode control and model reference adaptive system-sliding mode observer for direct torque control of induction motor drive

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PROCEEDINGS OF THE INSTITUTION OF MECHANICAL ENGINEERS PART I-JOURNAL OF SYSTEMS AND CONTROL ENGINEERING 2023年第5期237卷 839-869页

作者： Krim, Saber Mimouni, Mohamed Faouzi Univ Kairouan Higher Inst Appl Sci & Technol Kasserine Kairouan Tunisia Univ Monastir Natl Engn Sch Monastir Lab Automat Elect Syst & Environm Monastir Tunisia Univ Kairouan Higher Inst Appl Sci & Technol Kasserine Kairouan 3100 Tunisia

This article aims first to propose an improved space vector modulation-direct torque control in order to enhance the induction motor performance using: (1) a super-twisting controller and (2) a novel model reference adaptive system based on a sliding mode observer. Second, due to the complexity of the suggested control algorithm, this article deals also with a hardware implementation on a field-programmable gate array board. Indeed, the field-programmable gate array is mainly chosen to reduce the execution time, thanks to its parallel processing which significantly improves the quality of the control system by reducing the sampling period, and consequently the delays in the control loop. Besides, the super-twisting controller is proposed to enhance the speed regulation loop which is a second-order sliding mode control technique that uses a continuous control law to prevent the chattering phenomenon induced by the first-order sliding mode control technique. Moreover, the high performance control requires information about the rotor speed which can be obtained by a sensor. Generally, the use of the speed sensor increases the system cost and size, and reduces its system reliability. Therefore, a combination between a model reference adaptive system observer and a sliding mode observer is suggested for speed estimation and overcoming the sensitivity of the classical model reference adaptive system observer against uncertainties and stator resistance variations. The performance of the proposed space vector modulation-direct torque control-super-twisting controller with the model reference adaptive system-sliding mode observer algorithm of an induction motor is verified through simulation, hardware co-simulation and experimental validation utilizing a field-programmable gate array Virtex-5-ML507 board. The performance of the suggested sensorless control method is compared also with other recent published schemes.

关键词： field-programmable gate array Xilinx system generator hardware architecture induction motor super-twisting model reference adaptive system

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Loop Unrolling for Energy Efficiency in Low-Cost field-programmable gate arrays

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2019年第4期11卷 1–23页

作者： Dumpala, Naveen Kumar Patil, Shivukumar B. Holcomb, Daniel Tessier, Russell Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA

field-programmable gate arrays (FPGAs) are used for a wide variety of computations in low-cost embedded systems. Although these systems often have modest performance constraints, their energy consumption must typically be limited. Many FPGA applications employ repetitive loops that cannot be straightforwardly split into parallel computations. Performing a loop sequentially generally requires high-speed clocks that consume considerable clock power and sometimes require clock generation using a phase-locked loop (PLL). Loop unrolling addresses the high-speed clock issue, but its use often leads to significant combinational glitch power. In this work, a computer-aided design (CAD) approach that unrolls loops for designs targeted to low-cost FPGAs is described. Our approach considers latency constraints in an effort to minimize energy consumption for loop-based computation. To reduce glitch power, a glitch-filtering approach is introduced that provides a balance between glitch reduction and design performance. Glitch-filter enable signals are generated and routed to the filters using resources best suited to the target FPGA. Our approach automatically inserts glitch filters and associated control logic into a design prior to processing with FPGA synthesis, place, and route tools. Our energy-saving loop-unrolling approach has been evaluated using five benchmarks often used in low-cost FPGAs. The energy-saving capabilities of the approach have been evaluated for an Intel Cyclone IV and a Xilinx Artix-7 FPGA using board-level power measurement. The use of unrolling and glitch filtering is shown to reduce energy by at least 65% for an Artix-7 device and 50% for a Cyclone IV device while meeting design latency constraints.

关键词： field-programmable gate array loop unrolling energy

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Analysis of a Novel Non-Volatile Look-Up Table (NV LUT) Controller Design with Resistive Random-Access Memories (RRAM) for field-programmable gate arrays (FPGA)

Analysis of a Novel Non-Volatile Look-Up Table (NV LUT) Cont...

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IEEE Regional Symposium on Micro and Nanoelectronics (IEEE-RSM)

作者： Chee, Hock Leong Kumar, T. Nandha Almurib, Haider A. F. Kang, Desmond Wen Hui Univ Nottingham Dept Elect & Elect Engn Semenyih Selangor Malaysia

ISBN: (纸本)9781728104607

This paper studies the simulation results of a novel controller circuit design for non-volatile (NV) look-up tables (LUT) combined with an electrical model of a resistive random-access memory (RRAM)-an emerging non-volatile memory (NVM) device. The Write and Read schemes of the controller is tested for a 2x2 RRAM array. The selected RRAM successfully switches between low '0' and high '1' while the unselected the RRAM remain undisturbed, demonstrating the elimination of the intrinsic sneak-path current problem in RRAMs. Reading of a selected RRAM is also performed with agreeable results.

关键词： field-programmable gate array memristor non-volatile look-up table non-volatile memory resistive random-access memory resistive switching

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EFFICIENT DIGITAL IMPLEMENTATION OF SIGNAL PROCESSING ALGORITHMS IN STATE-OF-THE-ART field-programmable gate arrayS FOR GAMMA-RAY SPECTROSCOPY

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NUCLEAR TECHNOLOGY 2014年第1期187卷 69-81页

作者： Fahiman, Fateme Kafaee, Mahdi Moussavi-Zarandi, Alt Fahiman, Meisam Amirkabir Univ Technol Dept Energy Engn & Phys Tehran Iran Iran Univ Sci & Technol Dept Comp Engn Tehran Iran

In this work, a board based on a Spartan-3 field-programmable gate array was designed as a hardware prototyping platform for development of a multichannel digital gamma spectrometer. The device is compatible with various detectors like high-purity germanium, NaI, and CsI detectors. Before implementing the hardware, the method for digital signal processing for gamma spectroscopy was developed. The aim of this paper is to introduce a robust tool suitable for optimizing the design of complicated systems. The characteristics of this method, such as its ability to implement adaptive shaping, are investigated. The optimum conditions for digital filtering were determined using MATLAB/Simulink. This scheme can be useful for commercial production. Simulation was used to examine each processing unit in the whole signal processing procedure including cusplike shaping. The proposed method can be used as a computer design tool for optimizing digital multichannel analyzers or digital nuclear spectrometers.

关键词： digital pulse spectrometer system simulation field-programmable gate array

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Single and multiple precision sequential large multipliers for field-programmable gate arrays

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2016年第4期24卷 2961-2973页

作者： Senturk, Ali Gok, Mustafa Cukurova Univ Dept Comp Engn Adana Turkey Cukurova Univ Dept Elect Engn Adana Turkey

This paper presents single and multiple precision sequential large multiplier designs for field-programmable gate arrays. Both designs use the Karatsuba Ofman method. They are pipelined and can generate a full size (double operand size) or a single size product. The syntheses results show that the sequential large Karatsuba Ofman multiplier (SLKOM) implementations have up to 2.23 times less delay compared with the standard sequential large multipliers implementations presented in previous research. The 2048-bit multiple precision sequential Karatsuba Ofman large multiplier (MPSLKOM) implementation can simultaneously execute eight 256-bit multiplications. The MPSLKOM implementations use roughly 1% more registers and up to 3% more LUTs than the SLKOM implementations.

关键词： Large multipliers Karatsuba-Ofman field-programmable gate array

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Design and development of multi-channel front end electronics based on dual-polarity charge-to-digital converter for SiPM detector applications

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Nuclear Science and Techniques 2023年第2期34卷 1-12页

作者： Yu‑Ying Li Chang‑Yu Li Kun Hu Institute of Frontier and Interdisciplinary Science Shandong UniversityQingdao 266237China

With the development of silicon photomultiplier(SiPM)technology,front-end electronics for SiPM signal processing have been highly sought after in various fields.A compact 64-channel front-end electronics(FEE)system achieved by fieldprogrammable gate array-based charge-to-digital converter(FPGA-QDC)technology was built and *** FEE consists of an analog board and FPGA *** analog board incorporates commercial amplifiers,resistors,and *** FPGA board is composed of a low-cost *** electronics performance of the FEE was evaluated in terms of noise,linearity,and uniformity.A positron emission tomography(PET)detector with three different readout configurations was designed to validate the readout capability of the FEE for SiPM-based *** PET detector was made of a 15×15 lutetium–yttrium oxyorthosilicate(LYSO)crystal array directly coupled with a SiPM array *** experimental results show that FEE can process dual-polarity charge signals from the SiPM *** addition,it shows a good energy resolution for 511-keV gamma photons under the dual-end readout for the LYSO crystal array irradiated by a Na-22 ***,the FEE based on FPGA-QDC shows promise for application in SiPM-based radiation detectors.

关键词： Readout electronics Charge measurement Radiation detector Silicon photomultiplier field-programmable gate array

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Fine-grained hardware resource optimization and design for FPGA-based real-time simulation of large-scale renewable energy generations

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International Journal of Electrical Power and Energy Systems 2025年 169卷

作者： Li, Yanfei Wang, Zhiying Fu, Xiaopeng Li, Peng Zhao, Ligang Wu, Xiaoshan Key Laboratory of Smart Grid of Ministry of Education Tianjin University Tianjin 300072 China China Southern Power Grid Electric Power Research Institute Guangzhou 510663 China

Real-time simulation of renewable energy generations (REGs) is essential for the development and testing of centralized scheduling controllers, inverter controllers and edge computing devices. The rapid expansion of renewable energy has brought tremendous computational challenges to the real-time simulation of REGs, particularly control system solutions. This study proposes a fine-grained hardware resource optimization and design method for real-time simulation of REG control system based on field-programmable gate array (FPGA). A hardware resource demand model is built at the arithmetic operation level. The minimum solution time and hardware resource constraints are considered. A detailed hardware design and automatic hardware description language generation method are proposed to rapidly generate the functional hardware modules for the REG control system solution. Real-time simulations of two REG systems integrated with 15 detailed modeling photovoltaic (PV) arrays and 15 wind turbines (WTs) have been conducted on a single FPGA, respectively. The simulation time-step of the PV-REG system is 9 μs and the time-step for the WT-REG system is 10 μs. Compared with the traditional hardware design, the hardware resource utilization has been reduced by 30% approximately. The relative error is less than 0.5% in contrast with the commercial off-line transient simulation software PSCAD/EMTDC. © 2025 The Author(s)

关键词： Automatic hardware description language generation field-programmable gate array Hardware resource optimization Real-time simulation Renewable energy generation

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