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Evaluation of a high-throughput communication link for future automotive ADAS controllers

PROCEEDINGS OF THE INSTITUTION OF MECHANICAL ENGINEERS PART D-JOURNAL OF AUTOMOBILE ENGINEERING 2019年第9期233卷 2371-2378页

作者： Luo Yigui Sun Youteng Schade, Florian Hotfilter, Tim Becker, Juergen Zhu Yuan Ouyang Zizhou Liang Weiming Tongji Univ Sch Software Engn 4800 Caoan Rd Shanghai 201804 Peoples R China Tongji Univ Inst Intelligent Vehicles Shanghai Peoples R China Karlsruher Inst Technol Inst Tech Informat Verarbeitung Karlsruhe Germany Tongji Univ Chines Deutsch Hsch Kolleg Shanghai Peoples R China SAIC Motor Shanghai Peoples R China

The trend toward further integration of automotive electronic control units functionality into domain control units as well as the rise of computing-intensive driver assistance systems has led to a demand for high-performance automotive computation platforms. These platforms have to fulfill stringent safety requirements. One promising approach is the use of performance computation units in combination with safety controllers in a single control unit. Such systems require adequate communication links between the computation units. While Ethernet is widely used, a high-speed serial link communication protocol supported by an Infineon AURIX safety controller appears to be a promising alternative. In this paper, a high-speed serial link IP core is presented, which enables this type of high-speed serial link communication interface for field-programmable gate array-based computing units. In our test setup, the IP core was implemented in a high-performance Xilinx Zynq UltraScale+, which communicated with an Infineon AURIX via high-speed serial link and Ethernet. The first bandwidth measurements demonstrated that high-speed serial link is an interesting candidate for inter-chip communication, resulting in bandwidths reaching up to 127 Mbit/s using stream transmissions.

关键词： ADAS (advanced driver assistance systems) field-programmable gate array high-speed serial link Ethernet communication

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Operation method for parallel inverter system with common dc link

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IET POWER ELECTRONICS 2014年第5期7卷 1138-1147页

作者： Song, Chunwei Zhao, Rongxiang Zhu, Minglei Zeng, Zheng Zhejiang Univ Dept Elect Engn Hangzhou 310027 Peoples R China

The configuration of parallel inverter system (PIS) with common dc link and no isolation measure is proposed. The gate control signals for switches in parallel inverters are synchronised to achieve ideal parallel operation status. Adopting the double loop control method which is composed of an outer voltage loop and an inner current loop, PIS has good dynamic response and robustness. In addition, the circulating current caused by the delay time of control signal transmission is studied in detail. The proposed operation method is easy to be implemented on the digital control board using digital signal processing and field-programmable gate array. The simulation and experimental results are presented to demonstrate the validity and features of the proposed operation method.

关键词： dynamic response electric current control invertors synchronisation voltage control parallel inverter system common dc link PIS gate control signal transmission switches double loop control method outer voltage control loop inner current control loop dynamic response circulating current delay time digital control board digital signal processing field-programmable gate array

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Optimum and heuristic synthesis of multiple word-length Architectures

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2005年第1期13卷 39-57页

作者： Constantinides, GA Cheung, PYK Luk, W Univ London Imperial Coll Sci Technol & Med Dept Elect Engn London SW7 2BT England Univ London Imperial Coll Sci Technol & Med Dept Chem London SW7 2BZ England

This paper explores the problem of architectural synthesis (scheduling, allocation, and binding) for multiple word-length systems. It is demonstrated that the resource allocation and binding problem, and the interaction between scheduling, allocation, and binding, are complicated by the existence of multiple word-length operators. Both optimum and heuristic approaches to the combined problem are formulated. The optimum solution involves modeling as an integer linear program, while the heuristic solution considers intertwined scheduling, binding, and resource word-length selection. Techniques are introduced to perform scheduling with incomplete word-length information, to combine binding and word-length selection, and to refine word-length information based on critical path analysis. Results are presented for several benchmark and artificial examples, demonstrating significant resource savings of up to 46% are possible by considering these problems within the proposed unified framework.

关键词： binding bitwidth digital signal processing field-programmable gate array high-level synthesis scheduling word-length

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Modification and hardware implementation of cortex-like object recognition model

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IET IMAGE PROCESSING 2020年第14期14卷 3490-3498页

作者： Anbaran, Alireza Mohammadi Torkzadeh, Pooya Ebrahimpour, Reza Bagheri, Nasour Islamic Azad Univ Dept Elect & Comp Engn Sci & Res Branch Tehran Iran Shahid Rajaee Teacher Training Univ Fac Comp Engn Tehran Iran Inst Res Fundamental Sci IPM Sch Cognit Sci Tehran Iran Shahid Rajaee Teacher Training Univ Elect Engn Dept Tehran Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran Iran

Object recognition in the visual cortex of mammals and humans has inspired many computational object recognition models. Hierarchical model and X (HMAX) is a well-known biologically motivated object recognition model with scale and position tolerance and high accuracy. Due to the computational intensive nature, hardware implementation with massive parallel processing is suggested for real-time applications. However, it is important to explore algorithmic trade-offs when mapping an algorithm to are configurable hardware. A direct conversion of the software implementation of an algorithm generally results inefficient hardware resource usage. In this study, the authors propose a novel modification into the HMAX model which makes it suitable for hardware implementation. More precisely, to reduce the number of memory blocks and multipliers of the S2 layer of HMAX produces, they replace the first norm by the second norm, which critically affects the silicon area in an application-specific integrated circuit implementation or the required resources in field-programmable gate array (FPGA). To evaluate the proposed model, they implement a pipelined version of the revised model on a mid-range commercial Xilinx FPGA, i.e. XC6VLX240T platform from a Virtex 6 family of Xilinx using ISE. Compared to the recent hardware implementation of HMAX, the proposed model offers 83% resource degradation in DSP48 slices and 3% in memory blocks.

关键词： field programmable gate arrays object recognition visual cortex computational object recognition models hierarchical model biologically motivated object recognition model position tolerance computational intensive nature massive parallel processing configurable hardware software implementation hardware resource usage HMAX model application-specific integrated circuit implementation hardware implementation cortex-like object recognition model field-programmable gate array FPGA XC6VLX240T platform Virtex 6 family Xilinx ISE

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A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder

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IEEE ACCESS 2017年 5卷 20965-20984页

作者： Hailes, Peter Xu, Lei Maunder, Robert G. Al-Hashimi, Bashir M. Hanzo, Lajos Univ Southampton Sch Elect & Comp Sci Southampton SO17 1BJ Hants England Intel Corp Programmable Solut Grp San Jose CA 95134 USA

Low-density parity check (LDPC) error correction decoders have become popular in diverse communications systems, owing to their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into the implementation of LDPC decoder designs on field-programmable gate array (FPGA) devices, in order to exploit their high processing speed, parallelism, and re-programmability. Meanwhile, a variety of application-specific integrated circuit implementations of multi-mode LDPC decoders exhibiting both inter-standard and intra-standard reconfiguration flexibility are available in the open literature. However, the high complexity of the adaptable routing and processing elements that are required by a flexible LDPC decoder has resulted in a lack of viable FPGA-based implementations. Hence in this paper, we propose a parameterisable FPGA-based LDPC decoder architecture, which supports run-time flexibility over any set of one or more quasi-cyclic LDPC codes. Additionally, we propose an off-line design flow, which may be used to automatically generate an optimized HDL description of our decoder, having support for a chosen selection of codes. Our implementation results show that the proposed architecture achieves a high level of design-time and run-time flexibility, whilst maintaining a reasonable processing throughput, hardware resource requirement, and error correction performance.

关键词： Digital communication error correction codes low-density parity check (LDPC) codes field-programmable gate array iterative decoding

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High-performance computer system dedicated to ray-wavefront conversion technique aimed to display holograms in real-time

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OPTICAL ENGINEERING 2023年第8期62卷

作者： Maruyama, Tatsuya Ichihashi, Yasuyuki Hoshi, Ikuo Kakue, Takashi Shimobaba, Tomoyoshi Ito, Tomoyoshi Chiba Univ Grad Sch Engn Chiba Japan Natl Inst Informat & Commun Technol Radio Res Inst Koganei Japan

Holography is the ultimate three-dimensional (3D) imaging technology, and research is actively being conducted on generating at high-speed holograms with enormous amounts of information and improving image quality. Because computer holography is based on wave optics algorithms, reconstructing the texture of 3D images is difficult. On the other hand, in principle, reconstructing texture in integral photography based on geometric optics is easy and the method is well established. We developed a high-performance special-purpose computer, called holographic reconstruction for ultra-realistic imaging, dedicated to the ray-wavefront conversion method. The design and implementation of the circuit for the hologram generation were performed using field-programmable gate array technology. Parallelization was performed at each step for increasing the speed of the calculation process. Furthermore, by sending output data directly to a displaying device in the high-definition multimedia interface, the communication between the host personal computer (PC) and special-purpose computer was controlled in one direction, which significantly reduced communication time. The system was similar to 7.7 times faster than a PC alone and succeeded in the holographic reproduction of a textured 3D image in real time at 30 frames per second for a 1024 x 1024-pixel hologram. (c) The Authors. Published by SPIE under a Creative Commons Attribution 4.0 International License. Distribution or reproduction of this work in whole or in part requires full attribution of the original publication, including its DOI.

关键词： holography computer-generated hologram field-programmable gate array light-ray information discrete Fourier transform

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field programmable gate arrays implementation of automated sensor self-validation system for cupola furnaces

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COMPUTERS & INDUSTRIAL ENGINEERING 2004年第3期46卷 553-569页

作者： Mahmoud, WH Abdelrahman, M Haggard, RL Tennessee Technol Univ Dept Elect & Comp Engn Cookeville TN 38505 USA

The paper presents the use of an field-programmable gate array (FPGA) system in the hardware implementation of the algorithm. The self-validation (SV) algorithm is based on fuzzy logic and is used to estimate a confidence measure of a sensor's readings using the sensor's historic data. The hardware system consists of a data acquisition and conditioning system, a general-purpose CPU, and an FPGA system. The general-purpose CPU is used in the setup phase of the algorithm and in the preprocessing of the sensors' readings. The FPGA system is used in the on-line calculations of the confidence measures of the sensors' readings. The system is designed using data from an iron-melting cupola furnace. The paper presents the details of the developed SV software algorithm, the modifications of the algorithm to suit the FPGA implementation, the overall design of the hardware system, and the FPGA implementation of the algorithm. The results of the implementation are also discussed. (C) 2004 Elsevier Ltd. All rights reserved.

关键词： fuzzy controllers field-programmable gate array self-validation

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Low-area and high-speed hardware architectures of KLEIN lightweight block cipher for image encryption

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JOURNAL OF ELECTRONIC IMAGING 2023年第1期32卷

作者： Singh, Pulkit Agrawal, Bhaskar Chaurasiya, Rahul Kumar Acharya, Bibhudendra Natl Inst Technol Raipur Dept Elect & Commun Engn Raipur Chhattisgarh India Maulana Azad Natl Inst Technol Bhopal Dept Elect & Commun Engn Bhopal Madhya Pradesh India

Internet of Things (IoT) connects a wide range of small devices over a large network, allowing for a wide range of applications. With the advancement of open-source public networks (such as IoT), image transmission for resource-constrained devices is becoming more insecure. In this paper, two hardware implementations for KLEIN block cipher are proposed that can provide security to encrypt different sets of images under resource-constrained applications (such as wireless sensor network, radio frequency identification, IoT etc.). An improvement in maximum operating frequency of 32.72% and 75.66% in the proposed serial and pipelined architectures is observed compared with the state-of-the-art design, respectively. The implemented pipelined architecture yields high throughput of 1840.15 MHz, and the serialized architecture implies 108 numbers of slices implemented on field-programmable gate array (FPGA) xc5vlx50t-3ff1136 device. On application-specific integrated circuit (ASIC) platform, the proposed serialized KLEIN implementation consumed less area in terms of gate equivalent. The existing solution was also subjected to changing correlation coefficients, number of pixels changing rate, unified average changing intensity, and entropy values. The simulation results validate the effectiveness of the performance of the proposed encryption scheme.

关键词： security lightweight cryptography field-programmable gate array application-specific integrated circuit image encryption

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Development of a New High Speed Dual-Channel Impulse Ground Penetrating Radar

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IEEE JOURNAL OF SELECTED TOPICS IN APPLIED EARTH OBSERVATIONS AND REMOTE SENSING 2014年第3期7卷 753-760页

作者： Venkatachalam, Anbu Selvam Xu, Xianlei Huston, Dryver Xia, Tian Univ Vermont Sch Engn Burlington VT 05405 USA

This paper presents the development of a dual channel, air coupled Ultra-Wideband (UWB) Ground Penetrating Radar (GPR) targeting highway pavements and bridge deck inspections. Compared to most existing GPRs with a single channel and low survey speeds, our GPR possesses competitive features, including wide area coverage, high spatial resolution and operating capability at normal highway driving speed (up to 60 mph). The system has a two-channel microwave front end, a high speed (8 Gsps) real time data acquisition unit, a high throughput multi-thread data transmission and storage module, and a customized low-cost control element developed in a field-programmable gate array (FPGA). Experiments with different steel reinforcing bars establish GPR system performance.

关键词： field-programmable gate array ground penetrating radar ultra-wideband (UWB)

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The architecture of a fault-tolerant modular neurocomputer based on modular number projections

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NEUROCOMPUTING 2018年 272卷 96-107页

作者： Chervyakov, N. I. Lyakhov, P. A. Babenko, M. G. Lavrinenko, I. N. Lavrinenko, A. V. Nazarov, A. S. North Caucasus Fed Univ Dept Appl Math & Math Modeling Stavropol Russia North Caucasus Fed Univ Dept Higher Algebra & Geometry Stavropol Russia

This paper suggests a rather efficient architecture for an error correction unit of a residue number system (RNS) that is based on a redundant RNS (RRNS) and applied in parallel data processing structures owing to its capability to improve information stability in calculations. However, the high efficiency of error correction is still not achieved due to the need in the expensive and complex operators that require substantial computational resources and considerable execution time. The suggested error correction method employs the Chinese remainder theorem (CRT) and artificial neural networks (ANN) that appreciably simplify the process of error detection, localization and correction. The key components of the error correction procedure are optimized using (a) the mixed radix conversion (MRC), i.e., the parallel conversion of the numbers from an RNS into the mixed radix number system (MRNS), and (b) the adaptation of neural networks to different sets of RNS moduli (bases) and also to the modular arithmetic during the computation of modular number projections and the restoration of the correct residue on a faulty module. Therefore, the expensive topological structures of neural networks are replaced with the reconfiguration using the weight coefficients switching. In comparison with the existing CRT-based method of projection calculation, the suggested method yields a 20%-30% reduction in power consumption, yet requiring by 10%-20% less FPGA resources for implementation. (C) 2017 Elsevier B.V. All rights reserved.

关键词： Modular neurocomputer Residue number system Fault-tolerance Digital neuron Finite ring neural network field-programmable gate array

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