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检索条件"主题词=Field-programmable Gate Array"
561 条 记 录,以下是71-80 订阅
排序:
Evaluation of a high-throughput communication link for future automotive ADAS controllers
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PROCEEDINGS OF THE INSTITUTION OF MECHANICAL ENGINEERS PART D-JOURNAL OF AUTOMOBILE ENGINEERING 2019年 第9期233卷 2371-2378页
作者: Luo Yigui Sun Youteng Schade, Florian Hotfilter, Tim Becker, Juergen Zhu Yuan Ouyang Zizhou Liang Weiming Tongji Univ Sch Software Engn 4800 Caoan Rd Shanghai 201804 Peoples R China Tongji Univ Inst Intelligent Vehicles Shanghai Peoples R China Karlsruher Inst Technol Inst Tech Informat Verarbeitung Karlsruhe Germany Tongji Univ Chines Deutsch Hsch Kolleg Shanghai Peoples R China SAIC Motor Shanghai Peoples R China
The trend toward further integration of automotive electronic control units functionality into domain control units as well as the rise of computing-intensive driver assistance systems has led to a demand for high-per... 详细信息
来源: 评论
Operation method for parallel inverter system with common dc link
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IET POWER ELECTRONICS 2014年 第5期7卷 1138-1147页
作者: Song, Chunwei Zhao, Rongxiang Zhu, Minglei Zeng, Zheng Zhejiang Univ Dept Elect Engn Hangzhou 310027 Peoples R China
The configuration of parallel inverter system (PIS) with common dc link and no isolation measure is proposed. The gate control signals for switches in parallel inverters are synchronised to achieve ideal parallel oper... 详细信息
来源: 评论
Optimum and heuristic synthesis of multiple word-length Architectures
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2005年 第1期13卷 39-57页
作者: Constantinides, GA Cheung, PYK Luk, W Univ London Imperial Coll Sci Technol & Med Dept Elect Engn London SW7 2BT England Univ London Imperial Coll Sci Technol & Med Dept Chem London SW7 2BZ England
This paper explores the problem of architectural synthesis (scheduling, allocation, and binding) for multiple word-length systems. It is demonstrated that the resource allocation and binding problem, and the interacti... 详细信息
来源: 评论
Modification and hardware implementation of cortex-like object recognition model
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IET IMAGE PROCESSING 2020年 第14期14卷 3490-3498页
作者: Anbaran, Alireza Mohammadi Torkzadeh, Pooya Ebrahimpour, Reza Bagheri, Nasour Islamic Azad Univ Dept Elect & Comp Engn Sci & Res Branch Tehran Iran Shahid Rajaee Teacher Training Univ Fac Comp Engn Tehran Iran Inst Res Fundamental Sci IPM Sch Cognit Sci Tehran Iran Shahid Rajaee Teacher Training Univ Elect Engn Dept Tehran Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran Iran
Object recognition in the visual cortex of mammals and humans has inspired many computational object recognition models. Hierarchical model and X (HMAX) is a well-known biologically motivated object recognition model ... 详细信息
来源: 评论
A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder
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IEEE ACCESS 2017年 5卷 20965-20984页
作者: Hailes, Peter Xu, Lei Maunder, Robert G. Al-Hashimi, Bashir M. Hanzo, Lajos Univ Southampton Sch Elect & Comp Sci Southampton SO17 1BJ Hants England Intel Corp Programmable Solut Grp San Jose CA 95134 USA
Low-density parity check (LDPC) error correction decoders have become popular in diverse communications systems, owing to their strong error correction performance and their suitability to parallel hardware implementa... 详细信息
来源: 评论
High-performance computer system dedicated to ray-wavefront conversion technique aimed to display holograms in real-time
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OPTICAL ENGINEERING 2023年 第8期62卷
作者: Maruyama, Tatsuya Ichihashi, Yasuyuki Hoshi, Ikuo Kakue, Takashi Shimobaba, Tomoyoshi Ito, Tomoyoshi Chiba Univ Grad Sch Engn Chiba Japan Natl Inst Informat & Commun Technol Radio Res Inst Koganei Japan
Holography is the ultimate three-dimensional (3D) imaging technology, and research is actively being conducted on generating at high-speed holograms with enormous amounts of information and improving image quality. Be... 详细信息
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field programmable gate arrays implementation of automated sensor self-validation system for cupola furnaces
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COMPUTERS & INDUSTRIAL ENGINEERING 2004年 第3期46卷 553-569页
作者: Mahmoud, WH Abdelrahman, M Haggard, RL Tennessee Technol Univ Dept Elect & Comp Engn Cookeville TN 38505 USA
The paper presents the use of an field-programmable gate array (FPGA) system in the hardware implementation of the algorithm. The self-validation (SV) algorithm is based on fuzzy logic and is used to estimate a confid... 详细信息
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Low-area and high-speed hardware architectures of KLEIN lightweight block cipher for image encryption
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JOURNAL OF ELECTRONIC IMAGING 2023年 第1期32卷
作者: Singh, Pulkit Agrawal, Bhaskar Chaurasiya, Rahul Kumar Acharya, Bibhudendra Natl Inst Technol Raipur Dept Elect & Commun Engn Raipur Chhattisgarh India Maulana Azad Natl Inst Technol Bhopal Dept Elect & Commun Engn Bhopal Madhya Pradesh India
Internet of Things (IoT) connects a wide range of small devices over a large network, allowing for a wide range of applications. With the advancement of open-source public networks (such as IoT), image transmission fo... 详细信息
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Development of a New High Speed Dual-Channel Impulse Ground Penetrating Radar
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IEEE JOURNAL OF SELECTED TOPICS IN APPLIED EARTH OBSERVATIONS AND REMOTE SENSING 2014年 第3期7卷 753-760页
作者: Venkatachalam, Anbu Selvam Xu, Xianlei Huston, Dryver Xia, Tian Univ Vermont Sch Engn Burlington VT 05405 USA
This paper presents the development of a dual channel, air coupled Ultra-Wideband (UWB) Ground Penetrating Radar (GPR) targeting highway pavements and bridge deck inspections. Compared to most existing GPRs with a sin... 详细信息
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The architecture of a fault-tolerant modular neurocomputer based on modular number projections
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NEUROCOMPUTING 2018年 272卷 96-107页
作者: Chervyakov, N. I. Lyakhov, P. A. Babenko, M. G. Lavrinenko, I. N. Lavrinenko, A. V. Nazarov, A. S. North Caucasus Fed Univ Dept Appl Math & Math Modeling Stavropol Russia North Caucasus Fed Univ Dept Higher Algebra & Geometry Stavropol Russia
This paper suggests a rather efficient architecture for an error correction unit of a residue number system (RNS) that is based on a redundant RNS (RRNS) and applied in parallel data processing structures owing to its... 详细信息
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