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Automatic cache partitioning method for high-level synthesis

MICROPROCESSORS AND MICROSYSTEMS 2019年 67卷 71-81页

作者： Jones, Bryant Hanna, Darrin M. Oakland Univ Dept Elect & Comp Engn Rochester MI 48309 USA

Existing algorithms can be automatically translated from software to hardware using High-Level Synthesis (HLS), allowing for quick prototyping or deployment of embedded designs. High-level software is written with a single main memory in mind, whereas hardware designs can take advantage of many parallel memories. The translation and optimization of memory usage, and the generation of resulting architectures, is important for high-performance designs. Tools provide optimizations on memory structures targeting data reuse and partitioning, but generally these are applied separately for a given object in memory. Memory access that cannot be effectively optimized is serialized to the memory, hindering any further parallelization of the surrounding generated hardware. In this work, we present an automated optimization method for creating custom cache memory architectures for HLS generated designs. Our optimization uses runtime profiling data, and is performed at a localized scope. This method combines data reuse savings and memory partitioning to further increase the potential parallelism and alleviate the serialized memory access, increasing performance. Comparisons are made against architectures without this optimization, and against other HLS caching approaches. Results are presented showing this method requires 72% of the number of execution cycles compared to a single-cache design, and 31% compared to designs with no caches. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Compilers field-programmable gate array High-level synthesis Caches Memory architectures

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New wind turbine emulator based on DC machine: hardware implementation using FPGA board for an open-loop operation

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IET CIRCUITS DEVICES & SYSTEMS 2019年第6期13卷 896-902页

作者： Moussa, Intissar Bouallegue, Adel Khedher, Adel Univ Sousse Elect Engn Ecole Natl Ingenieurs Sousse LATIS Lab Adv Technol & Intelligent Syst Sousse 4023 Tunisia

This work deals with the development of an open-loop wind turbine emulator to verify the system operation with respect to the wind profile. The emulator consists essentially of a 300 W DC motor powered by DC/DC buck converter which controlled through field-programmable gate array (FPGA) and pulse-width modulation strategy. The motor rotational speed allows to imitate proportionally different wind velocity. A hardware test bench based on the fast prototyping method using MATLAB/Xilinx System Generation (XSG) environment and FPGA board of wind turbine simulator is built to validate the simulation results. Simulation and experimental results confirm the efficiency of the implemented method to make the proposed emulator able to react as a real wind in laboratory.

关键词： DC-DC power convertors machine control wind turbines DC motors field programmable gate arrays DC machine hardware implementation FPGA board open-loop operation open-loop wind turbine emulator system operation wind profile 300 W DC motor field-programmable gate array pulse-width modulation strategy motor rotational speed proportionally different wind velocity hardware test bench wind turbine simulator power 300 0 W implemented method

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Evaluation of a high-throughput communication link for future automotive ADAS controllers

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PROCEEDINGS OF THE INSTITUTION OF MECHANICAL ENGINEERS PART D-JOURNAL OF AUTOMOBILE ENGINEERING 2019年第9期233卷 2371-2378页

作者： Luo Yigui Sun Youteng Schade, Florian Hotfilter, Tim Becker, Juergen Zhu Yuan Ouyang Zizhou Liang Weiming Tongji Univ Sch Software Engn 4800 Caoan Rd Shanghai 201804 Peoples R China Tongji Univ Inst Intelligent Vehicles Shanghai Peoples R China Karlsruher Inst Technol Inst Tech Informat Verarbeitung Karlsruhe Germany Tongji Univ Chines Deutsch Hsch Kolleg Shanghai Peoples R China SAIC Motor Shanghai Peoples R China

The trend toward further integration of automotive electronic control units functionality into domain control units as well as the rise of computing-intensive driver assistance systems has led to a demand for high-performance automotive computation platforms. These platforms have to fulfill stringent safety requirements. One promising approach is the use of performance computation units in combination with safety controllers in a single control unit. Such systems require adequate communication links between the computation units. While Ethernet is widely used, a high-speed serial link communication protocol supported by an Infineon AURIX safety controller appears to be a promising alternative. In this paper, a high-speed serial link IP core is presented, which enables this type of high-speed serial link communication interface for field-programmable gate array-based computing units. In our test setup, the IP core was implemented in a high-performance Xilinx Zynq UltraScale+, which communicated with an Infineon AURIX via high-speed serial link and Ethernet. The first bandwidth measurements demonstrated that high-speed serial link is an interesting candidate for inter-chip communication, resulting in bandwidths reaching up to 127 Mbit/s using stream transmissions.

关键词： ADAS (advanced driver assistance systems) field-programmable gate array high-speed serial link Ethernet communication

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Modification and hardware implementation of cortex-like object recognition model

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IET IMAGE PROCESSING 2020年第14期14卷 3490-3498页

作者： Anbaran, Alireza Mohammadi Torkzadeh, Pooya Ebrahimpour, Reza Bagheri, Nasour Islamic Azad Univ Dept Elect & Comp Engn Sci & Res Branch Tehran Iran Shahid Rajaee Teacher Training Univ Fac Comp Engn Tehran Iran Inst Res Fundamental Sci IPM Sch Cognit Sci Tehran Iran Shahid Rajaee Teacher Training Univ Elect Engn Dept Tehran Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran Iran

Object recognition in the visual cortex of mammals and humans has inspired many computational object recognition models. Hierarchical model and X (HMAX) is a well-known biologically motivated object recognition model with scale and position tolerance and high accuracy. Due to the computational intensive nature, hardware implementation with massive parallel processing is suggested for real-time applications. However, it is important to explore algorithmic trade-offs when mapping an algorithm to are configurable hardware. A direct conversion of the software implementation of an algorithm generally results inefficient hardware resource usage. In this study, the authors propose a novel modification into the HMAX model which makes it suitable for hardware implementation. More precisely, to reduce the number of memory blocks and multipliers of the S2 layer of HMAX produces, they replace the first norm by the second norm, which critically affects the silicon area in an application-specific integrated circuit implementation or the required resources in field-programmable gate array (FPGA). To evaluate the proposed model, they implement a pipelined version of the revised model on a mid-range commercial Xilinx FPGA, i.e. XC6VLX240T platform from a Virtex 6 family of Xilinx using ISE. Compared to the recent hardware implementation of HMAX, the proposed model offers 83% resource degradation in DSP48 slices and 3% in memory blocks.

关键词： field programmable gate arrays object recognition visual cortex computational object recognition models hierarchical model biologically motivated object recognition model position tolerance computational intensive nature massive parallel processing configurable hardware software implementation hardware resource usage HMAX model application-specific integrated circuit implementation hardware implementation cortex-like object recognition model field-programmable gate array FPGA XC6VLX240T platform Virtex 6 family Xilinx ISE

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VLSI implementation of reversible logic gates cryptography with LFSR key

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MICROPROCESSORS AND MICROSYSTEMS 2019年第Sep.期69卷 68-78页

作者： Karunamurthi, Saranya Natarajan, Vijeyakumar Krishnasamy Dr Mahalingam Coll Engn & Technol Dept Elect & Elect Engn Coimbatore Tamil Nadu India Dr Mahalingam Coll Engn & Technol Dept Elect & Commun Engn Coimbatore Tamil Nadu India

The reversible computation is an emerging research field, which is used in different applications such as optical computing, digital signal processing, nanotechnologies, bio-information and in low-power computation. In present days, these applications require security algorithm to keep the information securely. The power and area analysis are one of the major challenges to mathematically secure cryptography protocols. Moreover, hackers can take confidential data while it passes through the transmission line. To overcome this problem, Reversible logic cryptography design (RLCD) architecture is introduced in this paper. With the help of RLCD, the encryption and decryption architecture is designed. Linear feedback shift register (LFSR) is required to produce a key which is given to the encryption and decryption block. The application specified integrated chip (ASIC) and field-programmable gate array (FPGA) performances are evaluated for both existing and proposed method. More than 7% of the ASIC performances improved in RLCD-LFSR method compared to the conventional methods. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Application specified integrated chip field-programmable gate array Linear feedback shift register Power Reversible logic cryptography design

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Pseudo-Sensorless High-Performance Bilateral Teleoperation by Sliding-Mode Control and FPGA

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IEEE-ASME TRANSACTIONS ON MECHATRONICS 2014年第1期19卷 384-393页

作者： Hace, Ales Franc, Marko Univ Maribor Inst Robot SLO-2000 Maribor Slovenia Isomat Doo Mezica 2392 Slovenia

This paper proposes a pseudo-sensorless implementation of scaled bilateral teleoperation. It is based on Hall effect sensors that are built within the motor housing. The proposed implementation requires no external sensor that can deteriorate system dynamics and performance. The integrated sensors have been used both for position measurement and external force estimation that are necessary in high-performance bilateral teleoperation. Nevertheless, system perturbation dynamics may always appear in a practical mechatronic system. Therefore, the chattering-free sliding-mode control algorithm is applied that ensures robustness toward the disturbances, and yet is easy to implement. The data acquisition algorithms as well as the control algorithm are implemented by field-programmable gate array (FPGA) in order to provide high control rate that can further increase robustness required for haptic fidelity of the system for scaled teleoperation. The applied algorithms along with the FGPA implementation were validated by the 2-DoF experimental system. It has been shown that the proposed pseudo-sensorless implementation by FPGA provides high bilateral teleoperation performance.

关键词： Bilateral teleoperation field-programmable gate array haptics sliding-mode control (SMC)

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An experimental study of coarse-grained reconfigurable system-on-chip-based software-defined radio

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2016年第3期24卷 1176-1193页

作者： Nithiyanantham, Janakiraman Palanisamy, Nirmal Kumar Anna Univ Dept Elect & Commun Engn Fac Informat & Commun Engn Madras 600025 Tamil Nadu India

Software-defined radio (SDR) research deals with a mixture of hardware and software technologies, where RF operating parameters and components are to be set or altered by modifiable software or firmware. This paper describes the coarse-grained reconfigurable array (CGRA) implementations of SDR architecture. This architecture is an extension of traditional SDR in complex adaptation strategies, such as highly reliable communications and efficient utilization of the resources and spectrum upgrade, through its internal states (performance) and hardware architecture. The proposed CGRA-based SDR implementation is based on dynamic partial reconfiguration methodology, which has the capability of reusing the same hardware module to handle different algorithms. This CGRA-based SDR provides greater flexibility and adds new abilities without additional cost. Initially, the SDR system was simulated in the Agilent SystemVue environment to analyze the error boundaries of the proposed SDR architecture. Then the SDR system was coded in the Verilog hardware description language and implemented on top of CGRAs such as the MOLEN, MORPHOSYS, and ADRES reconfigurable system-on-chip (SoC) architectures. These SoC architectures were installed within the Xilinx Virtex 5 field-programmable gate array to analyze the performance of SDR architectures in terms of area utilization, operational speed, power optimization, reconfiguration time, coprocessor execution time, preemption support, and relocation support of the system. The performance analysis indicates that the ADRES SoC architecture is suitable for dynamic partial reconfiguration and the MOLEN SoC architecture is more suitable for power, area, and speed requirements and low circuit complexity compared to other architectures.

关键词： Software-defined radio reconfigurable architecture field-programmable gate array system-on-chip MOLEN MORPHOSYS ADRES

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Design of a Multiple Pseudorandom Number Generator Combined Chaotic System With RNS and Its Application to Secure Image Processing

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IEEE ACCESS 2024年 12卷 155246-155258页

作者： Liu, Chien-Chun Chen, Chih-Chiang Yan, Jun-Juh Liao, Teh-Lu Natl Cheng Kung Univ Dept Engn Sci Tainan 70101 Taiwan Air Force Inst Technol Dept Aircraft Engn Kaohsiung 82063 Taiwan Natl Cheng Kung Univ Dept Syst & Naval Mechatron Engn Tainan 70101 Taiwan Natl Chin Yi Univ Technol Dept Elect Engn Taichung 41107 Taiwan

This paper presents a novel approach to designing a multiple pseudorandom number generator (MPNG) through the integration of several key techniques. Specifically, the method leverages the chaotic dynamics of the 2D Tinkerbell system, a residue number system (RNS), and XOR operations to generate multiple sets of pseudorandom number sequences. The MPNG offers several advantages, including a simple design and low hardware resource requirements. Implemented using a field-programmable gate array (FPGA), it applies each chaotic system state to produce three sets of random number sequences, achieving a generation rate three times higher. The generated sequences are rigorously evaluated using the NIST SP800-22 and Diehard test suites, along with Shannon entropy and histogram analyses, all of which confirm their randomness. The results pass all NIST SP800-22 and Diehard test items, demonstrating the properties of random numbers. Additionally, this paper proposes a synchronization controller to achieve state synchronization between the master system and the slave system, enabling symmetric encryption and decryption applications for secure image processing.

关键词： Chaotic communication Encryption Main-secondary Generators Synchronization field programmable gate arrays NIST Hardware Noise measurement Receivers Multiple pseudorandom number generator chaotic system residue number system field-programmable gate array

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Stability-guaranteed predictive sliding surface control of silicon carbide dual-output nine-switch inverter

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ELECTRICAL ENGINEERING 2022年第4期104卷 2009-2020页

作者： Gulbudak, Ozan Karabuk Univ Coll Engn Dept Elect Elect Engn Main Campus Elect Elect Engn 108 TR-78050 Karabuk Turkey

In this study, a finite control set model predictive control strategy is proposed for a nine-switch converter system. The predictive control routine with discrete-solution space in energy transformation applications is widely used and offers a satisfactory closed-loop operation. However, the stability analysis of the predictive control method is a challenging task, and the practical stability approaches are applied to examine the closed-loop stability characteristics. Designing the guaranteed-stability predictive control is not an easy task since even the norm choice of the objective function may result in closed-loop instability. Regarding closed-loop stability, stability-guaranteed predictive sliding surface control approach is introduced in this study. The multi-objective cost function is reformulated in the proposed method as a sliding surface function usually used in sliding mode control methods. Thus, the best-suited control input that meets the sliding mode control stability criterion is picked. The proposed reformulation process enables the sliding surface function as an objective function, and the sliding surface function is gauged for each legitimate switching combination. The proposed control method is experimentally verified by using a 3.2 kW silicon carbide nine-switch inverter prototype. The experimental results prove that the proposed method guarantees closed-loop stability, and dual-AC load control is achieved.

关键词： Sliding mode control Sliding surface-based predictive approach Nine-switch inverter field-programmable gate array Nonlinear control

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Minimalistic SDHC-SPI hardware reader module for boot loader applications

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MICROELECTRONICS JOURNAL 2017年 67卷 32-37页

作者： Ruiz-de-Clavijo, Paulino Ostua, Enrique Bellido, Manuel-J. Juan, Jorge Viejo, Julian Guerrero, David Univ Seville ETS Ingn Informat Dept Tecnol Elect Seville Spain

This paper introduces a low-footprint full hardware boot loading solution for FPGA-based programmable Systems on Chip. The proposed module allows loading the system code and data from a standard SD card without having to re-program the whole embedded system. The hardware boot loader is processor independent and removes the need of a software boot loader and the related memory resources. The hardware overhead introduced is manageable, even in low-range FPGA chips, and negligible in mid-and high-range devices. The implementation of the SD card reader module is explained in detail and an example of a multi-boot loader is offered as well. The multi-boot loader is implemented and tested with the Xilinx's Picoblaze microcontroller.

关键词： field-programmable gate array Secure Digital Boot loader Serial Peripheral Interface System on Chip Embedded systems

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