检索结果-内蒙古大学图书馆

Embedded architecture for noise-adaptive video object detection using parameter-compressed background modeling

JOURNAL OF REAL-TIME IMAGE PROCESSING 2017年第2期13卷 397-414页

作者： Ratnayake, Kumara Amer, Aishy Concordia Univ Dept Elect & Comp Engn Montreal PQ Canada

Video processing algorithms are computationally intensive and place stringent requirements on performance and efficiency of memory bandwidth and capacity. As such, efficient hardware accelerations are inevitable for fast video processing systems. In this paper, we propose resource- and power-optimized FPGA-based configurable architecture for video object detection by integrating noise estimation, Mixture-of-Gaussian background modeling, motion detection, and thresholding. Due to large amount of background modeling parameters, we propose a novel Gaussian parameter compression technique suitable for resource- and power-constraint embedded video systems. The proposed architecture is simulated, synthesized and verified for its functionality, accuracy and performance on a Virtex-5 FPGA-based embedded platform by directly interfacing to a digital video input. Intentional exploitation of heterogeneous resources in FPGAs, and advanced design techniques such as heavy pipelining and data parallelism yield real-time processing of HD-1080p video streams at 30 frames per second. Objective and subjective evaluations to existing hardware-based methods show that the proposed architecture obtains orders of magnitude performance improvements, while utilizing minimal hardware resources. This work is an early attempt to devise a complete video surveillance system onto a stand-alone resource-constraint FPGA-based smart camera.

关键词： field-programmable gate arrays FPGA Video signal processing Noise Moving objects Motion detection Thresholding Gaussian background update Gaussian parameter compression

来源：评论

学校读者我要写书评

暂无评论

PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era

引用

IEEE TRANSACTIONS ON COMPUTERS 2017年第6期66卷 982-995页

作者： Ebrahimi, Zahra Khaleghi, Behnam Asadi, Hossein Sharif Univ Technol Dept Comp Engn Tehran *** Iran

Significant increase of static power in nano-CMOS era and, subsequently, the end of Dennard scaling has put a Power Wall to further integration of CMOS technology in field-programmable gate arrays (FPGAs). An efficient solution to cope with this obstacle is power gating inactive fractions of a single die, resulting in Dark Silicon. Previous studies employing power gating on SRAM-based FPGAs have primarily focused on using large-input Look-up Tables (LUTs). The architectures proposed in such studies inherently suffer from poor logic utilization which limits the benefits of power gating techniques. This paper proposes a Power-Efficient Architecture for FPGAs (PEAF) based on combination of Reconfigurable Hard Logics (RHLs) and a small-input LUT. In the proposed architecture, we selectively turn off unused RHLs and/or LUTs within each logic block by employing a reconfigurable controller. By mapping a majority of logic functions to simple-design RHLs, PEAF is able to significantly improve power efficiency without deteriorating the performance. Experimental results over a comprehensive set of benchmarks (MCNC, IWLS'05, and VTR) demonstrate that compared with baseline four-LUT architecture, PEAF reduces the total static power and Power-Delay-Product (PDP), on average, by 24.5 and 21.7 percent, respectively. This is while the overall system performance is also improved by 1.8 percent. PEAF increases total area by 18.9 percent, however, it still occupies 22.1 percent less area footprint than the six-LUT architecture with 31.5 percent improvement in PDP.

关键词： field-programmable gate arrays static power SRAM dark silicon hard logic

来源：评论

学校读者我要写书评

暂无评论

System-Level, FPGA-Based, Real-Time Simulation of Ship Power Systems

引用

IEEE TRANSACTIONS ON ENERGY CONVERSION 2017年第2期32卷 737-747页

作者： Milton, Matthew Benigni, Andrea Bakos, Jason Univ South Carolina Dept Elect Engn Columbia SC 29208 USA Univ South Carolina Dept Comp Sci & Engn Columbia SC 29208 USA

In this paper, we present a scalable approach for real-time simulation of ship power systems with high-frequency power electronics converters (100-200 kHz). The proposed approach is based on the latency-based linear multistep compound method and relies on field-programmable gate array (FPGA) execution. Several examples of increasing dimension and complexity are used to evaluate the scalability-both of in terms of computational delay and of resources usage-of the proposed approach. Real-time execution with a 50 ns time step is achieved for all the examples considered.

关键词： field-programmable gate arrays parallel algorithms power system simulation power electronics real time systems

来源：评论

学校读者我要写书评

暂无评论

An efficient systolic array grid-based structure of the robust Bayesian regularization technique for real-time enhanced imaging in uncertain remote sensing environment

引用

JOURNAL OF REAL-TIME IMAGE PROCESSING 2017年第4期13卷 783-796页

作者： Castillo Atoche, A. Carrasco Alvarez, R. Palma Marrufo, O. Vazquez Castillo, J. Univ Autonoma Yucatan Dept Mechatron Ave Ind Contaminantes S-N Perifer Norte Merida Yucatan Mexico Univ Guadalajara Elect Engn Div Blvd Marcelino Garcia Barragan 1421 Guadalajara Jalisco Mexico Univ Quintana Roo Div Sci Blvd Bahia S-N Esq Ignacio Comonfort Chetmal Quintana Roo Mexico

In this paper, we address a hardware implementation of the efficient robust Bayesian regularization architecture for the real-time enhancement of large-scale remote sensing (RS) imaging. The efficient sense of the proposed architecture is related to the high-performance embedded implementation that is achieved with the aggregation of parallel computing and systolic array design techniques in a novel grid connected-based accelerator. Then, the developed high-speed accelerator is integrated with an embedded processor via the HW/SW co-design paradigm. The presented approach is used for solving RS image enhancement/reconstruction of the ill-conditioned inverse spatial spectrum pattern estimation problems via an interesting low-cost high-performance embedded computing solution. Finally, we show the achieved results and how we drastically reduced the computational load for real-world large-scale geospatial images.

关键词： Remote sensing Real-time systems Systolic array architectures field-programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

CUTE Mote, A Customizable and Trustable End-Device for the Internet of Things

引用

IEEE SENSORS JOURNAL 2017年第20期17卷 6816-6824页

作者： Gomes, Tiago Salgado, Filipe Tavares, Adriano Cabral, Jorge Univ Minho Ctr ALGORITMI P-4800058 Guimaraes Portugal

The ubiquitous connectivity of the low-end devices in the Internet of Things (IoT) brings new challenges over the traditional wireless sensor networks' architectures. Such challenges require not only security and privacy-related features, but also solutions to handle the ever-growing amount of data transferred over the network. However, performing such tasks on resource constrained devices is not straightforward. The need for energy-efficient devices, while preserving their performance and security capabilities, requires new solutions at the architectural level of the wireless device. This paper proposes a heterogeneous architecture that targets low-end and resource constrained IoT devices, combining a hardcore microcontroller unit (MCU) and a reconfigurable computing unit (RCU) with an IEEE 802.15.4 radio transceiver. The MCU hosts an embedded operating system with an IoT-enabled network stack, and exploits the available field-programmable gate array technology to implement the RCU and to deploy customized sensing-and network-related accelerators, offloading heavy, and/or complex software tasks to dedicated hardware blocks. The customizable and trustable end-device mote was implemented using the proposed architecture and the achieved results demonstrates the benefits, both in terms of performance and energy, of accelerating network-related tasks in always-connected resource constrained IoT devices.

关键词： Accelerator architectures heterogeneous networks Internet of Things field-programmable gate arrays wireless sensor networks

来源：评论

学校读者我要写书评

暂无评论

G-AETCAM: gate-Based Area-Efficient Ternary Content-Addressable Memory on FPGA

引用

IEEE ACCESS 2017年 5卷 20785-20790页

作者： Irfan, Muhammad Ullah, Zahid CECOS Univ IT & Emerging Sci Dept Elect Engn Peshawar 25100 Pakistan

This paper presents a novel architecture for ternary content-addressable memory (TCAM), using G-AETCAM cells, which outputs the address of the provided input data. The proposed architecture is a matrix of G-AETCAM cells arranged in the form of rows and columns using flip-flop as a memory element and a control logic circuitry consisting of logic gates. One G-AETCAM cell encodes the input and stored bit into one encoded bit which results in a match-line after passing from the AND-gate-array. Many architectures configure random-access memory (RAM) available on FPGAs as content-addressable storage architecture but are efficient for specific size and deal with data only in ascending or descending order while the proposed architecture provides freedom in size with no chance of making a single memory cell as useless and can store ternary data in any order. RAM-based TCAMs require pre-processing for the storage of TCAM words while the proposed design does not involve any pre-processing. The proposed architecture reduces the transistor count by a factor of 25.55, as compared with the RAM-based TCAM, which ultimately reduces area and increases the speed of operations. The proposed architecture is successfully implemented on Xilinx Virtex-6 FPGA for the size 64 x 36 and achieves a speed of 358 MHz.

关键词： Content-addressable storage field-programmable gate arrays flip-flops logic gates memory RAM-based TCAM

来源：评论

学校读者我要写书评

暂无评论

A Very Fast Trace-Driven Simulation Platform for Chip-Multiprocessors Architectural Explorations

引用

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2017年第11期28卷 3033-3045页

作者： Elrabaa, Muhammad E. S. Hroub, Ayman Mudawar, Muhamed F. Al-Aghbari, Amran Al-Asli, Mohammed Khayyat, Ahmad King Fahd Univ Petr & Minerals Comp Engn Dept Dhahran 31261 Saudi Arabia

Simulation is the main tool for computer architects and parallel application developers for developing new architectures and parallel algorithms on many-core machines. Simulating a many-core architecture represent a challenge to software simulators even with parallelization of these SW on multi-cores. field programmable gate arrays offer an excellent implementation platform due to inherent parallelism. Existing FPGA-based simulators however, are mostly execution-driven which consumes too many FPGA resources. Hence, they still trade-off accuracy with simulation speed as SW simulators do. In this work, an application-level trace-driven FPGA-based many-core simulator is presented. A parameterized Verilog template was developed that can generate any number of simulator tiles. The input trace has an architecturally agnostic format that is directly interpreted by the FPGA-based timing model to re-construct the execution events of the original application with accurate timing. This allows fitting a large number of simulation tiles on a single FPGA without sacrificing simulation speed or accuracy. Experimental results show that the simulator's average accuracy is similar to 14 percent with simulation speeds ranging from 100's of MIPs to over 2,200 MIPS for a 16-core target architecture. Hence, with accuracy similar to SW simulators, its speed is higher than all other FPGA-based simulators.

关键词： Trace-driven simulations hardware simulators chip-multiprocessors multithreading field-programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Optimization and performance evaluation of graphic processing units for voice processing

引用

JOURNAL OF ALGORITHMS & COMPUTATIONAL TECHNOLOGY 2017年第4期11卷 388-394页

作者： Sayadi, Fatma E. Bahri, Haythem Chouchene, Marwa Atri, Mohamed Monastir Univ Fac Sci Lab Elect & Microelect EE Environm St Monastir 5019 Tunisia

With the advancement in the device technology and parallel architecture, field-programmable gate arrays (FPGAs) can well perform the speech processing operation. FPGAs have very impressive results, despite their low operating frequency, by completely extracting the parallelism. Nevertheless, recent central processing unit and graphic processing unit (GPU) have also an inherent feature for high performance. In fact, recent GPUs enable dramatic increases in computing performance by harnessing great number of cores. In this context, we seek to analyze the performance of the linear prediction coding algorithm implementation on two different platforms: one based on the GPU NVIDIA GeForce GTX 480 and another on the FPGA Spartan-6. Subsequently, we try to apply several optimization strategies on those platforms. The experimental results highlight the relative robustness or weakness of both these platforms. The tests prove that, for several samples, GPU manages speedups of up to 4x compared to the FPGA and around 48x compared to a sequential execution.

关键词： Linear predictive coding graphic processing unit field-programmable gate arrays optimization strategies shared memory

来源：评论

学校读者我要写书评

暂无评论

Learning accelerator of deep neural networks with logarithmic quantization

Learning accelerator of deep neural networks with logarithmi...

引用

International Congress on Advanced Applied Informatics

作者： Takeo Ueki Keisuke Iwai Takashi Matsubara Takakazu Kurokawa Department of Computer Science National Defence Academy of Japan

ISBN: (纸本)9781538674482;9781538674475

In recent years, Deep Neural Network (DNN)s have become widely spread. Several high-throughput hardware implementations for DNNs have been proposed. One of the key points for hardware implementations of DNNs is to reduce their circuit scale because DNNs require a lot of product-sum operations. Previous papers presented some accelerators using logarithmic quantization to reduce circuit scale by replacing multipliers with shifters. However, most of them are implemented only for inference, and we can find no previous paper using logarithmic quantization for learning. In this paper, a learning accelerator using a logarithmic quantization is proposed. The accelerator uses a stochastic approach for logarithmic quantization. It enables DNNs to learn using logarithmic quantization values. Preliminary evaluation confirmed that DNNs using the proposed method can achieve recognition of MNIST with an accuracy of 97.8%. This evaluation result proves that the proposed method can be used for learning DNNs. The accelerator using the proposed method is implemented on a field-programmable gate array (FPGA) (Xilinx Zynq7020) and synthesized with Xilinx Vivado 2017.1. As a result, it is confirmed to have 2.9 times smaller circuit scale compared with the same FPGA accelerator using 32-bit fixed point number.

关键词： Neural networks Logarithmic computation Approximate computing field-programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

AutoRARE: An Automated Tool For Generating FPGA-Based Multi-Memory Hardware Accelerators For Compute-Intensive Applications

AutoRARE: An Automated Tool For Generating FPGA-Based Multi-...

引用

IEEE International Performance Computing and Communications Conference

作者： Shrikant S. Jadhav Clay Gloster Christopher Doss Youngsoo Kim Jannatun Naher Dept. of Electrical and Computer Engineering North Carolina A&T State University Greensboro NC Dept. of Computer Systems Technology North Carolina A&T State University Greensboro NC Dept. of Electrical and Computer Engineering Bradley University Peoria IL

ISBN: (纸本)9781538668092;9781538668085

In this paper, we present AutoRARE, a Java-based automated design tool for generating field programmable gate Array (FPGA)-based hardware accelerators. AutoRARE automatically generates all VHDL models needed to build/synthesize a processor specifically tailored for each application. The user needs only provide the VHDL description of a special-purpose floating point Arithmetic Logic Unit (ALU) or function core. The tool generates the VHDL description for the memory interface, memory controller, host processor interface, and the application specific processor. We also present details of the FPGA-based multi-memory hardware accelerator for accelerating computationally intensive applications, generated using AutoRARE. The multi-memory hardware accelerator is highly pipelined and able to simultaneously read and write multiple floating point values from multiple memories. The multi-memory architecture is the key to providing hardware accelerators that execute 10X-100X faster than typical multi-core processors. The Taylor Series expansion of the sine/cosine function is used as an application to demonstrate the merits of the multi-memory hardware accelerator. In our experiments, we executed the Taylor Series in software and compared execution times with an FPGA-based hardware implementation. Our experiments show that the FPGA-based multi-memory Taylor Series hardware accelerator is 481X faster than software executing the Taylor Series on a typical server.

关键词： Reconfigurable computing field-programmable gate arrays field-programmable custom computing machines High performance computing Multi-Memory architecture Multiple memory banks

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：