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NASA Technical Reports Server (Ntrs) 20040171246: Printed Circuit Board Design with Hdl Designer

2017年

NASA Technical Reports Server (Ntrs) 20040171246: Printed Circuit Board Design with Hdl Designer by NASA Technical Reports Server (Ntrs); published by

关键词： (ntrs) 20040171246: alternating current board circuit circuit boards computer aided design costs design direct current field-programmable gate arrays hardware description languages lafourcade, teresa nasa technical reports server (ntrs) printed circuits simulation systems engineering vhsic (circuits) winkert, thomas k.

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NASA Technical Reports Server (Ntrs) 20040171233: a Discussion of Using a Reconfigurable Processor to Implement the Discrete Fourier Transform

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2017年

NASA Technical Reports Server (Ntrs) 20040171233: a Discussion of Using a Reconfigurable Processor to Implement the Discrete Fourier Transform by NASA Technical Reports Server (Ntrs); published by

关键词： (ntrs) 20040171233: algorithms architecture (computers) data processing discrete discrete functions discussion field-programmable gate arrays floating point arithmetic fourier fourier transformation hardware description languages nasa technical reports server (ntrs) reconfigurable hardware white, michael j.

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NASA Technical Reports Server (Ntrs) 20060017831: a Plug and Play Gnc Architecture Using Fpga Components

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2017年

NASA Technical Reports Server (Ntrs) 20060017831: a Plug and Play Gnc Architecture Using Fpga Components by NASA Technical Reports Server (Ntrs); published by

关键词： (ntrs) 20060017831: aircraft control architecture architecture (computers) autonomy avionics components computer programs field-programmable gate arrays guidance (motion) ippoloito, c. kaneshige, j. krishnakumar, k. nasa technical reports server (ntrs) navigation pires, c. real time operation reconfigurable hardware reports software engineering waterman, r.

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NASA Technical Reports Server (Ntrs) 20050237977: Design of the Protocol Processor for the Robus-2 Communication System

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2017年

NASA Technical Reports Server (Ntrs) 20050237977: Design of the Protocol Processor for the Robus-2 Communication System by NASA Technical Reports Server (Ntrs); published by

关键词： (ntrs) 20050237977: architecture (computers) communication communication networks computer systems design data processing equipment design fault tolerance field-programmable gate arrays hardware hardware description languages malekpour, mahyar r. miner, paul s. nasa technical reports server (ntrs) point to point communication processor protocol (computers) redundancy synchronism time division multiple access torres-pomales, wilfredo

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NASA Technical Reports Server (Ntrs) 20050206351: a Vhdl Core for Intrinsic Evolution of Discrete Time Filters with Signal Feedback

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2017年

NASA Technical Reports Server (Ntrs) 20050206351: a Vhdl Core for Intrinsic Evolution of Discrete Time Filters with Signal Feedback by NASA Technical Reports Server (Ntrs); published by

关键词： (ntrs) 20050206351: digital systems discrete dutton, kenneth evolution feedback field-programmable gate arrays filters gwaltney, david a. hardware description languages nasa technical reports server (ntrs) robustness (mathematics) signal analyzers signal generators signal processing vhsic (circuits)

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Efficient Realization of Fixed-Point Binary and Ternary Adders on FPGAs

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2017年第4期26卷 1750053-1750053页

作者： Khurshid, Burhan Naaz, Roohie Natl Inst Technol Srinagar Dept Comp Sci & Engn Srinagar 190006 Jammu & Kashmir India

Binary and ternary adders are frequently used to speed-up many digital signal processing (DSP) operations like multiplication, compression, filtering, convolution, etc. FPGA realization of these circuits uses a combination of look-up tables (LUTs) and carry-chains. Alternatively, inbuilt operators and parameterizable IP cores provide an efficient means of implementing these circuits. However, the realization is not optimal in the sense that the full potential of the underlying resources is not utilized. In this paper, we use technology-dependent approaches to restructure the Boolean networks corresponding to these circuits. The restructured networks are then mapped optimally onto the FPGA fabric using minimum possible resources. Our analysis shows a subsequent speed-up in the performance of these circuits when compared to different conventional and existing approaches.

关键词： Circuit optimization field-programmable gate arrays fixed-point arithmetic technology-dependent optimizations

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FPGA implementation of logarithmic versions of Baum-Welch and Viterbi algorithms for reduced precision hidden Markov models

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BULLETIN OF THE POLISH ACADEMY OF SCIENCES-TECHNICAL SCIENCES 2017年第6期65卷 935-947页

作者： Pietras, M. Klesk, P. West Pomeranian Univ Technol Fac Comp Sci & Informat Technol 49 Zolnierska St Szczecin Poland

This paper presents a programmable system-on-chip implementation to be used for acceleration of computations within hidden Markov models. The high level synthesis (HLS) and "divide-and-conquer" approaches are presented for parallelization of Baum-Welch and Viterbi algorithms. To avoid arithmetic underflows, all computations are performed within the logarithmic space. Additionally, in order to carry out computations efficiently - i.e. directly in an FPGA system or a processor cache - we postulate to reduce the floating-point representations of HMMs. We state and prove a lemma about the length of numerically unsafe sequences for such reduced precision models. Finally, special attention is devoted to the design of a multiple logarithm and exponent approximation unit (MLEAU). Using associative mapping, this unit allows for simultaneous conversions of multiple values and thereby compensates for computational efforts of logarithmic-space operations. Design evaluation reveals absolute stall delay occurring by multiple hardware conversions to logarithms and to exponents, and furthermore the experiments evaluation reveals HMMs computation boundaries related to their probabilities and floating-point representation. The performance differences at each stage of computation are summarized in performance comparison between hardware acceleration using MLEAU and typical software implementation on an ARM or Intel processor.

关键词： hidden Markov models numerical stability Viterbi algorithm parallel architectures field-programmable gate arrays

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System-on-chip field-programmable gate array design for onboard real-time hyperspectral unmixing

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JOURNAL OF APPLIED REMOTE SENSING 2016年第1期10卷

作者： Nascimento, Jose M. P. Vestias, Mario Inst Politecn Lisboa Inst Super Engn Lisboa Rua Conselheiro Emidio Navarro P-1959007 Lisbon Portugal Inst Telecomunicacoes Lisbon Portugal Inst Engn Sistemas & Comp Invest & Desenvolviment Lisbon Portugal

Hyperspectral instruments have been incorporated in satellite missions, providing large amounts of data of high spectral resolution of the Earth surface. This data can be used in remote sensing applications that often require a real-time or near-real-time response. To avoid delays between hyperspectral image acquisition and its interpretation, the last usually done on a ground station, onboard systems have emerged to process data, reducing the volume of information to transfer from the satellite to the ground station. For this purpose, compact reconfigurable hardware modules, such as field-programmable gate arrays (FPGAs), are widely used. This paper proposes an FPGA-based architecture for hyperspectral unmixing. This method based on the vertex component analysis (VCA) and it works without a dimensionality reduction preprocessing step. The architecture has been designed for a low-cost Xilinx Zynq board with a Zynq-7020 system-on-chip FPGA-based on the Artix-7 FPGA programmable logic and tested using real hyperspectral data. Experimental results indicate that the proposed implementation can achieve real-time processing, while maintaining the methods accuracy, which indicate the potential of the proposed platform to implement high-performance, low-cost embedded systems, opening perspectives for onboard hyperspectral image processing. (C) 2016 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： hyperspectral unmixing vertex component analysis field-programmable gate arrays onboard processing real time

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FPGA-based test bed for measurement of AM/AM and AM/PM distortion and modeling memory effects in RF PAs

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INTEGRATION-THE VLSI JOURNAL 2016年 52卷 291-300页

作者： Cruz Nunez-Perez, Jose Ricardo Cardenas-Valdez, Jose Montoya-Villegas, Katherine Apolinar Reynoso-Hernandez, J. Raul Loo-Yau, Jose Gontrand, Christian Tlelo-Cuautle, Esteban Inst Politecn Nacl Ctr Invest & Desarrollo Tecnol Digital IPN CITEDI Tijuana 22150 Baja California Mexico Ctr Sci Res & Higher Educ Ensenada CICESE Dept Elect & Telecommun Ensenada 22860 Baja California Mexico Inst Politecn Nacl IPN CINVESTAV Ctr Invest & Estudios Avanzados Zapopan 45019 Jalisco Mexico Inst Natl Sci Appl Lyon INSA Lyon UMR CNRS 5270 INL F-69621 Villeurbanne France INAOE Puebla 72840 Mexico

Using a field-programmable gate array (FPGA) development board, a digital signal processor (DSP) builder, and the phase-to-amplitude conversion principle, a low-cost system for measuring the amplitude-to-amplitude (AM/AM) and amplitude-to-phase (AM/PM) distortion curves of radio frequency (RF) power amplifiers (PAs) is presented. The state of the art based on the measurements and preliminary studies of AM/AM and AM/PM distortion curves is discussed. A full digital control of the test bed simulated/emulated in Matlab/Simulink is introduced to recalculate the known AM/AM and AM/PM measurements stored as look-up table (LUT). Finally, the low-cost system comprises the memory polynomial model (MPM) that involves the nonlinearity order and memory effects of real PAs. (C) 2015 Elsevier B.V. All rights reserved.

关键词： AM/AM AM/PM field-programmable gate arrays Memory modeling Memory polynomial model Power amplifier RF Test bed

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Design of a Compact Sound Localization Device on a Stand-Alone FPGA-Based Platform

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2016年第11期E99D卷 2682-2693页

作者： Kugler, Mauricio Tossavainen, Teemu Kuroyanagi, Susumu Iwata, Akira Nagoya Inst Technol Dept Comp Sci & Engn Nagoya Aichi 4668555 Japan Aalto Univ Sch Sci Dept Comp Sci & Engn Konemiehentie 2 Espoo 02150 Finland

Sound localization systems are widely studied and have several potential applications, including hearing aid devices, surveillance and robotics. However, few proposed solutions target portable systems, such as wearable devices, which require a small unnoticeable platform, or unmanned aerial vehicles, in which weight and low power consumption are critical aspects. The main objective of this research is to achieve real-time sound localization capability in a small, self-contained device, without having to rely on large shaped platforms or complex microphone arrays. The proposed device has two surface-mount microphones spaced only 20 mm apart. Such reduced dimensions present challenges for the implementation, as differences in level and spectra become negligible, and only time-difference of arrival (TDoA) can be used as a localization cue. Three main issues have to be addressed in order to accomplish these objectives. To achieve real-time processing, the TDoA is calculated using zero-crossing spikes applied to the hardware-friendly Jeffers model. In order to make up for the reduction in resolution due to the small dimensions, the signal is upsampled several-fold within the system. Finally, a coherence-based spectral masking is used to select only frequency components with relevant TDoA information. The proposed system was implemented on a field-programmable gate array (FPGA) based platform, due to the large amount of concurrent and independent tasks, which can be efficiently parallelized in reconfigurable hardware devices. Experimental results with white-noise and environmental sounds show high accuracies for both anechoic and reverberant conditions.

关键词： sound localization time difference of arrival compact device real-time field-programmable gate arrays

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