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Long-Range Pulse Interactions in Unclocked FPGAs

IEEE ACCESS 2023年 11卷 41158-41166页

作者： Cohen, Seth D. Fendley, Casey M. Beal, Aubrey N. Corron, Ned J. Kratos SRE Inc Birmingham AL 35211 USA Univ Alabama Huntsville Dept Elect & Comp Engn Huntsville AL 35899 USA

Evidence of long-range interactions between logic transitions in unclocked FPGA circuits is reported. The relative positions of pulses traveling in digital feedback loops are observed to dynamically interact and move to equal spacing over long timescales. We confirm the presence of this interaction over different FPGA supply voltages and hypothesize the pulse interactions are due to current draw in the power distribution network of the FPGA. This pulse interaction effect is observed for different FPGA families and manufacturers, including Altera and Xilinx, and has been tested using both look-up table (LUT) and carry chain (CC) logic to realize the feedback delays.

关键词： field programmable gate arrays Feedback loop Delays Transient analysis Steady-state Couplings Table lookup Asynchronous circuits feedback circuits field-programmable gate arrays pulse circuits pulse interactions non-blocking delay lines oscillators network dynamics transient analysis

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A hardware accelerator for quantile estimation of network packet attributes 27

A hardware accelerator for quantile estimation of network pa...

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27th Euromicro Conference on Digital System Design

作者： Gallardo-Pavesi, Carolina Fernandez, Yaime Soto, Javier E. Hernandez, Cecilia Figueroa, Miguel Univ Concepcion Dept Elect Engn Concepcion Chile Univ Concepcion Dept Comp Sci Concepcion Chile Ctr Biotechnol & Bioengn CeBiB Santiago Chile Adv Ctr Elect & Elect Engn AC3E Santiago Chile

ISBN: (纸本)9798350380392;9798350380385

Measuring statistical properties of network traffic can improve our understanding of traffic distribution and help us detect short and long-term anomalies. However, computing the exact value of these properties requires significant storage and computation, which limits their application in high-speed networks. Hardware accelerators provide the computational power to process a large sequence of network packets with high throughput and low latency, but their performance is ultimately limited by the amount of on-chip memory available on the device. Consequently, researchers have proposed sketch-based algorithms to estimate properties of a data stream with sublinear memory and theoretical estimation error bounds. In this paper, we present a streaming algorithm and hardware accelerator for quantile estimation, which is based on the architecture of the KLL sketch. Implemented on an AMD Virtex XCU55 UltraScale+ FPGA, the accelerator operates at a clock frequency of 356 MHz, thereby achieving a minimum line rate of 182 Gbps and a maximum estimation latency of 4.33 mu s. When processing a set of 10 real traffic traces of up to 123 million packets, the accelerator estimates 1000 packet-size quantiles per trace with a median error of 0.39% or less, and a maximum error of 1.3% or less across all traces.

关键词： Quantile estimation network measurement hardware acceleration sketch-based algorithms field-programmable gate arrays

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A Novel Delay-Aware Packing Algorithm for FPGA Architecture Using RFET 67

A Novel Delay-Aware Packing Algorithm for FPGA Architecture ...

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67th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Lu, Sheng Shang, Liuting Jung, Sungyong Zhang, Yichen Pan, Chenyun Univ Texas Arlington Dept Elect Engn Arlington TX 76019 USA

ISBN: (纸本)9798350387186;9798350387179

Reconfigurable devices are gaining increasing attention as a viable alternative and supplementary solution to traditional CMOS technology. In this paper, we develop a more efficient 2-input look-up table (LUT) based on the reconfigurable field-effect transistors (RFETs), leading to a smaller transistor usage and a smaller critical path delay. The cells are organized into regular matrices, known as MClusters, with a fixed interconnection pattern to replace LUTs in field-programmable gate arrays (FPGAs). To improve the efficiency of utilizing this structure, we design a SAT-based delay-aware packing algorithm to better utilize logical gates for the MCluster structure. Finally, we combine this algorithm with FPGA simulation tools to form a comprehensive benchmarking flow. A series of benchmark tests show that under the optimal design, up to 35% and 30% reduction can be achieved in delay and energy-delay product (EDP), respectively, compared to the traditional CMOS FPGAs.

关键词： Reconfigurable FET field-programmable gate arrays look-up table partitioning algorithm packing algorithm technology mapping performance benchmarking

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Square Kilometre Array Low Atomic commercial off-the-shelf correlator and beamformer

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JOURNAL OF ASTRONOMICAL TELESCOPES INSTRUMENTS AND SYSTEMS 2022年第1期8卷

作者： Hampson, Grant A. Bunton, John D. Humphrey, David Bengston, Keith J. Jourjon, Guillaume Bolin, Andrew B. Chen, Yuqing Troup, Euan R. Babich, Giles C. van Aardt, Jason C. CSIRO Space & Astron Marsfield NSW Australia

The Square Kilometre Array Low is a next generation radio telescope, consisting of 512 antenna stations spread over 65 km, to be built in Western Australia. The correlator and beamformer (CBF) design is central to the telescope signal processing. CBF receives 6 Tera-bits-per-second (Tbps) of station data continuously and processes it in real time with a compute load of 2 Peta-operations-per-second (Pops). The correlator calculates up to 22 million cross products between all pairs of stations, whereas the beamformers (BFs) coherently sum station data to form more than 500 beams. The output of the correlator is up to 7 Tbps, and the BF 2 Tbps. The design philosophy, called "Atomic COTS," is based on commercial off-the-shelf (COTS) hardware. Data routing is implemented in network switches programmed using the Programming Protocol-Independent Packet Processors (P4) language and the signal processing occurs in COTS field-programmable gate array (FPGA) cards. The P4 language allows routing to be determined from the metadata in the Ethernet packets from the stations. That is, metadata describing the contents of the packet determines the routing. Each FPGA card inputs a fraction of the overall bandwidth for all stations and then implements the processing needed to generate complete science data products. Generation of complete science products in a single FPGA is named here as Atomic processing. A Tango distributed control system configures the multitude of processing modes as well as maintaining the overall health of the CBF system hardware. The resulting 6 Tbps in and 9 Tbps out, 2 Pops Atomic COTS network attached accelerator occupies five racks and consumes 60 kW. (C) The Authors. Published by SPIE under a Creative Commons Attribution 4.0 International License.

关键词： antenna arrays correlators beam steering accelerator architectures communication switching field-programmable gate arrays

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Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini Accelerator 27

Efficient Edge AI: Deploying Convolutional Neural Networks o...

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27th Euromicro Conference on Digital System Design

作者： Peccia, Federico Nicolas Pavlitska, Svetlana Fleck, Tobias Bringmann, Oliver FZI Res Ctr Informat Technol Karlsruhe Germany Univ Tubingen Tubingen Germany Karlsruhe Inst Technol Karlsruhe Germany

ISBN: (纸本)9798350380392;9798350380385

The growing concerns regarding energy consumption and privacy have prompted the development of AI solutions deployable on the edge, circumventing the substantial CO2 emissions associated with cloud servers and mitigating risks related to sharing sensitive data. But deploying Convolutional Neural Networks (CNNs) on non-off-the-shelf edge devices remains a complex and labor-intensive task. In this paper, we present an end-to-end workflow for the deployment of CNNs on field programmable gate arrays (FPGAs) using the Gemmini accelerator, which we modified for efficient implementation on FPGAs. We describe how we leverage the use of open-source software on each optimization step of the deployment process, the customizations we added to them and their impact on the final system's performance. We were able to achieve real-time performance by deploying a YOLOv7 model on a Xilinx ZCU102 FPGA with an energy efficiency of 36.5 GOP/s/W. Our FPGA-based solution demonstrates superior power efficiency compared with other embedded hardware devices and even outperforms other FPGA reference implementations. Finally, we present how this kind of solution can be integrated into a wider system, by testing our proposed platform in a traffic monitoring scenario.

关键词： Convolutional Neural Networks field-programmable gate arrays FPGA accelerator Edge Computing Deployment Workflow Energy Efficiency

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Enhancing the Computational Efficiency of Genetic Programming Through Alternative Floating-Point Primitives 18th

Enhancing the Computational Efficiency of Genetic Programmin...

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18th International Conference on Parallel Problem Solving from Nature (PPSN)

作者： Crary, Christopher Burlacu, Bogdan Banzhaf, Wolfgang Univ Florida Dept Elect & Comp Engn Gainesville FL 32610 USA Univ Appl Sci Upper Austria Heurist & Evolutionary Algorithms Lab Hagenberg Upper Austria Austria Michigan State Univ Dept Comp Sci & Engn E Lansing MI 48824 USA

ISBN: (纸本)9783031700545;9783031700552

Can evolution operate effectively with noisy floating-point function primitives? In this paper, we are motivated by recent work that aims to accelerate genetic programming (GP) through specialized hardware and field-programmable gate arrays (FPGAs), for which it has been shown that additional performance and power/energy benefits could likely be achieved with floating-point function primitives that trade off enhanced computational efficiency for increased error. Although GP is known to be robust in filtering out certain forms of noise (e.g., within input data), it is not immediately clear that less-accurate function primitives would be viable for GP, since GP formulates arbitrary compositions of its primitives, which could potentially compound error to a prohibitive level. In addition, when introducing more complex forms of computation, such as function differentiation and local optimization techniques, it is not readily apparent that using rougher primitive implementations would be tenable. Here, we address both situations by employing the state-of-the-art CPU-based Operon tool on a diverse set of 15 regression problems, and we show that tree-based GP is capable of evolving very similar (and sometimes better) results with alternative high-performance approximations of standard function primitives, while often also allowing for faster CPU runtimes. Most importantly, in the context of specialized hardware, we conclude that our proposed techniques can likely allow for significant speedups over general-purpose computing platforms, as well as improved power/energy efficiency.

关键词： Genetic programming field-programmable gate arrays Approximate computing Floating-point Symbolic regression

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Design and Implementation of Asynchronous Processor on FPGA

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IEEE ACCESS 2022年 10卷 118370-118379页

作者： Shin, Ziho Oh, Myeong-Hoon Elect & Telecommun Res Inst ETRI Affiliated Inst Daejeon South Korea Honam Univ Dept Comp Engn Gwangju South Korea

Low-power and fault-tolerant features for microprocessors have been recognized as two of the greatest concerns in applications for edge devices. In this study, we propose asynchronous circuit design techniques for field-programmable gate arrays (FPGA) that can fundamentally overcome the drawbacks of conventional synchronous circuit designs. We used commercial FPGAs and implemented an asynchronous MSP430 microprocessor using the proposed technique. We also introduce an interfacing architecture between the synchronous block memory and asynchronous core to support the congeniality of the commercial embedded processor and the asynchronous core. Furthermore, we analyze a compiler for MSP430 and adapt its result to achieve a high-level development environment for asynchronous MSP430. The experimental results showed that the asynchronous MSP430 consumes 62.3% less power than its synchronous counterpart and has significant fault tolerance compared to the synchronous MSP430 under unstable supply voltage conditions. Additionally, the asynchronous MSP430 emitted 13% less electromagnetic noise at the working frequency.

关键词： Asynchronous circuits field-programmable gate arrays microprocessors

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RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients

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IEEE ACCESS 2022年 10卷 19215-19231页

作者： Nagornov, Nikolay N. Lyakhov, Pavel A. Valueva, Maria V. Bergerman, Maxim, V North Caucasus Fed Univ Dept Math Modeling Stavropol 355017 Russia North Caucasus Fed Univ North Caucasus Ctr Math Res Stavropol 355017 Russia

Medical imaging using different modalities has many problems. The main ones are low informativeness, various distortion noises, and a large amount of information. Fusion, denoising, and visual data compression are used to solve them in practice. Discrete wavelet transform is one way to implement various fusion, denoising, and compression methods for 2D and 3D medical image processing. Medical imaging systems produce increasingly accurate images with scanning technology and digital devices development. These images have improved quality using both higher spatial resolutions and color bit-depth. Processing a large volume of medical imaging data requires considerable resources and processing time. Modern wavelet-based devices for medical image processing do not meet the current performance demand. Hardware accelerators are being designed to solve this problem. This paper proposes new (field-programmable gate array) FPGA accelerators using wavelet processing (WP) with scaled filter coefficients (SFC) and parallel computing in residue number system (RNS) to improve the performance of high-quality 3D medical image WP systems. The computational complexity is reduced using the developed WP method with SFC and the proposed wavelet filter coefficients scaling algorithm. Parallel computing is organized in RNS using moduli sets of a particular type. Hardware implementation of 3D medical image WP using the proposed FPGA accelerators increases device performance by 2.89-3.59 times, increasing the hardware resources by 1.18-3.29 times compared to state-of-the-art solutions. The device performance improvement is achieved while maintaining high-quality 3D medical image processing in peak signal-to-noise ratio terms.

关键词： Biomedical imaging Three-dimensional displays Discrete wavelet transforms Performance evaluation field programmable gate arrays Image coding Wavelet transforms Medical image processing discrete wavelet transform scaled filter coefficients residue number system high-performance computing hardware accelerator field-programmable gate arrays

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Reconfigurable High-Performance Computing of Sparse Linear Algebra

Reconfigurable High-Performance Computing of Sparse Linear A...

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作者： Bank Tavakoli, Erfan Arizona State University

学位级别：Ph.D., Doctor of Philosophy

This thesis presents novel software/hardware co-design methodologies aimed at accelerating sparse linear algebra applications within the realm of High-Performance Computing (HPC). The motivation stems from the limitations of conventional CPU- and GPU-based solutions for sparse linear algebra, which are hindered by fixed hardware architecture and memory hierarchy, frequent off-chip memory access, and high energy consumption. In response, this work explores the deployment of field-programmable gate arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs) to overcome these challenges through their customized nature, offering performance and energy efficiency gains. The scope of the thesis is divided into three main parts: firstly, it introduces a framework that combines an FPGA computational kernel with a novel scheduling algorithm running on a host processor for accelerating the supernodal multifrontal algorithm for sparse Cholesky factorization. This approach minimizes off-chip memory access and on-chip memory requirements by efficiently managing data dependencies and enhancing data locality. Secondly, it presents FSpGEMM, an OpenCL-based framework for accelerating general sparse matrix-matrix multiplication on FPGAs. FSpGEMM exploits a new compressed sparse vector format (CSV) and a custom buffering scheme tailored to Gustavson's algorithm, significantly improving computational performance by optimizing memory access patterns. Additionally, a row reordering technique is utilized to increase the data reuse enabled by the CSV format. Lastly, the thesis proposes an ASIC design for Sparse Tensor Core, which utilizes a Hardware Merge Sorter to increase parallelism in processing units without compromising operating frequency, offering a high-speed solution for sparse linear algebra operations. In summary, the thesis addresses the challenges of implementing sparse linear algebra algorithms on FPGAs and ASICs, such as the complexity of data dependencies and the n

关键词： High-Performance Computing Sparse linear algebra Sparse vector format field-programmable gate arrays Supernodal multifrontal algorithm

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Reconfigurable content-addressable memory (CAM) on FPGAs: A tutorial and survey

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FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE 2022年 128卷 451-465页

作者： Irfan, Muhammad Sanka, Abdurrashid Ibrahim Ullah, Zahid Cheung, Ray C. C. City Univ Hong Kong Dept Elect Engn Hong Kong Peoples R China Ghulam Ishaq Khan Inst Engn Sci & Technol Fac Elect Engn Topi Pakistan Inst Appl Sci & Technol Pak Austria Fachhsch Haripur Pakistan

Content-addressable memory (CAM) is a massively parallel searching device that returns the address of a given search input in one clock cycle. field-programmable gate array (FPGA)-based CAMS are becoming popular due to their applications in the latest networking systems, e.g., software-defined networks (SDNs) leading to upcoming 5G networks. Ternary CAM (TCAM) implements a routing table in a network router to classify and forward data packets where don't care bits (X-bits) correspond to multiple addresses. FPGAs do not have a hard-core CAM, although it is a prime element in networking applications. This paper serves as a comprehensive survey on FPGA-based CAM/TCAMs implemented using block random-access memory (BRAM), lookup table RAM (LUTRAM), and flip-flops (FFs). BRAM-based TCAM suffers from the pre-processing of mapping data, requires the data to be in a specific order in some cases, and has a large SRAM/TCAM bit ratio. LUTRAM-based CAM/TCAM suffers from wide bit-wise ANDing, high routing complexity, but has a small SRAM/TCAM bit ratio of 14 compared to 16 in the case of BRAM-based TCAM. Shallow and wide RAM blocks are required to implement large-size RAM-based TCAMs (BRAM-based and LUTRAM-based TCAMs). FF-based TCAMs use FFs as their memory elements and have reduced hardware costs per TCAM bit. However, due to the routing complexity, it suffers from scalability and a large amount of power consumption. The update latency of BRAM-based TCAM and LUTRAM-based TCAM is proportional to the depth of BRAM and LUTRAM, respectively. However, FF-based CAM updates in 1 or 2 clock cycles depending on the availability of input/output pins on target FPGA. (C) 2021 Published by Elsevier B.V.

关键词： field-programmable gate arrays Content-addressable memory Reconfigurable computing Network router Random-access memory SRAM-based TCAM

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