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Extensible FlexRay Communication Controller for FPGA-Based Automotive Systems

IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY 2015年第2期64卷 453-465页

作者： Shreejith, Shanker Fahmy, Suhaib A. Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore TUM CREATE Singapore 138602 Singapore

Modern vehicles incorporate an increasing number of distributed compute nodes, resulting in the need for faster and more reliable in-vehicle networks. Time-triggered protocols such as FlexRay have been gaining ground as the standard for high-speed reliable communications in the automotive industry, marking a shift away from the event-triggered medium access used in controller area networks (CANs). These new standards enable the higher levels of determinism and reliability demanded from next-generation safety-critical applications. Advanced applications can benefit from tight coupling of the embedded computing units with the communication interface, thereby providing functionality beyond the FlexRay standard. Such an approach is highly suited to implementation on reconfigurable architectures. This paper describes a field-programmable gate array (FPGA)-based communication controller (CC) that features configurable extensions to provide functionality that is unavailable with standard implementations or off-the-shelf devices. It is implemented and verified on a Xilinx Spartan 6 FPGA, integrated with both a logic-based hardware ECU and a fully fledged processor-based electronic control unit (ECU). Results show that the platform-centric implementation generates a highly efficient core in terms of power, performance, and resource utilization. We demonstrate that the flexible extensions help enable advanced applications that integrate features such as fault tolerance, timeliness, and security, with practical case studies. This tight integration between the controller, computational functions, and flexible extensions on the controller enables enhancements that open the door for exciting applications in future vehicles.

关键词： Automotive systems field-programmable gate arrays networks

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An embedded architecture for real-time object detection in digital images based on niching particle swarm optimization

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JOURNAL OF REAL-TIME IMAGE PROCESSING 2015年第1期10卷 75-89页

作者： Mehmood, Shahid Cagnoni, Stefano Mordonini, Monica Khan, Shoab Ahmad Ctr Adv Studies Engn Islamabad Pakistan Univ Parma Dept Informat Engn I-43100 Parma Italy

Particle swarm optimization (PSO) is an efficient population-based optimization technique. Niching is introduced into PSO to deal with multimodal problems, and converge onto the largest possible number of minima. In this paper, a niching PSO algorithm is described, which targets the imaging domain;our niching PSO enhances the fitness of a particle dynamically, based on the current position of the particle's neighbors, while also contemplating the chance of stopping exploration by halting a particle over favorable regions of the fitness landscape. It also caters for repulsion among closely located neighbors, which induces the particles to spread over the region of interest instead of converging onto a single punctual optimum. Based on this technique, an architecture is proposed and implemented for detecting objects in digital images. The new architecture, being efficient and portable, can be used in embedded computer vision and pattern recognition applications. We have assessed the architecture performance in the real-world task of detecting license plates in digital images, an instance of the more general class of object detection problems for which it has been designed. In doing so, we have compared our results with respect to both a corresponding sequential implementation and a standard computer implementation of a classical algorithm which solves the same problem.

关键词： Niching particle swarm optimization Swarm intelligence field-programmable gate arrays Object detection

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Reconfigurable architecture for real-time image compression on-board satellites

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JOURNAL OF APPLIED REMOTE SENSING 2015年第1期9卷

作者： Manthey, Kristian Krutz, David Juurlink, Ben German Aerosp Ctr DLR Inst Opt Sensor Syst Opt Sensors & Elect D-12489 Berlin Germany Tech Univ Berlin Embedded Syst Architecture D-10587 Berlin Germany

A high-speed image compression architecture with region-of-interest (ROI) support and with flexible access to compressed data based on the Consultative Committee for Space Data Systems 122.0-B-1 image data compression standard is presented. Modifications of the standard permit a change of compression parameters and the reorganization of the bit stream after compression. An additional index of the compressed data is created, which renders it possible to locate individual parts of the bit stream. On request, stored images can be reassembled according to the application's needs and as requested by the ground station. Interactive transmission of the compressed data is possible such that overview images can be transmitted first followed by detailed information for the ROI. The architecture was implemented for a Xilinx Virtex-5QV and a single instance is able to compress images at a rate of 200 Mpx/s at a clock frequency of 100 MHz. The design ensures that all parts of the system have a high utilization and parallelism. A Virtex-5QV allows compression of images with a width of up to 4096 px without external memory. The power consumption of the architecture is similar to 4 W. This example is one of the fastest implementations yet reported and sufficient for future high-resolution imaging systems. (C) 2015 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： remote sensing image data compression field-programmable gate arrays focal plane assembly Consultative Committee for Space Data Systems Earth observation

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Comparative study of LDPC coding schemes and FPGA implementation for inter-vehicle communications

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ELECTRONICS LETTERS 2015年第16期51卷 1255-1256页

作者： Kiokes, G. Zountouridou, E. Hellen Air Force Acad Dept Elect Elect Power & Telecommun Dekeleia Air Base Dekeleia Attica Greece Natl Tech Univ Athens Sch Elect & Comp Engn Zografos Greece

A novel comparative study of different low-density parity-check (LDPC) coding algorithms and implementation issues through field-programmable gate arrays (FPGAs) technology for wireless vehicular applications is presented. A key development in LDPC codes is the iterative decoding algorithm which uses the belief propagation algorithm. A comprehensive investigation of the performance of different coding schemes was carried out. Four different decoding techniques were tested by computer-based simulations of messages modulated under the binary phase-shift keying modulation scheme and transmitted through a vehicular channel model. Finally, the best performance ratio against complexity algorithm was chosen to be implemented on a Xilinx FPGA platform.

关键词： field programmable gate arrays iterative decoding parity check codes phase shift keying FPGA implementation LDPC coding schemes belief propagation algorithm field-programmable gate arrays inter-vehicle communications iterative decoding algorithm low-density parity-check coding algorithm phase-shift keying modulation scheme vehicular channel model

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A Random Number Generator Using Ring Oscillators and SHA-256 as Post-Processing

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INTERNATIONAL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS 2015年第2期61卷 199-204页

作者： Loza, Szymon Matuszewski, Lukasz Jessa, Mieczyslaw Poznan Univ Tech Fac Elect & Telecommun Ul Polanka 3 PL-61131 Poznan Poland

Today, cryptographic security depends primarily on having strong keys and keeping them secret. The keys should be produced by a reliable and robust to external manipulations generators of random numbers. To hamper different attacks, the generators should be implemented in the same chip as a cryptographic system using random numbers. It forces a designer to create a random number generator purely digitally. Unfortunately, the obtained sequences are biased and do not pass many statistical tests. Therefore an output of the random number generator has to be subjected to a transformation called post-processing. In this paper the hash function SHA-256 as post-processing of bits produced by a combined random bit generator using jitter observed in ring oscillators (ROs) is proposed. All components - the random number generator and the SHA-256, are implemented in a single field programmable gate Array (FPGA). We expect that the proposed solution, implemented in the same FPGA together with a cryptographic system, is more attack-resistant owing to many sources of randomness with significantly different nominal frequencies.

关键词： random numbers cryptography ring oscillators hash functions field-programmable gate arrays

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SC Build: a computer-aided design tool for design space exploration of embedded central processing unit cores for field-programmable gate arrays

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IET COMPUTERS AND DIGITAL TECHNIQUES 2009年第1期3卷 24-32页

作者： Anderson, I. D. L. Khalid, M. A. S. Univ Windsor RCIM Dept Elect & Comp Engn Windsor ON N9B 3P4 Canada

A genetic algorithm-based design space exploration technique using parameterised cores is examined. A computer-aided design tool called SCBuild was developed which is capable of applying a genetic algorithm to a core's parameters, and generating hardware description language models of core variants. The tool can also compute estimates of a variant's area and critical path delay on a field-programmable gate array. Using this tool, several experiments were conducted using a soft-core processor with a large design space. It was concluded from these experiments that using a genetic algorithm to explore the design space of a parameterised core can help a designer make intelligent decisions regarding the assignment of values to the parameters of an embedded hardware platform.

关键词： hardware description language computer-aided design tool embedded central processing unit cores SC Build field-programmable gate arrays parameterised cores logic CAD hardware description languages microprocessor chips design space exploration soft-core processor genetic algorithm field programmable gate arrays genetic algorithms

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FPGA-based Time and Cost Effective Hamming Weight Comparators for Binary Vectors

FPGA-based Time and Cost Effective Hamming Weight Comparator...

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International Conference on Computer as a Tool (EUROCON), IEEE

作者： Sklyarov, Valery Skliarova, Iouliia Sudnitson, Alexander Kruus, Margus Univ Aveiro Dept Elect Telecommun & Informat IEETA P-3810193 Aveiro Portugal Tallinn Univ Technol Dept Comp Engn Tallinn Estonia

ISBN: (纸本)9781479985692

The paper shows that resources and performance of Hamming weight comparators for binary vectors significantly depend on available basic elements from which the comparators are built and, thus, to optimize the final circuits different design techniques need to be applied. The presented analysis of existing solutions clearly demonstrates that although they may be efficient for one platform (such as fully customized circuits), for another platform (such as FPGA) they become not advantageous at all. The paper suggests several, supplementing each other, Hamming weight counters and comparators based on optimized mapping of the circuits to FPGA look-up tables giving the best performance and the fewest resources compared to the best known alternatives. It is shown that the proposed methods are easily adjustable to a wide range of problem dimensions. Besides, the paper gives well-defined recommendations that enable the most appropriate circuit to be chosen for particular requirements such as the size of the vectors and the required performance. Final evaluations of the results have been done through prototyping in FPGAs and comparison with the best known alternatives.

关键词： field-programmable gate arrays Hamming weight counter Hamming weight comparator Parallel processing

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Advanced illumination control algorithm for medical endoscopy applications 2

Advanced illumination control algorithm for medical endoscop...

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Conference on Image Sensing Technologies - Materials, Devices, Systems, and Applications II

作者： Sousa, Ricardo M. Waeny, Martin Santos, Pedro Morgado-Dias, F. Univ Madeira P-9000390 Funchal Portugal Awaiba Lda P-9020105 Funchal Portugal Madeira Interact Technol Inst P-9020105 Funchal Portugal

ISBN: (纸本)9781628415971

CMOS image sensor manufacturer, AWAIBA, is providing the world's smallest digital camera modules to the world market for minimally invasive surgery and one time use endoscopic equipment. Based on the world's smallest digital camera head and the evaluation board provided to it, the aim of this paper is to demonstrate an advanced fast response dynamic control algorithm of the illumination LED source coupled to the camera head, over the LED drivers embedded on the evaluation board. Cost efficient and small size endoscopic camera modules nowadays embed minimal size image sensors capable of not only adjusting gain and exposure time but also LED illumination with adjustable illumination power. The LED illumination power has to be dynamically adjusted while navigating the endoscope over changing illumination conditions of several orders of magnitude within fractions of the second to guarantee a smooth viewing experience. The algorithm is centered on the pixel analysis of selected ROIs enabling it to dynamically adjust the illumination intensity based on the measured pixel saturation level. The control core was developed in VHDL and tested in a laboratory environment over changing light conditions. The obtained results show that it is capable of achieving correction speeds under 1 s while maintaining a static error below 3% relative to the total number of pixels on the image. The result of this work will allow the integration of millimeter sized high brightness LED sources on minimal form factor cameras enabling its use in endoscopic surgical robotic or micro invasive surgery.

关键词： Automatic Illumination Control CMOS Image Sensors LED Lighting Medical Imaging field-programmable gate arrays

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The hybrid reconfigurable system for high-performance computing 9

The hybrid reconfigurable system for high-performance comput...

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9th International Conference of Information and Communiation Technologies (AICT)

作者： Lyashov, M., V Alekseenko, J., V Bereza, A. N. Blanco, L. M. L. Tech Univ Inst Serv & Business Branch Don State Shakhty Russia

ISBN: (纸本)9781467368551

This work considers the problem of the GRID-computing concept application, where user computing resources are provided as a service. The prototype of hybrid reconfigurable system for high-performance computing is presented in this paper. The developed system will integrate CPUs, GPUs, and hardware FPGA based accelerators into a single environment, allowing scientists to conduct researches that require large-scale computations.

关键词： high performance computing reconfigurable systems hybrid systems GRID-computing hardware accelerators field-programmable gate arrays genetic algorithms

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A Tag Based Vector Reduction Circuit

A Tag Based Vector Reduction Circuit

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IEEE High Performance Extreme Computing Conference (HPEC)

作者： Wei, Ming Huang, Yi-hua Sun Yat Sen Univ Sch Informat Sci & Technol Guangzhou 510006 Guangdong Peoples R China

ISBN: (纸本)9781467392860

Fast and efficient vector reduction circuit is very important to the real time application. In this paper, a new tag based fully pipelined vector reduction circuit is proposed, which can concurrently handle multiple vectors input with arbitrary sequence. Meanwhile, the proposed circuit provides simple and efficient interface and access timing similar to a RAM. So it can be used in a broad range.

关键词： Vector reduction fully pipelined field-programmable gate arrays

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