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Conference on Applications of Digital Image Processing XXXVIII

作者： Cardenas, Javier Figueroa, Miguel Pezoa, Jorge E. Univ Concepcion Dept Elect Engn Concepcion Chile Univ Concepcion Ctr Opt & Photon Concepcion Chile

ISBN: (纸本)9781628417654

We present a custom digital architecture for bruised apple classification using hyperspectral images in the near infrared (NIR) spectrum. The algorithm classifies each pixel in an image into one of three classes: bruised, non bruised, and background. We extract two 5-element feature vectors for each pixel using only 10 out of the 236 spectral bands provided by the hyperspectral camera, thereby greatly reducing both the requirements of the imager and the computational complexity of the algorithm. We then use two linear-kernel support vector machine (SVM) to classify each pixel. Each SVM was trained with 504 windows of size 17 x 17-pixel taken from 14 hyperspectral images of 320 x 320 pixels each, for each class. The architecture then computes the percentage of bruised pixels in each apple in order to adequately classify the fruit. We implemented the architecture on a Xilinx Zynq Z-7010 field-programmable gate array (FPGA) and tested it on images from a NIR N17E push-broom camera with a frame rate of 25 fps, a band-pixel rate of 1.888 MHz, and 236 spectral bands between 900 and 1700 nanometers in laboratory conditions. Using 28-bit fixed-point arithmetic, the circuit accurately discriminates 95.2% of the pixels corresponding to an apple, 81% of the pixels corresponding to a bruised apple, and 96.4% of the background. With the default threshold settings, the highest false positive (FP) for a bruised apple is 18.7%. The circuit operates at the native frame rate of the camera, consumes 67 mW of dynamic power, and uses less than 10% of the logic resources on the FPGA.

关键词： Hyperspectral imaging Computer vision Food quality control field-programmable gate arrays Support-vector machine

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Noise-Robust Hardware Implementation of Neural Networks

Noise-Robust Hardware Implementation of Neural Networks

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International Joint Conference on Neural Networks (IJCNN)

作者： Canals, Vincent Alomar, Miquel L. Morro, Antoni Oliver, Antoni Rossello, Josep L. Univ Balearic Isl Dept Phys Palma de Mallorca Spain

ISBN: (纸本)9781479919598

Efficient hardware implementations of neural networks are of high interest. Stochastic computing is an alternative to conventional digital logic that allows to exploit the intrinsic parallelism of neural networks using few hardware resources. We present a new stochastic methodology that extends the capabilities of classical stochastic computing. In particular, the present approach exhibits practically total immunity to noise. This is demonstrated evaluating the influence of the noise on the system's performance for a mathematical regression task.

关键词： Neural networks Probabilistic logic Stochastic systems Computational intelligence field-programmable gate arrays Hardware implementation Noise robustness

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Noise-Robust Hardware Implementation of Neural Networks

Noise-Robust Hardware Implementation of Neural Networks

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International Joint Conference on Neural Networks

作者： Vincent Canals Miquel L. Alomar Antoni Morro Antoni Oliver Josep L. Rossello Physics Department University of Balearic Islands Palma de Mallorca Spain

ISBN: (纸本)9781479919611

关键词： Neural networks Probabilistic logic Stochastic systems Computational intelligence field-programmable gate arrays Hardware implementation Noise robustness Neural network Noise robustness field programmable gate arrays Probabilistic logic Artificial Intelligence Computational intelligence stochastic systems System performance hardware resource Noise

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Adapting FreeRTOS for multicores: an experience report

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SOFTWARE-PRACTICE & EXPERIENCE 2014年第9期44卷 1129-1154页

作者： Mistry, James Naylor, Matthew Woodcock, Jim British Telecommun PLC Ipswich IP5 3RE Suffolk England Univ York Dept Comp Sci York YO10 5GH N Yorkshire England

Multicore processors are ubiquitous. Their use in embedded systems is growing rapidly, and given the constraints on uniprocessor clock speeds, their importance in meeting the demands of increasingly processor-intensive embedded applications cannot be understated. To harness this potential, system designers need to have available to them embedded operating systems with built-in multicore support for widely available embedded hardware. This paper documents our experience of adapting FreeRTOS, a popular embedded real-time operating system, to support multiple processors. A working multicore version of FreeRTOS that is able to schedule tasks on multiple processors as well as provide full mutual-exclusion support for use in concurrent applications is presented. Mutual exclusion is achieved in an almost completely platform-agnostic manner, preserving one of FreeRTOS's most attractive features: portability. Copyright (c) 2013 John Wiley & Sons, Ltd.

关键词： embedded systems operating systems multicore computing task scheduling software-based mutual exclusion field-programmable gate arrays

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High-Sampling Rate Dynamic Inversion-Filter Realization and Applications in Digital Control

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IEEE-ASME TRANSACTIONS ON MECHATRONICS 2014年第1期19卷 238-248页

作者： Chang, Herrick L. Tsao, Tsu-Chin Univ Calif Los Angeles Dept Mech & Aerosp Engn Los Angeles CA 90095 USA

This paper presents a stable inversion of nonminimum phase systems with highly efficient computation for high-sampling rate applications. The stable filter that inverts the dynamics of a nonminimum system is based on cascading a stable pole-zero cancellation infinite impulse response (IIR) filter with a high-order finite impulse response (FIR) filter which inverts the unstable zero dynamics. The high-order FIR filter is realized based on efficient IIR filter implementation first introduced by Powell and Chau then later modified by Kurosu. As a demonstrative example, the inversion filters are applied to feedforward tracking and repetitive control algorithms and realized by a field programmable gate array. The controllers are implemented at 100-kHz sampling rate to control the motion of a 4 degrees-of-freedom magnetically levitated shaft in experiment.

关键词： Digital control electromagnetic forces feedforward systems field-programmable gate arrays infinite impulse response (IIR) filters mechatronics

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Single ADC Digital PFC Controller Using Precalculated Duty Cycles

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IEEE TRANSACTIONS ON POWER ELECTRONICS 2014年第2期29卷 996-1005页

作者： Sanchez, Alberto de Castro, Angel Manuel Lopez, Victor Azcondo, Francisco J. Garrido, Javier Univ Autonoma Madrid HCTLab Lab E-28049 Madrid Spain Univ Cantabria Dept Elect Technol Syst & Automat Engn E-39005 Santander Spain

Traditional digital power factor correction (PFC) uses three sensors to measure the input and output voltages and the input current. Each sensor, especially the input current one, increases the cost of the system and generates power losses in case of resistive sensors. This paper presents a controller for boost PFC converters. It uses precalculated duty cycles generated offline, and applies them to the switch. In order to control the converter with nonnominal conditions, just one analog-to-digital converter (ADC) is used, which measures the output voltage. Measuring the average and the ripple of the output voltage with this ADC, the controller takes compensation action for changes in the input voltage but also in the load of the converter. The average value is used to control the input voltage changes, while the ripple value is used to control load changes. These two loops present low frequency bandwidth, so the ADC and the whole system can be low cost. Finally, a comparator is used to detect the zero-crossing of the input voltage, so the precalculated values are synchronized with the ac mains. In this way, the converter only uses one ADC and one comparator, both with low bandwidth. Results show that high power factor and normative compliance are reached, even under nonnominal conditions.

关键词： Digital control field-programmable gate arrays rectifiers switched mode power supplies

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High-Speed Implementation of bcrypt Password Search using Special-Purpose Hardware

High-Speed Implementation of bcrypt Password Search using Sp...

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2014 International Conference on Reconfigurable Computing and FAGAs

作者： Wiemer, Friedrich Zimmermann, Ralf Ruhr Univ Bochum Horst Gortz Inst IT Secur HGI Bochum Germany

ISBN: (纸本)9781479959440

Using passwords for user authentication is still the most common method for many internet services and attacks on the password databases pose a severe threat. To reduce this risk, servers store password hashes, which were generated using special password-hashing functions, to slow down guessing attacks. The most frequently used functions of this type are PBKDF2, bcrypt and scrypt. In this paper, we present a novel, flexible, high-speed implementation of a bcrypt password search system on a low-power Xilinx Zynq 7020 FPGA. The design consists of 40 parallel bcrypt cores running at 100 MHz. Our implementation outperforms all currently available implementations and improves password attacks on the same platform by at least 42%, computing 6,511 passwords per second for a cost parameter of 5.

关键词： cryptography field programmable gate arrays message authentication bcrypt password search system field-programmable gate arrays frequency 100 MHz high-speed password search system implementation low-power Xilinx Zynq 7020 FPGA parallel bcrypt cores password attacks special-purpose hardware Clocks Cryptography Fabrics field programmable gate arrays Hardware Power demand Registers

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Educating Hardware Design - From Boolean Equations to Massively Parallel Computing Systems 9

Educating Hardware Design - From Boolean Equations to Massiv...

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9th Southern Conference on programmable Logic (SPL)

作者： Knodel, Oliver Zabel, Martin Lehmann, Patrick Spallek, Rainer G. Tech Univ Dresden Dept Comp Sci D-01062 Dresden Germany

ISBN: (纸本)9781479968480

The future of hardware development lies in massively parallel hardware architectures as used in embedded as well as high-performance systems, for instance streaming-based, real-time and database applications. Especially field-programmable gate arrays provide a platform for the rapid development of integrated circuits and the accompanied software. For reasons of energy efficiency, it is increasingly important to tailor hardware directly to the application. As such systems are very complex, the training of engineers has to start early. Furthermore, the usual curricula in computer science and electrical engineering teach only basic skills. In this paper we present lectures and especially practical FPGA design courses for bachelor and master students. We introduce a selection of individual projects, which were realized by students in practical courses. With examples from final bachelor projects and master theses we demonstrate the quality of education and its integration into current research. We describe possible improvements of labs, such as automated test benches and a remote FPGA laboratory for advanced courses.

关键词： Boolean algebra educational courses electronic engineering education embedded systems field programmable gate arrays further education logic design parallel architectures Boolean equations FPGA design courses advanced courses automated test benches bachelor students computer science education quality electrical engineering field-programmable gate arrays final bachelor projects hardware design hardware development high-performance systems integrated circuits massively parallel computing systems massively parallel hardware architecture master students master theses practical courses remote FPGA laboratory Computer architecture Computers Educational institutions field programmable gate arrays Hardware System-on-chip field programmable gate arrays computer hardware design Embedded systems Advanced Courses Continuing Education electrical engineering Computer hardware computer science system-on-chip parallel computing system Parallel architectures Logic design Computer Architecture Boolean algebra Educational institutions

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Teaching FPGA-based Systems

Teaching FPGA-based Systems

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IEEE Global Engineering Education Conference

作者： Skliarova, Iouliia Sklyarov, Valery Sudnitson, Alexander Kruus, Margus Univ Aveiro DETI IEETA HIPEAC P-3800 Aveiro Portugal Tallinn Univ Technol Dept Comp HIPEAC Tallinn Estonia

ISBN: (纸本)9781479931903

In this paper we report on recent advances in teaching field-programmable gate Array-based systems within engineering courses given in two Universities: University of Aveiro in Portugal and Tallinn University of Technology in Estonia. Although both institutions have a 6-year history of intensive and fruitful collaboration in this area there is a constant need to update both the teaching methods and the respective laboratory equipment and tools to keep in pace with the demanding industry requirements. This paper describes the most recent changes in the organization of the respective courses and the corresponding teaching materials. In particular, the developed communication modules required for software/hardware co-design are explained in detail.

关键词： field-programmable gate arrays engineering education teaching materials

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Improving Multibank Memory Access Parallelism with Lattice-Based Partitioning

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ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2014年第4期11卷 45-45页

作者： Cilardo, Alessandro Gallo, Luca Univ Naples Federico II Dept Elect Engn & Informat Technol I-80125 Naples Italy

Emerging architectures, such as reconfigurable hardware platforms, provide the unprecedented opportunity of customizing the memory infrastructure based on application access patterns. This work addresses the problem of automated memory partitioning for such architectures, taking into account potentially parallel data accesses to physically independent banks. Targeted at affine static control parts (SCoPs), the technique relies on the Z-polyhedral model for program analysis and adopts a partitioning scheme based on integer lattices. The approach enables the definition of a solution space including previous works as particular cases. The problem of minimizing the total amount of memory required across the partitioned banks, referred to as storage minimization throughout the article, is tackled by an optimal approach yielding asymptotically zero memory waste or, as an alternative, an efficient approach ensuring arbitrarily small waste. The article also presents a prototype toolchain and a detailed step-by-step case study demonstrating the impact of the proposed technique along with extensive comparisons with alternative approaches in the literature.

关键词： Design Languages Theory Memory partitioning polyhedral model fine-grained distributed shared memory field-programmable gate arrays

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