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Proceedings of the ACM/SIGDA international symposium on field programmable gate arrays

作者： David Uliana Krzysztof Kepa Peter Athanas Virginia Tech Blacksburg VA USA

ISBN: (纸本)9781450318877

This paper presents bFlow, an FPGA development framework for the rapid prototyping and implementation of hardware accelerators for hybrid computing platforms. This framework makes use of an abstracted, graphical front-end usable by those without computer engineering backgrounds, as well as an accelerated back-end that speeds up compilation times, increasing turns-per-day. bFlow's performance, usability, and application to the acceleration of big-data life-science problems verified by participants of the NSF-funded Summer Institute organised by the Virginia Bioinformatics Institute (VBI). In less than two weeks, a group of four non-computer science/computer engineering participants made modifications to a reference Smith-Waterman implementation, adding functionality and scaling throughput by a factor of four to 600 million base pairs per second.

关键词： field-programmable gate arrays bioinformatics co-processor heterogeneous computing design productivity convey HC-1 big-data

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Analysis and architecture design of scalable fractional motion estimation for H.264 encoding

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INTEGRATION-THE VLSI JOURNAL 2012年第4期45卷 427-438页

作者： Vasiljevic, Jasmina Ye, Andy Ryerson Univ Dept Elect & Comp Engn Toronto ON M5B 2K3 Canada

Fractional Motion Estimation (FME) is an important part of the H.264/AVC video encoding standard. The algorithm can significantly increase the compression ratio of video encoders while improving video quality. However, it is computationally expensive and can consist of over 45% of the total motion estimation runtime. To maximize the performance and utilization of FME implementations on field-programmable gate arrays (FPGAs), one needs to effectively exploit the inherent parallelism in the algorithm. In this work, we explore two approaches to FME algorithm parallelization in order to effectively increase the processing power of the computing hardware. We call the first method vertical scaling and the second horizontal scaling. We implemented six scaled FME designs on a Xilinx XC5VLX85T (Virtex-5) FPGA. We found that scaling vertically within a 4 x 4 sub-block is more efficient than scaling horizontally across several sub-blocks. As a result, we were able to achieve higher video resolutions at lower hardware resource cost. In particular, it is shown that the best vertically scaled design can achieve 30 fps of QSXGA video with 4 reference frames with only 25.5 K LUTS and 28.7 K registers. (C) 2011 Elsevier B.V. All rights reserved.

关键词： Fractional motion estimation H.264 field-programmable gate arrays Scalability

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Using Data Contention in Dual-ported Memories for Security Applications

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2012年第1期67卷 15-29页

作者： Gueneysu, Tim Ruhr Univ Bochum Horst Gortz Inst IT Secur Bochum Germany

field programmable gate arrays (FPGA) provide the invaluable feature of dynamic hardware reconfiguration by loading configuration bit files. However, this flexibility also opens up the threat of theft of Intellectual Property (IP) since these configuration files can be easily extracted and cloned. In this context, the ability to bind an application configuration to a specific device is an important step to prevent product counterfeiting. Furthermore, such a technology can also enable advanced business models such as device-specific feature activation. In this work, we present a new technique to generate entropy on FPGA device-based on data contention in the hardware circuitry. For this entropy, we use the output of intentionally generated write collisions in synchronous dual-ported block RAMs (BRAM). We show that the parts of this output generated by such write collisions can be either probabilistic but also deterministic and device-specific. The characteristics of such an entropy source can be used for a large variety of security applications, such as chip identification and device authentication. In addition to that, we also propose a solution to efficiently create cryptographic keys on-chip at runtime. As a last contribution, we eventually present a strategy how to transform this entropy source into a circuit for True Random Number Generation (TRNG).

关键词： Write collisions field-programmable gate arrays Security applications Device identification Random number generation Metastability Data contention Dual-ported block RAM

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Correlation-Based Detection of OFDM Signals in the Angular Domain

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IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY 2012年第3期61卷 951-958页

作者： Turunen, Vesa Kosunen, Marko Vaarakangas, Mikko Ryynanen, Jussi Aalto Univ Dept Micro & Nanosci Espoo 00076 Finland Nokia Res Ctr Helsinki 00180 Finland

Spectrum sensing is an essential part of future cognitive radios, as the spectrum sensor provides information about the utilization of the surrounding radio spectrum. Several approaches to implementing spectrum sensing have been proposed in the literature, one of them being the class of feature detectors. Cyclostationary feature detectors are, in general, considered to be superior in performance but suffer from high implementation complexity. Therefore, most studies still utilize energy detectors, which may not reach the performance requirements set for practical implementations. This paper presents angular domain feature detection algorithms that are based on cyclostationary properties. Angular domain signal processing is shown to simplify the implementation considerably while preserving comparable performance. Moreover, a new detection algorithm that leads to multiplier-free implementation and reduces the memory requirements, compared with any previous approaches, is proposed.

关键词： Autocorrelation cognitive radio detection algorithms digital signal processing field-programmable gate arrays orthogonal frequency-division multiplex (OFDM)

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Frequency Estimation Using a Genetic Algorithm With Regularization Implemented in FPGAs

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IEEE TRANSACTIONS ON SMART GRID 2012年第3期3卷 1353-1361页

作者： Coury, Denis V. Delbem, Alexandre C. B. de Carvalho, Janison Rodrigues Oleskovicz, Mario Simoes, Eduardo V. Barbosa, Daniel da Silva, Tiago V. Univ Sao Paulo Engn Sch Sao Carlos Dept Elect Engn Sao Carlos SP Brazil Univ Sao Paulo Inst Math & Comp Sci Sao Carlos SP Brazil Univ Salvador Salvador BA Brazil Univ Fed Bahia Salvador BA Brazil

This paper proposes an accurate and precise genetic algorithm(GA) for frequency estimation of electrical power system (EPS) signals. The problem of estimating the frequency of a distorted electrical signal is modeled as an optimization problem. A regularization technique is used to guide the GA to a plausible solution from a practical point of view when the signal has significant output distortions. In this approach, the GA using regularization (GAR) enables the balanced investigation of a number of potential solutions, largely exploring the search space from one side, and weighing the suitable solutions according to practical purposes from the other side. The GAR is programmed in a field-programmable gate array (FPGA) device. This is made possible due to 1) the implicit parallelism of FPGAs in computing their instructions and 2) the suitable choice of steps of GARs to explore this parallelism. To evaluate the performance of the proposed method, an EPS was simulated having typical operation conditions. The relatively high robustness exhibited by the GAR to harmonics and noise makes it a promising equipment in the challenge of construction of smart power grids.

关键词： Digital relaying field-programmable gate arrays frequency estimation genetic algorithms power system protection

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Embedded Flash on a Low-Power 65-nm Logic Technology

IEEE ELECTRON DEVICE LETTERS

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IEEE ELECTRON DEVICE LETTERS 2012年第9期33卷 1261-1263页

作者： Fong, S. Ariyoshi, J. Ema, T. Lattice Semicond Inc San Jose CA 95134 USA Fujitsu Semicond Ltd Kuwana 5110192 Japan

We have successfully integrated an embedded Flash technology into a 65-nm leading-edge logic technology. We have also optimized the logic transistor characteristics to achieve an extremely low standby current suitable... 详细信息

关键词： Embedded Flash memory field-programmable gate arrays low power

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FPGA Design of a New Frequency Relay Based on Evolutionary Algorithms

FPGA Design of a New Frequency Relay Based on Evolutionary A...

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IEEE PES Innovative Smart Grid Technologies Conference

作者： Denis V. Coury Alexandre C. B. Delbem Mario Oleskovicz Eduardo V. Simoes Daniel Barbosa Janison R. de Carvalho Depto de Engenharia Eletrica e de Computacao - Escola de Engenharia de Sao Carlos -EESC Universidade de Sao Paulo - USP Av. Trabalhador Sancarlense 400 Centro CEP 13566-590 - Sao Carlos-SP-Brasil Instituto de Ciencias Matematicas e de Computagao -ICMC

ISBN: (纸本)9781467352727

This paper presents an efficient technique for frequency estimation in Electrical Power Systems (EPS) based on Genetic Algorithms (GAs). Frequency estimation of a distorted electrical signal is modeled as an optimization problem. The motivation concerning the use of the GA approach is related to its intrinsic robustness to noise. The GA is implemented in a FPGA (field-programmable gate Array) device and the estimation process is computed in real-time. This is made possible due to (a) the implicit parallelism of FPGAs (b) the suitable choice of the GA operators to explore this parallelism and (c) the determination of the appropriate architecture for a FPGA that parallelizes the GA routine and ensures its good performance. In order to evaluate the performance of the proposed method, an EPS was simulated using the ATP software for some typical operation conditions. The resulting signals were analyzed by the proposed GA/FPGA approach and they were compared to the performance of a commercial relay. Promising results were found with the proposed methodology.

关键词： Frequency Estimation Genetic Algorithms field-programmable gate arrays Digital Relaying Power System Protection

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COST-PERFORMANCE ANALYSIS OF COMPONENT ARCHITECTURAL DESIGNS FOR DYNAMIC PARTIALLY RECONFIGURABLE SYSTEMS

COST-PERFORMANCE ANALYSIS OF COMPONENT ARCHITECTURAL DESIGNS...

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25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)

作者： Diaz, David Dumitriu, Victor Kirischian, Lev Ryerson Univ Dept Elect & Comp Engn Toronto ON Canada

ISBN: (纸本)9781467314336

Dynamic Partially Reconfigurable Computing(DPRC) systems have received significant attention in recent years as a potential alternative to traditional computing system designs;such systems implement much of their functionality in the form of virtual components, represented by configuration bit-streams. However, for such systems to be adopted as viable mainstream solutions to system design, a number of problems and challenges must be addressed. One such challenge is the decision criteria for the selection of architectures for the components which make up such systems. This study explores the importance a cost-efficiency factor (CEF) has in the design of virtual components in embedded reconfigurable systems. Dedicated hardware, software, and hybrid architectures were analyzed for two video applications. The resulting analysis demonstrates that the selection of architectures for virtual components can benefit from considerations of the CEF and time-to-market associated with each architecture.

关键词： field-programmable gate arrays hardware parallel architectures reconfigurable architectures

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Novel Fine Tunable Multichannel All-Digital Transmitter

Novel Fine Tunable Multichannel All-Digital Transmitter

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IEEE/MTT-S International Microwave Symposium

作者： Nelson V. Silva Arnaldo S. R. Oliveira Nuno Borges Carvalho Departamento de Electronica Telecomunicacoes e Informatica Instituto de Telecomunicacoes Universidade de Aveiro

ISBN: (纸本)9781467361750

All-digital transmitters are gaining an increased research importance due to the unparalleled proliferation of dissimilar wireless standards and more recently due to the white space technology needs. In this paper, a new fine tunable multi-channel transmitter is presented. This new architecture supports concurrent multi-rate, multi-band, multi-standard transmission and significantly minimizes the output frequencies restrictions of current approaches by allowing fine frequency tuning for channel selection. The obtained results show the feasibility and potential of FPGA-embedded RF transmitters where the use of polyphase datapaths substantially improves the SNR of the desired signals.

关键词： Cognitive radio Delta-sigma modulation field-programmable gate arrays Radio transmitters Software radio

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Improved Performance of TES Bolometers using Digital Feedback

Improved Performance of TES Bolometers using Digital Feedbac...

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Conference on Millimeter, Submillimeter, and Far-Infrared Detectors and Instrumentation for Astronomy VI

作者： de Haan, Tijmen Smecher, Graeme Dobbs, Matt McGill Univ Dept Phys Montreal PQ H3A 2T8 Canada

ISBN: (纸本)9780819491534

Voltage biased, frequency multiplexed TES bolometers have become a widespread tool in mm-wave astrophysics. However, parasitic impedance and dynamic range issues can limit stability, performance, and multiplexing factors. Here, we present novel methods of overcoming these challenges, achieved through digital feedback, implemented on a field-programmable gate Array (FPGA). In the first method, known as Digital Active Nulling (DAN), the current sensor (e.g. SQUID) is nulled in a separate digital feedback loop for each bolometer frequency. This nulling removes the dynamic range limitation on the current sensor, increases its linearity, and reduces its effective input impedance. Additionally, DAN removes constraints on wiring lengths and maximum multiplexing frequency. DAN has been fully implemented and tested. Integration for current experiments, including the South Pole Telescope, will be discussed. We also present a digital mechanism for strongly increasing stability in the presence of large series impedances, known as Digitally Enhanced Voltage Bias (DEVB).

关键词： Digital feedback baseband feedback TES bolometers field-programmable gate arrays

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