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17th IEEE International Symposium on High-Performance Computer Architecture (HPCA)

作者： Pellauer, Michael Adler, Michael Kinsy, Michel Parashar, Angshuman Emer, Joel MIT Computat Struct Grp Comp Sci & AI Lab Cambridge MA 02139 USA Intel Corp VSSAD Grp Santa Clara CA 95054 USA

ISBN: (纸本)9781424494354

In this paper we present the HAsim FPGA-accelerated simulator. HAsim is able to model a shared-memory multicore system including detailed core pipelines, cache hierarchy, and on-chip network, using a single FPGA. We describe the scaling techniques that make this possible, including novel uses of time-multiplexing in the core pipeline and on-chip network. We compare our time-multiplexed approach to a direct implementation, and present a case study that motivates why high-detail simulations should continue to play a role in the architectural exploration process.

关键词： Simulation Modeling On-Chip Networks field-programmable gate arrays FPGA

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Towards Scalable FPGA CAD Through Architecture 11

Towards Scalable FPGA CAD Through Architecture

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19th Annual ACM International Symposium on field-programmable gate arrays

作者： Chin, Scott Y. L. Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781450305549

Long FPGA CAD runtime has emerged as a limitation to the future scaling of FPGA densities. Already, compile times on the order of a day are common, and the situation will only get worse as FPGAs get larger. Without a concerted effort to reduce compile times, further scaling of FPGAs will eventually become impractical. Previous works have presented fast CAD tools that tradeoff quality of result for compile time. In this paper, we take a different but complementary approach. We show that the architecture of the FPGA itself can be designed to be amenable to fast-compile. If not done carefully, this can lead to lower-quality mapping results, so a careful tradeoff between area, delay, power, and compile run-time is essential. We investigate the extent to which run-time can be reduced by employing high-capacity logic blocks. We extend previous studies on logic block architectures by quantifying the area, delay and CAD runtime trade-offs for large capacity blocks, and also investigate some multi-level logic block architectures. In addition, we present an analytically derived equation to guide the design of logic block I/O requirements.

关键词： field-programmable gate arrays FPGAs Architecture CAD Run-time

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Self-adjusting Fuzzy MPPT PV System Control by FPGA Design

Self-adjusting Fuzzy MPPT PV System Control by FPGA Design

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Asia-Pacific Power and Energy Engineering Conference (APPEEC)

作者： Cheng, Ze Yang, Hongzhi Liu, Yanli Tianjin Univ Sch Elect Engn & Automat Tianjin Peoples R China

ISBN: (纸本)9781424462551

In this paper, an adaptive fuzzy MPPT controller is designed with FPGA, the design of fuzzy controller and adaptive control theory is described in detail, and it is discussed that how to implement adaptive fuzzy MPPT control with FPGA, and finally The solar storage control system is built with the controller, the experiment proved that the controller using this method can adjust the parameter according to the change of the external condition, with fast search optimum ability to make the system working at the max power point steadily, lays the foundation for SoC design of PV system.

关键词： self-adjusting fuzzy photovoltaic array field-programmable gate arrays

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Analysis of Within-Die Process Variation in 65nm FPGAs

Analysis of Within-Die Process Variation in 65nm FPGAs

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12th International Symposium on Quality Electronic Design (ISQED)

作者： Tuan, Tim Lesea, Austin Kingsley, Chris Trimberger, Steve Xilinx Res Labs San Jose CA 95124 USA

ISBN: (纸本)9781612849140

FPGAs are a great platform for studying within-die process variation because test structures can be implemented in product silicon using reconfigurable logic. This approach can achieve very high coverage without wasting otherwise useful silicon area. In this paper, we present a detailed analysis of within-die delay variation in a 65nm FPGA. We use densely distributed test oscillators to measure within-die performance variation across a large sample of dies, and identify both random and spatially correlated systematic components through post-processing. Finally, we evaluate the benefit of modeling within-die systematic variation in static timing analysis.

关键词： field-programmable gate arrays within-die variation systematic variation variation-aware design

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Real-Time Pattern Matching with FPGAs

Real-Time Pattern Matching with FPGAs

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IEEE 27th International Conference on Data Engineering (ICDE 2011)

作者： Woods, Louis Teubner, Jens Alonso, Gustavo Swiss Fed Inst Technol Dept Comp Sci Syst Grp Zurich Switzerland

ISBN: (纸本)9781424489589

We demonstrate a hardware implementation of a complex event processor, built on top of field-programmable gate arrays (FPGAs). Compared to CPU-based commodity systems, our solution shows distinctive advantages for stream monitoring tasks, e.g., wire-speed processing and predictable performance. The demonstration is based on a query-to-hardware compiler for complex event patterns that we presented at VLDB 2010 [1]. By example of a click stream monitoring application, we illustrate the inner workings of our compiler and indicate how FPGAs can act as efficient and reliable processors for event streams.

关键词： Automata CPU-based commodity systems Decoding Event detection FPGA field programmable gate arrays Hardware Monitoring Pattern matching VLDB 2010 click stream monitoring application complex event patterns complex event processor field programmable gate arrays field-programmable gate arrays file servers microprocessor chips pattern matching predictable performance program processors query-to-hardware compiler real-time pattern matching wire-speed processing

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VPR 5.0: FPGA CAD and Architecture Exploration Tools with Single-Driver Routing, Heterogeneity and Process Scaling

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2011年第4期4卷 32-32页

作者： Luu, Jason Kuon, Ian Jamieson, Peter Campbell, Ted Ye, Andy Fang, Wei Mark Kent, Kenneth Rose, Jonathan Univ Toronto Toronto ON Canada Univ New Brunswick Fredericton NB E3B 5A3 Canada

The VPR toolset has been widely used in FPGA architecture and CAD research, but has not evolved over the past decade. This article describes and illustrates the use of a new version of the toolset that includes four new features: first, it supports a broad range of single-driver routing architectures, which have superior architectural and electrical properties over the prior multidriver approach (and which is now employed in the majority of FPGAs sold). Second, it can now model, for placement and routing a heterogeneous selection of hard logic blocks. This is a key (but not final) step toward the incluion of blocks such as memory and multipliers. Third, we provide optimized electrical models for a wide range of architectures in different process technologies, including a range of area-delay trade-offs for each single architecture. Finally, to maintain robustness and support future development the release includes a set of regression tests for the software. To illustrate the use of the new features, we explore several architectural issues: the FPGA area efficiency versus logic block granularity, the effect of single-driver routing, and a simple use of the heterogeneity to explore the impact of hard multipliers on wiring track count.

关键词： Algorithms Design Experimentation Reliability FPGA VPR field-programmable gate arrays placement routing heterogeneous hard blocks

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Analysis of Within-Die Process Variation in 65nm FPGAs

Analysis of Within-Die Process Variation in 65nm FPGAs

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International Symposium on Quality Electronic Design

作者： Tim Tuan Austin Lesea Chris Kingsley Steve Trimberger Xilinx Research Labs

ISBN: (纸本)9781612849133

关键词： field-programmable gate arrays Within-die variation Systematic variation Variation-aware design

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An FPGA-Integrated Time-to-Digital Converter Based on Two-Stage Pulse Shrinking

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2010年第6期59卷 1663-1670页

作者： Szplet, Ryszard Klepacki, Kamil Mil Univ Technol PL-00908 Warsaw Poland

We present the design and test results of a new time-to-digital converter based on the cyclic pulse shrinking method and implemented in a field-programmable gate array (FPGA) device. The pulse shrinking is realized in a loop containing two complementary delay lines. The first line shrinks, and the second line stretches the duration time of a circulating pulse;hence, the length ratio of the lines determines the pulse-shrinking capability of the converter. This resolution control mechanism is different from the bias adjustment typically used in complementary metal-oxide-semiconductor (CMOS) application-specific integrated circuit (ASIC) pulse-shrinking elements. Two forms of representation of a measured time interval (the pulse width and the time interval between two pulses) are utilized in the described converter to improve the efficiency of resolution control. To diminish the jitter of the edges of a circulating pulse and, consequently, to increase the precision of the converter, a two-stage conversion is introduced. The first stage, having a low resolution, rapidly shortens the measured pulse, thus limiting the number of cycles, whereas the second stage provides a final high resolution within a narrow time interval range. The optimal resolution of the first conversion stage is theoretically derived. Mostly, the same logical resources of the FPGA device are utilized in both conversion stages;thus, the overall area overhead of the converter is reduced. The converter has a resolution of 42 ps and a measurement uncertainty of below 56 ps within the measurement range of 11.5 ns. The converter has been implemented in a general-purpose reprogrammable device Spartan-3 (Xilinx).

关键词： field-programmable gate arrays pulse shrinking time digitizer time-to-digital converter two-stage interpolation

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NALLATECH IN-SOCKET FPGA FRONT-SIDE BUS ACCELERATOR

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COMPUTING IN SCIENCE & ENGINEERING 2010年第2期12卷 78-82页

作者： Steffen, Craig Genest, Gildas Univ Illinois US Natl Ctr Supercomp Applicat Urbana IL 61801 USA Nallatech Cumbernauld Scotland

field-programmable gate arrays, which are more flexible than application-specific integrated circuits, have emerged as a low-power alternative to CPUs.

关键词： FPGA front-side bus accelerator field-programmable gate arrays Xeon Xilinx accelerators bandwidth compiler field programmable gate arrays field-programmable gate array low-power electronics reconfigurable socket- based accelerator

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HIGH-PERFORMANCE HETEROGENEOUS COMPUTING WITH THE CONVEY HC-1

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COMPUTING IN SCIENCE & ENGINEERING 2010年第6期12卷 80-87页

作者： Bakos, Jason D. Univ S Carolina Dept Comp Sci & Engn Columbia SC 29208 USA

Unlike other socket-based reconfigurable coprocessors, the Convey HC-1 contains nearly 40 field-programmable gate arrays, scatter-gather memory modules, a high-capacity crossbar switch, and a fully coherent memory sys... 详细信息

关键词： Reconfigurable computing coherent memory system convey HC-1 coprocessors field programmable gate arrays field-programmable gate arrays field-programmable gate arrays heterogeneous computing high-capacity crossbar switch high-performance computing high-performance heterogeneous computing hybrid computing reconfigurable architectures scatter-gather memory modules socket-based reconfigurable coprocessors

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