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Conversion Algorithms and Implementations for Koblitz Curve Cryptography

IEEE TRANSACTIONS ON COMPUTERS 2010年第1期59卷 81-92页

作者： Brumley, Billy Bob Jarvinen, Kimmo U. Aalto Univ Dept Informat & Comp Sci Espoo 02150 Finland

In this paper, we discuss conversions between integers and tau-adic expansions and we provide efficient algorithms and hardware architectures for these conversions. The results have significance in elliptic curve cryptography using Koblitz curves, a family of elliptic curves offering faster computation than general elliptic curves. However, in order to enable these faster computations, scalars need to be reduced and represented using a special base-tau expansion. Hence, efficient conversion algorithms and implementations are necessary. Existing conversion algorithms require several complicated operations, such as multiprecision multiplications and computations with large rationals, resulting in slow and large implementations in hardware and microcontrollers with limited instruction sets. Our algorithms are designed to utilize only simple operations, such as additions and shifts, which are easily implementable on practically all platforms. We demonstrate the practicability of the new algorithms by implementing them on Altera Stratix II FPGAs. The implementations considerably improve both computation speed and required area compared to the existing solutions.

关键词： Elliptic curve cryptography Koblitz curves field-programmable gate arrays public-key cryptosystems

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MATRIX STRUCTURES AND PARALLEL ALGORITHMS FOR IMAGE SUPERRESOLUTION RECONSTRUCTION

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SIAM JOURNAL ON MATRIX ANALYSIS AND APPLICATIONS 2010年第4期31卷 1873-1893页

作者： Zhang, Qiang Guy, Richard T. Plemmons, Robert J. Wake Forest Univ Hlth Sci Dept Biostat Sci Winston Salem NC 27159 USA Wake Forest Univ Dept Math Winston Salem NC 27109 USA Wake Forest Univ Dept Math & Comp Sci Winston Salem NC 27109 USA

Computational resolution enhancement (superresolution) is generally regarded as a memory-intensive process due to the large matrix-vector calculations involved. In this paper, a detailed study of the structure of the n(2) x n(2) superresolution matrix is used to decompose the matrix into nine matrices of size l(2) x l(2), where l is the upsampling factor. As a result, previously large matrix-vector products can be broken into many small, parallelizable products. An algorithm is presented that utilizes the structural results to perform superresolution on compact, highly parallel architectures such as field-programmable gate arrays.

关键词： image superresolution field-programmable gate arrays parallel computation structured matrices

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High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann Machines

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IEEE TRANSACTIONS ON NEURAL NETWORKS 2010年第11期21卷 1780-1792页

作者： Le Ly, Daniel Chow, Paul Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications has been limited. A primary cause for this lack of adoption is that neural networks are usually implemented as software running on general-purpose processors. Hence, a hardware implementation that can exploit the inherent parallelism in neural networks is desired. This paper investigates how the restricted Boltzmann machine (RBM), which is a popular type of neural network, can be mapped to a high-performance hardware architecture on field-programmable gate array (FPGA) platforms. The proposed modular framework is designed to reduce the time complexity of the computations through heavily customized hardware engines. A method to partition large RBMs into smaller congruent components is also presented, allowing the distribution of one RBM across multiple FPGA resources. The framework is tested on a platform of four Xilinx Virtex II-Pro XC2VP70 FPGAs running at 100 MHz through a variety of different configurations. The maximum performance was obtained by instantiating an RBM of 256 x 256 nodes distributed across four FPGAs, which resulted in a computational speed of 3.13 billion connection-updates-per-second and a speedup of 145-fold over an optimized C program running on a 2.8-GHz Intel processor.

关键词： Boltzmann machines computer architecture field-programmable gate arrays neural network hardware parallel processing

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A framework of embedded reconfigurable systems based on re-locatable virtual components

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INTERNATIONAL JOURNAL OF EMBEDDED SYSTEMS 2010年第3-4期4卷 182-194页

作者： Dumitriu, Victor Kirischian, Lev Ryerson Univ Dept Elect & Comp Engn 350 Victoria St Toronto ON M5B 2K3 Canada

The use of modern field-programmable logic devices can help system designers achieve better cost-performance characteristics, in particular in the case of multi-task and multi-modal workloads. This is particularly true when the embedded systems are based on run-time and partially reconfigurable FPGA devices. Such devices permit a system to implement part of its functionality in virtual form, by storing circuits as configuration bit-streams. The use of such virtual components, however, imposes certain requirements on both the behaviour of the system as well as the components themselves. The work presented here analyses some of these requirements, and proposes a potential framework for designing embedded systems using virtual resources. Two examples of a system using virtual components are presented and the infrastructure overhead for supporting virtual components is analysed. It is found that such systems can be implemented efficiently, both in terms of hardware resources as well as timing performance.

关键词： dynamic reconfiguration embedded systems field-programmable gate arrays system design video processing virtual hardware component virtualisation

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Power-aware FPGA Routing Fabrics and Design Tools

Power-aware FPGA Routing Fabrics and Design Tools

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18th IEEE/IFIP International Conference on VLSI and System-on-Chip

作者： Nishida, Shoichi Eto, Jyunya Amagasaki, Motoki Iida, Masahiro Kuga, Morihiro Sueyoshi, Toshinori Kumamoto Univ Grad Sch Sci & Technol Kumamoto 8608555 Japan

ISBN: (纸本)9781424464708

The performance of field-programmable gate arrays (FPGAs) has been significantly improved due to a new process technology. However, several problems have arisen in the new generation FPGAs. Specifically, the issue of power consumption is a serious issue, because FPGAs have many routing resources. We report on the improvement of both the FPGA routing structure and electronic design automation (EDA) tools in order to solve this issue. In order to reduce the power consumption, high activity nets are assigned to low load lines, which is the routing structure used for small-world networks in FPGAs. In addition, the clustering and routing algorithms of the EDA tools are improved to complement the routing structure. This report demonstrates that the power can be reduced. Based on evaluation results, a maximum power consumption improvement of 48.4% was obtained, and the average improvement was 22.9% when using the proposed routing structure and EDA tools.

关键词： clustering algorithms electronic design automation electronic design automation tools field programmable gate arrays field-programmable gate arrays network routing power consumption power-aware FPGA routing fabrics

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A Less Configuration Memory Reconfigurable Logic Device with Error Detect and Correct Circuit

A Less Configuration Memory Reconfigurable Logic Device with...

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IEEE Region 10 Conference on TENCON 2010

作者： Zhao, Qian Ichinomiya, Yoshihiro Okamoto, Yasuhiro Amagasaki, Motoki Iida, Masahiro Sueyoshi, Toshinori Kumamoto Univ Grad Sch Sci & Technol Kumamoto 8608555 Japan

ISBN: (纸本)9781424468904

The field-programmable gate arrays (FPGAs) are widely used in varies fields in recent years. However, because of large amounts of configuration memories in FPGAs are used to implement logic and routing, the single event upset (SEU) problem makes them not feasible for applications that need high reliability. Moreover, as the threshold voltage becomes lower with the development of silicon process technology, the configuration memories are becoming more sensitive to SEU. Therefore, FPGAs require new technology to improve its dependability. In this research, we first develop a new Hamming code based error detect and correct (EDC) circuit that can prevent the configuration memory of a reconfigurable device from SEU. We then propose a novel reconfigurable logic element, namely COGRE, which will use much less configuration memory than the conventional FPGA 4-, 5- or 6-LUTs (lookup tables). Evaluation revealed that compared to the 6-LUT FPGAs with triple modular redundancy (TMR) configuration memory blocks, the 5- and 6-input COGRE with the novel error detect and correct circuit save about 75.44 and 74.29% memories on average, respectively. And the dependability of the proposed architectures is about 6.8 to 10 times better than the LUTs with a tile level TMR structure on average. Moreover, with the consideration of the on the fly scrubbing advantage of the EDC, SEUs cannot be accumulated, so a much higher dependability can be achieved.

关键词： EDC circuit Hamming code based error detect Hamming codes configuration memory reconfigurable logic device correct circuit error detect circuit field-programmable gate arrays logic circuits reconfigurable architectures reconfigurable logic element table l

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FPGA Power Reduction by Guarded Evaluation 10

FPGA Power Reduction by Guarded Evaluation

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18th ACM International Symposium on field-programmable gate arrays

作者： Anderson, Jason H. Ravishankar, Chirag Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781605589114

Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times during circuit operation, thereby reducing switching activity and lowering dynamic power. The concept is rooted in the property that under certain conditions, some signals within digital designs are not "observable" at design outputs, making the circuitry that generates such signals a candidate for guarding. Guarded evaluation has been demonstrated successfully for custom ASICs;in this paper, we apply the technique to FPGAs. In ASICs, guarded evaluation entails adding additional hardware to the design, increasing silicon area and cost. Here, we apply the technique in a way that imposes minimal area overhead by leveraging existing unused circuitry within the FPGA. The primary challenge in guarded evaluation is in determining the specific conditions under which a sub-circuit's inputs can be held constant without impacting the larger circuit's functional correctness. We propose a simple solution to this problem based on discovering "non-inverting paths" in the circuit's AND-inverter graph representation. Experimental results show that guarded evaluation can reduce switching activity by 22%, on average, and can reduce power consumption in the FPGA interconnect by 14%.

关键词： field-programmable gate arrays FPGAs power optimization low-power design logic synthesis technology mapping

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A SCALABILITY STUDY OF FRACTIONAL MOTION ESTIMATION FOR H.264 ENCODING

A SCALABILITY STUDY OF FRACTIONAL MOTION ESTIMATION FOR H.26...

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23rd Canadian Conference on Electrical and Computer Engineering (CCECE)

作者： Vasiljevic, Jasmina Ye, Andy Ryerson Univ Dept Elect & Comp Engn Toronto ON M5B 2K3 Canada

ISBN: (纸本)9781424453771

Fractional motion estimation (FME) is an important part of the H.264/AVC video encoding standard. The algorithm can significantly increase the compression ratio of video encoders while at the same time improve video quality. The FME algorithm, however, is also computationally expensive and can consist of over 45% of the total motion estimation process. To maximize the performance and efficiency of the FME implementations on field-programmable gate arrays (FPGAs), one needs to effectively exploit the inherent parallelism in the algorithm. In this work, we define two scalability approaches in order to intelligently parallelize the computing hardware. We implemented five scaled FME designs on a Xilinx XC5VLX330T (Virtex-5) FPGA. We found that scaling vertically with an 4x4 subblock is more efficient than scaling horizontally across several subblocks. It is shown that the best vertically scaled design can achieve 128 fps when encoding full 1920x1088 progressive HDTV video with only 20.7K LUTS and 23.4K registers.

关键词： Fractional Motion Estimation H.264/AVC field-programmable gate arrays

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Physically-Adaptive Computing via Introspection and Self-Optimization in Reconfigurable Systems

Physically-Adaptive Computing via Introspection and Self-Opt...

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作者： Zick, Kenneth M. University of Michigan

学位级别：Ph.D.

Digital electronic systems typically must compute precise and deterministic results, but in principle have flexibility in how they compute. Despite the potential flexibility, the overriding paradigm for more than 50 years has been based on fixed, non-adaptive integrated circuits. This one-size-fits-all approach is rapidly losing effectiveness now that technology is advancing into the nanoscale. Physical variation and uncertainty in component behavior are emerging as fundamental constraints and leading to increasingly sub-optimal fault rates, power consumption, chip costs, and lifetimes. This dissertation proposes methods of physically-adaptive computing (PAC), in which reconfigurable electronic systems sense and learn their own physical parameters and adapt with fine granularity in the field, leading to higher reliability and efficiency. We formulate the PAC problem and provide a conceptual framework built around two major themes: introspection and self-optimization. We investigate how systems can efficiently acquire useful information about their physical state and related parameters, and how systems can feasibly re-implement their designs on-the-fly using the information learned. We study the role not only of self-adaptation—where the above two tasks are performed by an adaptive system itself—but also of assisted adaptation using a remote server or peer. We introduce low-cost methods for sensing regional variations in a system, including a flexible, ultra-compact sensor that can be embedded in an application and implemented on field-programmable gate arrays (FPGAs). An array of such sensors, with only 1% total overhead, can be employed to gain useful information about circuit delays, voltage noise, and even leakage variations. We present complementary methods of regional self-optimization, such as finding a design alternative that best fits a given system region. We propose a novel approach to characterizing local, uncorrelated variations. Through in-system emulat

关键词： Physically-adaptive Computing Introspection Reconfigurable Digital Systems field-programmable gate arrays Physical Variation Nanoscale Thesis

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A Hierarchical Description Language and Packing Algorithm for Heterogenous FPGAs

A Hierarchical Description Language and Packing Algorithm fo...

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作者： Luu, Jason University of Toronto

学位级别：master

The complexity of field-programmable gate Array (FPGAs) logic blocks have undergone constant evolution to the point where both the basic soft logic blocks that implement combinational logic and the fixed-function hard blocks contain complex interconnects, hierarchy and modes. The goal of this thesis is to both support that complexity and enable future architecture exploration of even increased complexity and new kinds of hard functionality. To accomplish this, a Computer-Aided Design (CAD) flow that can map a user circuit to an FPGA with these complex blocks is needed. We propose a new language that can describe these complex blocks and a new area-driven tool for the packing stage of that CAD flow. The packing stage groups components of a user circuit into the complex blocks available on the FPGA. We conduct experiments to illustrate the quality of the packing tool and to demonstrate the newly-enabled architecture exploration capabilities

关键词： FPGA CAD Packing Clustering field-programmable gate arrays Computer-Aided Design Architecture

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