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REDUCTION IN THE NUMBER OF LUT ELEMENTS FOR CONTROL UNITS WITH CODE SHARING

INTERNATIONAL JOURNAL OF APPLIED MATHEMATICS AND COMPUTER SCIENCE 2010年第4期20卷 751-761页

作者： Barkalov, Alexander Titarenko, Larysa Bieganowski, Jacek Univ Zielona Gora Inst Comp Engn & Elect PL-65246 Zielona Gora Poland

Two methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional microprogram control units (CMCUs) with code sharing. The methods assume the application of field-programmable gate arrays for the implementation of the combinational part of the CMCU, whereas embedded-memory blocks are used for implementation of its control memory. Both methods are based on the existence of classes of pseudoequivalent operational linear chains in a microprogram to be implemented. Conditions for the application of the proposed methods and examples of design are shown. Results of conducted experiments are given.

关键词： compositional microprogram control unit code sharing operational linear chain field-programmable gate arrays look-up table design embedded-memory block

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A Hardware-Accelerated Quantum Monte Carlo framework (HAQMC) for N-body systems

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COMPUTER PHYSICS COMMUNICATIONS 2009年第12期180卷 2563-2573页

作者： Gothandaraman, Akila Peterson, Gregory D. Warren, G. Lee Hinde, Robert J. Harrison, Robert J. Univ Tennessee Dept Elect Engn & Comp Sci Knoxville TN 37996 USA Yeshiva Univ Dept Chem New York NY 10033 USA Univ Tennessee Dept Chem Knoxville TN 37996 USA

Interest in the study of structural and energetic properties of highly quantum clusters, such as inert gas clusters has motivated tile development of a hardware-accelerated framework for Quantum Monte Carlo simulations. In the Quantum Monte Carlo method, the properties of a system of atoms, such as the ground-state energies, are averaged over a number of iterations. Our framework is aimed at accelerating the computations in each iteration of the QMC application by offloading the calculation of properties, namely energy and trial wave function, onto reconfigurable hardware. This gives a user tile capability to run simulations for a large number of iterations, thereby reducing the statistical uncertainty in the properties, and for larger clusters. This framework is designed to run oil the Cray XD1 high performance reconfigurable computing platform, which exploits the coarse-grained parallelism of the processor along with the fine-grained parallelism of the reconfigurable computing devices available in the form of fieldprogrammable gate arrays. In this paper, we illustrate the functioning of the framework, which can be used to calculate the energies for a model cluster of helium atoms. In addition, we present the capabilities of the framework that allow the user to vary the chemical identities of the simulated atoms. Program summary Program title: Hardware Accelerated Quantum Monte Carlo (HAQMC) Catalogue identifier: AEEP _0_0 Program summary URL: http://***/summaries/AEEP_v1_*** Program obtainable from: CPC Program Library, Queen's University, Belfast, N. Ireland Licensing provisions: Standard CPC licence, http://***/licence/*** No. of lines in distributed program, including test data, etc.: 691537 No. of bytes in distributed program, including test data, etc.: 5 03 1226 Distribution format. *** Programming language: C/C++ for the QMC application, VHDL and Xilinx 8.1 ISE/EDK tools for FPGAdesigil and development Computer- Cray

关键词： Reconfigurable computing field-programmable gate arrays FPGA Cray XD1 Monte Carlo Quantum Monte Carlo

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Scalable register bypassing for FPGA-based processors

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MICROPROCESSORS AND MICROSYSTEMS 2009年第7-8期33卷 441-452页

作者： Kavvadias, Nikolaos Nikolaidis, Spiridon Aristotle Univ Thessaloniki Dept Phys Sect Elect & Comp Thessaloniki 54124 Greece

In this paper, a scalable scheme, configurable via register-transfer level parameters, for full register bypassing in a modern embedded processor architecture, termed ByoRISC, is presented. The register bypassing specification is parameterized regarding the number of homogeneous register file read and write ports and the number of pipeline stages of the processor. The performance characteristics (cycle time, chip area) of the proposed technique have been evaluated for FPGA target implementations of the synthesizable ByoRISC model. It is proved that, a full bypassing network is a viable solution for the elimination of data hazards when servicing instructions with multiple read and write operands. While the maximum clock frequency is reduced by 17.9% in average, when using partial versus full forwarding, the positive effect of custom computation eliminates this effect by providing cycle speedups of 3.9x to 5.5x and corresponding execution time speedups for a ByoRISC testbed processor of 3.6x. Individual application speedups of up to 9.4x have also been obtained. (C) 2009 Elsevier B.V. All rights reserved.

关键词： Microprocessors Register bypassing field-programmable gate arrays Embedded systems Hardware description languages

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An FPGA-Based Multiple-Axis Motion Control Chip

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2009年第3期56卷 856-870页

作者： Cho, Jung Uk Le, Quy Ngoc Jeon, Jae Wook Sungkyunkwan Univ Sch Informat & Commun Engn Suwon 440746 South Korea

This paper presents the design and implementation of a multiple-axis motion control chip using a field-programmable gate array (FPGA). This multiple-axis motion control chip is designed to control a multiple-axis motion system such as a robotic arm manipulator or a computer numerical control machine. The proposed motion control chip has many functions. These include velocity profile generation, interpolation calculation, inverse kinematics calculation, proportional-integral-derivative control, feedback count, pulse integration, data conversion, clock generation, and external interfacing. These functions are designed using the VHSIC hardware description language and implemented on an FPGA according to the electronic design automation design methodology. This allows for a highly sampled, accurate, flexible, compact, low-power, and low-cost motion control system. The detailed design of the proposed motion control chip is presented. A multiple-axis motion control system using this chip is implemented, and its performance is measured. The multiple-axis motion control system is implemented on a platform consisting of a chip-based multiple-axis motion controller, analog ac servo drivers, a selective compliant assembly robot arm robot, and a host personal computer.

关键词： field-programmable gate arrays manipulators motion control multiple-axis motion VHSIC hardware description language (VHDL)

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A RECONFIGURABLE ARRAY FOR BLIND SOURCE-SEPARATION ON AN FPGA

A RECONFIGURABLE ARRAY FOR BLIND SOURCE-SEPARATION ON AN FPG...

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2nd International Conference on Biomedical Electronics and Devices

作者： Escalona, Ricardo Herrera, Daniel Figueroa, Miguel Univ Concepcion Dept Elect Engn Concepcion Chile

ISBN: (纸本)9789898111647

We present a reconfigurable array which performs blind source separation on a range of field-programmable gate array (FPGA) devices. Our array uses independent component analysis (ICA) with the InfoMax algorithm to separate a mixture of signals without an external reference. We describe two configurations of the array, representing distinct points in the design space. Our experimental results show a performance improvement of more than one order of magnitude over an optimized software implementation of the algorithm on a computer, with a power consumption of just 100mW. Our array successfully separates a fetal electrocardiogram (ECG) mixture into the source signals of mother and fetus, enabling medical analysis on the resulting independent components.

关键词： Blind source-separation Independent component analysis InfoMax Embedded signal processing field-programmable gate arrays

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A Genetic Based Algorithm for Frequency Relaying using FPGAs

A Genetic Based Algorithm for Frequency Relaying using FPGAs

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General Meeting of the IEEE-Power-and-Energy-Society

作者： Coury, D. V. Oleskovicz, M. Delbem, A. C. B. Simoes, E. V. Silva, T. V. de Carvalho, J. R. Barbosa, D. Univ Sao Paulo Engn Sch Sao Carlos Dept Elect Engn BR-13566590 Sao Carlos SP Brazil Univ Sao Paulo Comp Sci BR-13566590 Sao Carlos SP Brazil Univ Sao Paulo Inst Math & Comp Sci BR-13566590 Sao Carlos SP Brazil

ISBN: (纸本)9781424442409

This work presents an accurate and precise Genetic Algorithm (GA) for frequency estimation of Electrical Power System (EPS) signals. The problem of estimating the frequency of a distorted electrical signal is modeled as an optimization problem. The advantages of GAs in this approach include the use of coding for a number of solutions which facilitates computer implementation, as well as the search for an appropriate solution from a population of possible solutions. The GA is programmed in a FPGA (field-programmable gate Array) device and the estimation procedure is performed in real-time. This is made possible due to (a) the implicit parallelism of FPGAs in computing their instructions and (b) the suitable choice of steps of GAs to explore this parallelism. To evaluate the performance of the proposed method, an EPS was simulated having typical operation conditions. The resulting signals were analyzed by the proposed GA-FPGA approach and promising results were compared to a commercial relay.

关键词： Frequency estimation Genetic algorithms field-programmable gate arrays Digital relaying Power system protection

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Packing Techniques for Virtex-5 FPGAs

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2009年第3期2卷 18-18页

作者： Ahmed, Taneem Kundarewich, Paul D. Anderson, Jason H. Xilinx Inc Toronto ON M4V 3A1 Canada

Packing is a key step in the FPGA tool flow that straddles the boundaries between synthesis, technology mapping and placement. Packing strongly influences circuit speed, density, and power, and in this article, we consider packing in the commercial FPGA context and examine the area and performance trade-offs associated with packing in a state-of-the-art FPGA-the Xilinx (R) Virtex (TM)-5 FPGA. In addition to look-up-table (LUT)-based logic blocks, modern FPGAs also contain large IP blocks. We discuss packing techniques for both types of blocks. Virtex-5 logic blocks contain dual-output 6-input LUTs. Such LUTs can implement any single logic function of up to 6 inputs, or any two logic functions requiring no more than 5 distinct inputs. The second LUT output has reduced speed, and therefore, must be used judiciously. We present techniques for dual-output LUT packing that lead to improved area-efficiency, with minimal performance degradation. We then describe packing techniques for large IP blocks, namely, block RAMs and DSPs. We pack circuits into the large blocks in a way that leverages the unique block RAM and DSP layout/architecture in Virtex-5, achieving significantly improved design performance.

关键词： Design Algorithms field-programmable gate arrays FPGAs optimization packing placement technology mapping performance power logic density

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A Flexible Heterogeneous Hardware/Software Solution for Real-Time HD H.264 Motion Estimation

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 2008年第12期18卷 1781-1785页

作者： Urban, Fabrice Poullaouec, Ronan Nezan, Jean-Francois Deforges, Olivier Thomson R&D Content Delivery & Compress Lab F-35576 Cesson Sevugne France CNRS UMR 6164 Inst Elect & Telecommun Rennes Image Grp Lab Rennes France

Quarter-pixel accuracy and variable block-size significantly enhance compression performances of the MPEG-4 AVC/H.264 video compression standard over its predecessors, but also significantly increase computation requirements. Firstly, a digital signal processor (DSP)-based solution that achieves real-time integer motion estimation is proposed. Fractional-pixel refinement is too computationally intensive to be efficiently processed on a software-based processor. To address this restriction, a flexible and low complexity VLSI subpixel refinement coprocessor is designed. Thanks to an improved datapath, a high throughput is achieved with low logic resources. Finally, an heterogeneous (DSP-field-programmable gate array) solution to handle real-time motion estimation with variable block-size and fractional-pixel accuracy for high-definition video is studied. This solution, combining programmability and efficiency, achieves motion estimation of 720 p sequences at up to 60 fps.

关键词： Digital signal processors field-programmable gate arrays H.264 motion estimation parallel processing real-time

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Provably sublinear point multiplication on Koblitz curves and its hardware implementation

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IEEE TRANSACTIONS ON COMPUTERS 2008年第11期57卷 1469-1481页

作者： Dimitrov, Vassil S. Jarvinen, Kimmo U. Jacobson, Michael J., Jr. (Andy) Chan, Wai Fong Huang, Zhun Univ Calgary Dept Elect & Comp Engn Calgary AB T2N 1N4 Canada Aalto Univ Dept Signal Proc & Acoust FIN-02150 Espoo Finland Univ Calgary Dept Comp Sci Calgary AB T2N 1N4 Canada VIA Technol Beijing Peoples R China

We describe algorithms for point multiplication on Koblitz curves using multiple-base expansions of the form k = Sigma +/- tau(a) (tau - 1)(b) and k = Sigma +/- tau(a)(tau - mu)(b)(tau(2) - mu tau - 1)(c). We prove that the number of terms in the second type is sublinear in the bit length of k, which leads to the first provably sublinear point multiplication algorithm on Koblitz curves. For the first type, we conjecture that the number of terms is sublinear and provide numerical evidence demonstrating that the number of terms is significantly less than that of tau-adic nonadjacent form expansions. We present details of an innovative FPGA implementation of our algorithm and performance data demonstrating the efficiency of our method. We also show that implementations with very low computation latency are possible with the proposed method because parallel processing can be exploited efficiently.

关键词： elliptic curve cryptography field-programmable gate arrays Koblitz curves multiple-base expansions parallel processing sublinearity

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Reconfigurable hardware solution to parallel prefix computation

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JOURNAL OF SUPERCOMPUTING 2008年第1期43卷 43-58页

作者： Park, Jin Hwan Dai, H. K. SUNY Albany Dept Comp Sci New Paltz NY 12561 USA Oklahoma State Univ Dept Comp Sci Stillwater OK 74078 USA

This paper presents the design and implementation of an efficient reconfigurable parallel prefix computation hardware on field-programmable gate arrays (FPGAs). The design is based on a pipelined dataflow algorithm, and control logic is added to reconfigure the system for arbitrary parallelism degree. The system receives multiple input streams of elements in parallel and produces output streams in parallel. It has an advantage of controlling the degree of parallelism explicitly at run time. The time complexity of the design is O(d+(N-d)/d), where d and N are parallelism degree and stream size, respectively. When the stream size is sufficiently larger than the initial trigger time of the pipeline (d), the time complexity becomes O(N/d). Unlike the prefix computation circuits found in the literature, the design is scalable for different problem sizes including unknown sized data. The design is modular based on a finite state machine, and implemented and tested for target FPGA devices Xilinx Spartan2S XC2S300EFT256-6Q and XC2S600EFG676-6.

关键词： parallel prefix computation reconfigurable hardware field-programmable gate arrays dataflow pipeline

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