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25th IEEE Instrumentation and Measurement Technology Conference

作者： Boggarpu, Naveen K. Kavanagh, Richard C. Univ Coll Cork Dept Elect & Elect Engn Cork Ireland

ISBN: (纸本)9781424415403

A novel compensation method to greatly reduce the slit errors (i.e. code wheel errors) that are caused by non-idealites in optical incremental encoders is proposed in this paper Manufacturing limitations in the code wheel, optical components and analog circuitry hinder the use of cheaper encoders for high-end applications. To measure the shaft velocity, the M/T-type Constant Sample-time Digital Tachometer (CSDT) method, which involves both pulse-count and auxiliary timer measurement, is employed to effectively time-stamp the encoder transitions, thereby removing the quantization error that is often associated with the sampling of digital positions. However the accuracy of the velocity calculation is usually compromised by encoder errors. This paper presents a two-stage, software solution to the problem. During the initial learning stage (which can be performed in-situ without the use of any expensive, high-accuracy reference equipment), the slit errors are calculated using the information obtained from the CSDT while subsequent operation of the motion system utilizes adjusted edge positions for velocity calculation. The performance improvement in velocity measurement associated with the learning algorithm is demonstrated using both a simulation model and an experimental implementation that utilizes a three-channel, optical incremental encoder, field-programmable gate array (FPGA) and digital signal processor (DSP).

关键词： Digital measurement error compensation optical transducers optical velocity measurement field-programmable gate arrays table lookup tachometers slit error

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Systematic generation of FPGA-based FFT implementations

Systematic generation of FPGA-based FFT implementations

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33rd IEEE International Conference on Acoustics, Speech and Signal Processing

作者： Kee, Hojin Petersen, Newton Kornerup, Jacob Bhattacharyya, Shuvra S. Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA Natl Instruments Corp Austin TX 78759 USA

ISBN: (纸本)9781424414833

In this paper, we propose a systemic approach for synthesizing field-programmable gate array (FPGA) implementations of fast Fourier transform (FFT) computations. Our approach considers both cost (in terms of FPGA resource requirements), and performance (in terms of throughput), and optimizes for both of these dimensions based on user-specified requirements. Our approach involves two orthogonal techniques - FFT inner loop unrolling and outer loop unrolling - to perform design space exploration in terms of cost and performance. By appropriately combining these two forms unrolling, we can achieve cost-optimized FFT implementations in terms of FPGA slices or block RAMs in FPGA, subject to the required throughput. We compared the results of our synthesis approach with a recently-introduced commercial FPGA intellectual property (IP) core - the FFT IP module in the Xilinx LogiCore Library, which provides different FFT implementations that are optimized for a limited set of performance levels. Our results demonstrate efficiency levels that are in some cases better than these commercial IP blocks. At the same time, our approach provides the advantages of being able to optimize implementations based on arbitrary, user-specified performance levels, and of being based on general formulations of FFT loop unrolling trade-offs, which can be retargeted to different kinds of FPGA devices.

关键词： fast Fourier transform field-programmable gate arrays memory management high-level synthesis

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Architecture-Specific Packing for Virtex-5 FPGAs 08

Architecture-Specific Packing for Virtex-5 FPGAs

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16th ACM/SIGDA International Symposium on field-programmable gate arrays

作者： Ahmed, Taneem Kundarewich, Paul D. Anderson, Jason H. Taylor, Brad L. Aggarwal, Rajat Xilinx Inc Toronto ON Canada

ISBN: (纸本)9781595939340

We consider packing in the commercial FPGA context and examine the speed, performance and power trade-offs associated with packing in a state-of-the art FPGA - the Xilinx (R) Virtex (TM) -5 FPGA. Two aspects of packing are discussed: 1) packing for general logic blocks, and 2) packing for large IP blocks. Virtex-5 logic blocks contain dual-output 6-input look-up-tables (LUTs). Such LUTs call implement any single logic function requiring no more than 6 inputs, or any two logic functions requiring no more than 5 distinct inputs. The second LUT Output is associated with slower speed, and therefore, must be used judiciously. We present placement-based techniques for dual-output LUT packing that;lead to improved area-efficiency and power, with minimal performance degradation. We then move on to address packing for large IP blocks, specifically, block RAMs and DSPs. We present a packing optimization that is widely applicable in DSP designs that leads to significantly improved design performance.

关键词： field-programmable gate arrays FPGAs optimization packing placement power performance

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New Learning Algorithm for High-Quality Velocity Measurement from Low-Cost Optical Encoders

New Learning Algorithm for High-Quality Velocity Measurement...

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2008 IEEE Instrumentation and Measurement Technology Conference (I2MTC 2008), vol.5

作者： Naveen K. Boggarpu Richard C. Kavanagh Department of Electrical and Electronic Engineering University College Cork Ireland

A novel compensation method to greatly reduce the slit errors (i.e. code wheel errors) that are caused by non-idealites in optical incremental encoders is proposed in this paper. Manufacturing limitations in the code wheel, optical components and analog circuitry hinder the use of cheaper encoders for high-end applications. To measure the shaft velocity, the M/T-type Constant Sample-time Digital Tachometer (CSDT) method, which involves both pulse-count and auxiliary timer measurement, is employed to effectively time-stamp the encoder transitions, thereby removing the quantization error that is often associated with the sampling of digital positions. However, the accuracy of the velocity calculation is usually compromised by encoder errors. This paper presents a two-stage, software solution to the problem. During the initial learning stage (which can be performed in-situ without the use of any expensive, high-accuracy reference equipment), the slit errors are calculated using the information obtained from the CSDT, while subsequent operation of the motion system utilizes adjusted edge positions for velocity calculation. The performance improvement in velocity measurement associated with the learning algorithm is demonstrated using both a simulation model and an experimental implementation that utilizes a three-channel, optical incremental encoder, field-programmable gate array (FPGA) and digital signal processor (DSP).

关键词： Digital measurement error compensation optical transducers optical velocity measurement field-programmable gate arrays table lookup tachometers slit error

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Scalable and modular algorithms for floating-point matrix multiplication on reconfigurable computing systems

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2007年第4期18卷 433-448页

作者： Zhuo, Ling Prasanna, Viktor K. Univ So Calif Dept Elect Engn Syst Los Angeles CA 90089 USA

The abundant hardware resources on current reconfigurable computing systems provide new opportunities for high-performance parallel implementations of scientific computations. In this paper, we study designs for floating- point matrix multiplication, a fundamental kernel in a number of scientific applications, on reconfigurable computing systems. We first analyze design trade-offs in implementing this kernel. These trade-offs are caused by the inherent parallelism of matrix multiplication and the resource constraints, including the number of configurable slices, the size of on-chip memory, and the available memory bandwidth. We propose three parameterized algorithms which can be tuned according to the problem size and the available hardware resources. Our algorithms employ a linear array architecture with simple control logic. This architecture effectively utilizes the available resources and reduces routing complexity. The Processing Elements (PEs) used in our algorithms are modular so that it is easy to embed floating- point units into them. Experimental results on a Xilinx Virtex-II Pro XC2VP100 show that our algorithms achieve good scalability and high sustained GFLOPS performance. We also implement our algorithms on Cray XD1. XD1 is a high-end reconfigurable computing system that employs both general-purpose processors and reconfigurable devices. Our algorithms achieve a sustained performance of 2.06 GFLOPS on a single node of XD1.

关键词： scientific computing field-programmable gate arrays reconfigurable hardware computations on matrices parallel algorithms

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Power and area minimization for multidimensional signal processing

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2007年第4期42卷 922-934页

作者： Markovic, Dejan Nikolic, Borivoje Brodersen, Robert W. Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90095 USA Univ Calif Berkeley Berkeley Wireless Res Ctr Berkeley CA 94704 USA

Sensitivity-based methodology is applied to optimization of performance, power and area across several levels of design abstraction for a complex wireless baseband signal processing algorithm. The design framework is based on a unified, block-based graphical description of the algorithm to avoid design re-entry in various phases of chip development. The use of architectural techniques for minimization of power and area for complex signal processing algorithms is demonstrated using this framework. As a proof of concept, an ASIC realization of the MIMO baseband signal processing for a multi-antenna WLAN is described. The chip implements a 4 x 4 adaptive singular value decomposition (SVD) algorithm with combined power and area minimization achieving a power efficiency of 2.1 GOPS/mW (12-bit add equivalent) in just 3.5 mm(2) in a standard 90 nm CMOS process. The computational throughput of 70 GOPS is implemented with 0.5 M cells at a 100 MHz clock and 385 mV supply, dissipating 34 mW of power. With optimal channel conditions the algorithm implemented can deliver up to 250 Mb/s over 16 sub-carriers.

关键词： circuit optimization CMOS digital integrated circuits design methodology field-programmable gate arrays matrix decomposition MIMO systems multidimensional signal processing parallel architectures pipelines sensitivity

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Development of a customized processor architecture for accelerating genetic algorithms

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MICROPROCESSORS AND MICROSYSTEMS 2007年第5期31卷 347-359页

作者： Kavvadias, Nikolaos Giannakopoulou, Vasiliki Nikolaidis, Spirldon Aristotle Univ Thessaloniki Sect Elect & Comp Dept Phys Thessaloniki 54124 Greece

In this paper, a new programmable RISC processor architecture named VGP-I is proposed, aiming to the acceleration of genetic algorithms in embedded systems. Compared to other GA engines, the VGP-I specification defines a compact instruction set supporting multiple operator types, with scalable instruction encodings, prograrnmer-visible and auxiliary registers and optional extensions. Apart from the programmable accelerator approach, VGP-I instructions have been tightly integrated to the Nios II soft-core processor as well. For performance assessment, a cycle-accurate reference VGP-I model has been developed while VGP-I subsets have been realized on a prototype microarchitecture and as Nios 11 custom instructions, both verified on programmable logic. Performance improvements on the execution of genetic operators are typically at the level of two orders of magnitude with application kernels written in ANSI C being accelerated by about 20x due to the usage of GA instruction set extensions. (c) 2007 Elsevier B.V. All rights reserved.

关键词： embedded systems field-programmable gate arrays genetic algorithms application-specific processors hardware description languages

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Real-time digital hardware simulation of power electronics and drives

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IEEE TRANSACTIONS ON POWER DELIVERY 2007年第2期22卷 1235-1246页

作者： Parma, Gustavo G. Dinavahi, Venkata Univ Fed Minas Gerais Dept Elect BR-3009210 Belo Horizonte MG Brazil Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2V4 Canada

This gaper presents a digital hardware realization of a real-time simulator for a complete induction machine drive using a field-programmable gate array (FPGA) as the computational engine. The simulator was developed using Very High Speed Integrated Circuit Hardware Description Language (VHDL), making it flexible and portable. A novel device-characteristic based model suitable for FPGA implementation has been proposed for the 2-level 6-pulse IGBT-based voltage-source converter (VSC). The VSC model is computed at a fixed time-step of 12.5 ns allowing a highly detailed and precise accounting of gating signals. The simulator also models a squirrel cage induction machine, a direct field-oriented control system, a space-vector pulse-width modulation scheme (SVPWM) and a measurement system. A multirate simulation of the system shows the slow (machine) as well as the fast (VSC and control) dynamic components. Real time simulation results under steady-state and transient conditions demonstrate modeling accuracy and efficiency.

关键词： field-programmable gate arrays induction motor drives pulse-width-modulated power converters real-time systems

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GlitchLess: An Active Glitch Minimization Technique for FPGAs 07

GlitchLess: An Active Glitch Minimization Technique for FPGA...

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15th ACM/SIGDA International Symposium on field-programmable gate arrays

作者： Lamoureux, Julien Lemieux, Guy G. Wilton, Steven J. E. Univ British Columbia Dept Elect & Comp Engn Vancouver BC V5Z 1M9 Canada

ISBN: (纸本)9781595936004

This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable delay elements within the logic blocks of an FPGA to programmably align the arrival times of early-arriving signals to the inputs of the lookup tables and to filter out glitches generated by earlier circuitry. On average, the proposed technique eliminates 91% of the glitching, which reduces overall FPGA power by 18%. The added circuitry increases overall area by 5% and critical-path delay by less than 1%. Furthermore, since it is applied after routing, the proposed technique requires no modifications to the existing FPGA routing architecture or CAD flow.

关键词： field-programmable gate arrays Power Minimization

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RAMP: Research accelerator for multiple processors

RAMP: Research accelerator for multiple processors

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Hot Chips 18 Conference

作者： Wawrzynek, John Patterson, David Oskin, Mark Lu, Shih-Lien Kozyrakis, Christoforos Hoe, James C. Chiou, Derek Asanovic, Krste Univ Calif Berkeley Div Comp Sci Berkeley CA 94720 USA

The RAMP project's goal is to enable the intensive, multidisciplinary innovation that the computing industry will need to tackle the problems of parallel processing. RAMP itself is an open-source, community-developed, FPGA-based emulator of parallel architectures. Its design framework lets a large, collaborative community develop and contribute reusable, composable design modules. Three complete designs - for transactional memory, distributed systems, and distributed-shared memory - demonstrate the platform's potential.

关键词： Distributed systems Distributed-shared memory Emulation field-programmable gate arrays Hardware-software codesign Integration Modeling of computer architecture Parallel architectures Transactional memory

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