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Segmented routing for speed-performance and routability in field-programmable gate arrays

VLSI DESIGN 1996年第4期4卷 275-291页

作者： Brown, S Khellah, M Lemieux, G Department of Electrical and Computer Engineering University of Toronto Canada

This paper addresses several issues involved for routing in field-programmable gate arrays (FPGAs) that have both horizontal and vertical routing channels, with wire segments of various lengths. Routing is studied by using CAD routing tools to map a set of benchmark circuits into FPGAs, and measuring the effects that various parameters of the CAD tools have on the implementation of the circuits. A two-stage routing strategy of global followed by detailed routing is used, and the effects of both of these CAD stages are discussed, with emphasis on detailed routing, We present a new detailed routing algorithm designed specifically for the types of routing structures found in the most recent generation of FPGAs, and show that the new algorithm achieves significantly better results than previously published FPGA routers with respect to the speed-performance of implemented circuits. The experiments presented in this paper address both of the key metrics for FPGA routing tools, namely the effective utilization of available interconnect resources in an FPGA, and the speed-performance of implemented circuits. The major contributions of this research include the following: 1) we illustrate the effect of a global router on both area-utilization and speed-performance of implemented circuits, 2) experiments quantify the impact of the detailed router cost functions on area-utilization and speed-performance, 3) we show the effect on circuit implementation of dividing multi-point nets in a circuit being routed into point-to-point connections, and 4) the paper illustrates that CAD routing tools should account for both routability and speed-performance at the same time, not just focus on one goal.

关键词： field-programmable gate arrays FPGAs CAD routability speed-performance

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Characterization and parameterized generation of synthetic combinational benchmark circuits

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1998年第10期17卷 985-996页

作者： Hutton, MD Rose, J Grossman, JP Corneil, DG Altera Corp San Jose CA 95134 USA Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada Univ Toronto Dept Comp Sci Toronto ON M5S 3G4 Canada

The development of new field-programmed, mask-programmed, and laser-programmed gate-array architectures is hampered by the lack of realistic test circuits that exercise both the architectures and their automatic placement and routing algorithms. In this paper, we present a method and a tool for generating parameterized and realistic synthetic circuits. To obtain the realism, we propose a set of graph-theoretic characteristics that describe a physical netlist, and have built a tool that can measure these characteristics on existing circuits. The generation tool uses the characteristics as constraints in the synthetic circuit generation. To validate the quality of the generated netlists, parameters that are not specified in the generation are compared with those of real circuits and with those of more "random" graphs.

关键词： algorithms design automation field-programmable gate arrays

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Optimal clock period fpga technology mapping for sequential circuits

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ACM Transactions on Design Automation of Electronic Systems 1998年第3期3卷 437-462页

作者： Pan, Reichen Liu, C.L. Clarkson University Potsdam NY United States University of Illinois at Urbana-Champaign Urbana IL United States Department of Electrical and Computer Engineering Clarkson University Potsdam NY 13699 United States Department of Computer Science University of Illinois at Urbana-Champaign Urbana IL 61801 United States

We study the technology mapping problem for sequential circuits for look-up table (LUT) based field programmable gate arrays (FPGAs). Existing approaches to the problem simply remove the flip-flops (FFs), then map the remaining combinational logic, and finally put the FFs back. These approaches ignore the sequential nature of a circuit and assume the positions of the FFs are fixed. However, FFs in a sequential circuit can be repositioned by a functionality-preserving transformation called retiming. As a result, existing approaches can only consider a very small portion of the available solution space. We propose in this paper a novel approach to the technology mapping problem. In our approach, retiming is integrated into the technology mapping process so as to consider the full solution space. We then present a polynomial technology mapping algorithm that, for a given circuit, produces a mapping solution with the minimum clock period among all possible ways of retiming. The effectiveness of the algorithm is also demonstrated experimentally. © 1999 ACM.

关键词： Algorithms Clock period field-programmable gate arrays FPGAs Logic replication Look-up tables Performance Retiming Sequential synthesis Technology mapping

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CRITICAL PATH-ANALYSIS FOR field-programmable gate arrays

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MICROPROCESSORS AND MICROSYSTEMS 1995年第7期19卷 435-439页

作者： [Anonymous] Texas Instruments

Device speed, or timing, is a critical aspect of system design. A realistic estimate of the achievable system speed is often required early in the design phase to avoid waste of valuable design time. System speed, of course, depends on the operation of all system components. This application note describes how to estimate the timing constraints of a field-programmable gate array (FPGA) design. However, the FPGA is only one component within the design: other devices also affect the system speed.

关键词： CRITICAL PATH ANALYSIS field-programmable gate arrays TIMING CONSTRAINTS

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A robust multiplexer-based FPGA inspired by biological systems

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JOURNAL OF SYSTEMS ARCHITECTURE 1997年第10期43卷 719-733页

作者： Tempesti, G Mange, D Stauffer, A Logic Systems Laboratory Department of Computer Science Swiss Federal Institute of Technology (EPFL) CH-1015 Lausanne Switzerland

Biological organisms are among the most robust systems known to man. Their robustness is based on a set of processes which cannot be adapted directly to the world of silicon but can provide an inspiration for the design of robust circuits. This paper introduces a multiplexer-based field programmable gate Array (FPGA) which we made capable of self-test and self-repair using an approach loosely based on biological mechanisms at the cellular level. The system is designed to provide on-line self-test and self-repair using a completely distributed system and a minimal amount of additional logic.

关键词： self-test self-repair field-programmable gate arrays reconfiguration embryonics

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On optimal board-level routing for FPGA-based logic emulation

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1997年第3期16卷 282-289页

作者： Mak, WK Wong, DF Department of Computer Sciences University of Technology Austin TX USA

In this paper, we consider a board-level routing problem which is applicable to held-programmable gate arrays (FPGA)-based logic emulation systems such as the Realizer System [3] and the Enterprise Emulation System [5] manufactured by Quickturn Design Systems. For the case where all nets are two-terminal nets, we present an O(n(2))-time optimal algorithm where n is the number of nets. Our algorithm guarantees 100% routing completion if the number of interchip signal pins on each FPGA chip in the logic emulation system is less than or equal to the number of I/O pins on the chip. Our algorithm is based on iterative computation of Euler circuits in graphs. We also prove that the routing problem with multiterminal nets is NP-complete. And we suggest one way to handle multiterminal nets using some additional resources.

关键词： design automation field-programmable gate arrays logic emulation routing

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Board-level multiterminal net routing for FPGA-based logic emulation

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ACM Transactions on Design Automation of Electronic Systems 1997年第2期2卷 151-167页

作者： Mak, Wai-Kei Wong, D.F. University of Texas at Austin Austin TX United States Department of Computer Sciences University of Texas at Austin Austin TX 78712 United States

We consider a board-level routing problem applicable to FPGA-based logic emulation systems such as the Realizer System [Varghese et al. 1993] and the Enterprise Emulation System [Maliniak 1992] manufactured by Quickturn Design Systems. Optimal algorithms have been proposed for the case where all nets are two-terminal nets [Chan and Schlag 1993;Mak and Wong 1995]. We show how multiterminal nets can be handled by decomposition into two-terminal nets. We show that the multiterminal net decomposition problem can be modeled as a bounded-degree hypergraph-to-graph transformation problem where hyperedges are transformed to spanning trees. A network flow-based algorithm that solves both problems is proposed. It determines if there is a feasible decomposition and gives one whenever such a decomposition exists. © 1997 ACM.

关键词： Board-level routing Crossbars field-programmable gate arrays Logic emulation Multi-terminal net decomposition

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Tradeoff literals against support for logic synthesis of LUT-based FPGAs

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 1996年第2期143卷 111-119页

作者： Lu, A Dagless, E Saul, J UNIV OXFORD COMP LABOXFORD OX1 3QDENGLAND

The paper deals with logic synthesis of lookup-table (LUT) based field-programmable gate arrays (FPGAs). Because each LUT can implement any k input Boolean function with the same area cost, the optimisation criterion of literal count, generally used in other multi-level logic synthesis methods, is not suitable for LUT-based technologies. Therefore a new logic optimisation criterion is proposed, which trades off literals against support. Based on this criterion, five logic operations in logic optimisation are analysed, and made to evaluate the circuit cost in accordance with the target technology. Using these techniques of logic optimisation, a good starting point for technology mapping of LUT-based FPGAs has been obtained. In the technology mapping phase, LUT-directed decomposition is applied. Experimental results indicate that synthesised circuits are much smaller and more routable than the circuits synthesised by other tools.

关键词： look-up tables technology mapping field-programmable gate arrays

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ARCHITECTURE OF field-programmable gate arrays

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PROCEEDINGS OF THE IEEE 1993年第7期81卷 1013-1029页

作者： ROSE, J ELGAMAL, A SANGIOVANNIVINCENTELLI, A STANFORD UNIV DEPT ELECT ENGNSTANFORDCA 94305 UNIV CALIF BERKELEY DEPT ELECT ENGN & COMP SCIBERKELEYCA 94720

A survey of field-programmable gate Array (FPGA) architectures and the programming technologies used to customize them is presented. Programming technologies are compared on the basis of their volatility, size, parasitic capacitance, resistance, and process technology complexity. FPGA architectures are divided into two constituents: logic block architectures and routing architectures. A classification of logic blocks based on their granularity is proposed and several logic blocks used in commercially available FPGA's are described. A brief review of recent results on the effect of logic block granularity on logic density and performance of an FPGA is then presented. Several commercial routing architectures are described in the context of a general routing architecture modeL Finally, recent results on the tradeoff between the flexibility of an FPGA routing architecture its routability and density are reviewed.

关键词： FPGA architectures PLD programming application specific integrated circuits field-programmable gate arrays granularity logic arrays logic block architectures logic density network routing parasitic capacitance process technology complexity programming technologies resistance routing architectures

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Effects of technology mapping on fault-detection coverage in reprogrammable FPGAs

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 1995年第6期142卷 407-410页

作者： Kwiat, K Debany, W Hariri, S SYRACUSE UNIV DEPT ELECT & COMP ENGNSYRACUSENY 13244

Although field-programmable gale arrays (FPGAs) are tested by their manufacturers prior to shipment, they are still susceptible to failures in the field, In this paper test vectors generated for the emulated (i.e. mission) circuit are fault-simulated on two different models: the original view of the circuit, and the design as it is mapped to the FPGA's logic cells, Faults in the cells and in the programming logic are considered. Experiments show that this commonly-used approach fails to detect most of the faults in the FPGA.

关键词： fault detection field-programmable gate arrays

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