Recent advances in field-programmable gate arrays (FPGA) and programmable interconnects have made it possible to build efficient hardware emulation engines. In addition, improvements in Computer-Aided Design (CAD) too...
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ISBN:
(纸本)9780897917438
Recent advances in field-programmable gate arrays (FPGA) and programmable interconnects have made it possible to build efficient hardware emulation engines. In addition, improvements in Computer-Aided Design (CAD) tools, mainly in synthesis tools, greatly simplify the design of large circuits. The RPM (Rapid Prototype Engine for Multiprocessors) Project leverages these two technological advances. Its goal is to develop a common hardware platform for the emulation of multiprocessor systems with different *** cost reasons, the use of FPGAs in RPM is limited to the memory controllers, while the rest of the emulator, including the processors, memories and interconnect, is built with off-the-shelf components. A flexible non-intrusive event logging mechanism is included at all levels of the memory hierarchy, making it possible to monitor the emulation in very fine detail. This paper presents the hardware design of RPM.
Owing to their high degree of flexibility and low design-turnaround time, field-programmable-gate-array (FPGA) based designs are becoming very popular. With the availability of different types of FPGA, the need of a u...
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Owing to their high degree of flexibility and low design-turnaround time, field-programmable-gate-array (FPGA) based designs are becoming very popular. With the availability of different types of FPGA, the need of a unified approach for logic-block-independent technology mapping is being felt increasingly. The paper presents a new approach to efficient realisation of a given combinational function in terms of a prespecified k-input-single-output logic block. All subfunctions of 1 to k inputs realisable by the logic block are generated and kept in a library. The approach is general in the sense that it is not targeted to any specific FPGA built around a specified set of basic blocks. It uses a node-clustering technique for breaking up the given combinational function into subfunctions with special treatment for the fanout nodes. The scheme utilises a novel signature-based strategy to find a match for a subfunction in the library. One contribution is the elegant signature-generation scheme that can be applied for any library-based search problem. The signature is unique for functions of up to four variables and has an aliasing of around 0.5% for functions with larger number of variables. For comparison with other mapping techniques, the KGPMAP algorithm has been applied to several combinational benchmark circuits using Actel's act1-library. The result has been found to be superior to other well known library-based technology mappers and some Actel-specific mappers.
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