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5th IEEE/ACM Symposium on Edge Computing (SEC)

作者： Liu, Shiya Liu, Lingjia Yi, Yang Virginia Tech Bradley Dept Elect & Comp Engn Blacksburg VA 24061 USA

ISBN: (纸本)9781728159430

With the advance of edge computing, a fast and efficient machine learning model running on edge devices is needed. In this paper, we propose a novel quantization approach that reduces the memory and compute demands on edge devices without losing much accuracy. Also, we explore its application in communication such as symbol detection in 5G systems, attack detection of smart grid, and dynamic spectrum access. Conventional neural networks such as convolutional neural networks (CNNs) and recurrent neural networks (RNNs) could be exploited on these applications and achieve state-of-the-art performance. However, conventional neural networks consume a large amount of computation and storage resources, and thus do not fit well to edge devices. Reservoir computing (RC), which is a framework for computation derived from RNN, consists of a fixed reservoir layer and a trained readout layer. The advantages of RC compared to traditional RNNs are faster learning and lower training costs. Besides, RC has faster inference speed with fewer parameters and resistance to overfitting issues. These merits make the RC system more suitable for applications running on edge devices. We apply the proposed quantization approach to RC systems and demonstrate the proposed quantized RC system on Xilinx Zynq (R)-7000 FPGA board. On the sequential MNIST dataset, the quantized RC system utilizes 62%, 65%, and 64% less of DSP, FF, and LUT, respectively compared to the floating-point RNN. The inference speed is improved by 17 times with an 8% accuracy drop.

关键词： edge computing quantization field-programmable gate arrays

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Virtualizing FPGAs in the Cloud 20

Virtualizing FPGAs in the Cloud

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25th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

作者： Zha, Yue Li, Jing Univ Penn Philadelphia PA 19104 USA

ISBN: (纸本)9781450371025

field-programmable gate arrays (FPGAs) have been integrated into the cloud infrastructure to enhance its computing performance by supporting on-demand acceleration. However, system support for FPGAs in the context of the cloud environment is still in its infancy with two major limitations, i.e., the inefficient runtime management due to the tight coupling between compilation and resource allocation, and the high programming complexity when exploiting scale-out acceleration. The root cause is that FPGA resources are not virtualized. In this paper, we propose a full-stack solution, namely ViTAL, to address the aforementioned limitations by virtualizing FPGA resources. Specifically, ViTAL provides a homogeneous abstraction to decouple the compilation and resource allocation. Applications are offline compiled onto the abstraction, while the resource allocation is dynamically determined at runtime. Enabled by a latency-insensitive communication interface, applications can be mapped flexibly onto either one FPGA or multiple FPGAs to maximize the resource utilization and the aggregated system throughput. Meanwhile, ViTAL creates an illusion of a single and large FPGA to users, thereby reducing the programming complexity and supporting scale-out acceleration. Moreover, ViTAL also provides virtualization support for peripheral components (e.g., on-board DRAM and Ethernet), as well as protection and isolation support to ensure a secure execution in the multi-user cloud environment. We evaluate ViTAL on a real system-an FPGA cluster composed of the latest Xilinx UltraScale+ FPGAs (XCVU37P). The results show that, compared with the existing management method, ViTAL enables fine-grained resource sharing and reduces the response time by 82% on average (improving Quality-of-Service) with a marginal virtualization overhead. Moreover, ViTAL also reduces the response time by 25% compared to AmorphOS (operating in high-throughput mode), a recently proposed FPGA virtualization method.

关键词： scale-out acceleration system abstraction compilation framework cloud computing field-programmable gate arrays

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A hardware accelerator for entropy estimation using the top-k most frequent elements 23

A hardware accelerator for entropy estimation using the top-...

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23rd Euromicro Conference on Digital System Design (DSD)

作者： Soto, Javier E. Ubisse, Paulo Hernandez, Cecilia Figueroa, Miguel Univ Concepcion Dept Elect Engn Concepcion Chile Univ Concepcion Dept Comp Sci Concepcion Chile Ctr Biotechnol & Bioengn CeBiB Concepcion Chile

ISBN: (纸本)9781728195353

Estimating the empirical entropy of the elements in a dataset is an important task in data analysis. In particular, empirical entropy can be effectively used to detect anomalies in network traffic. However, computing the empirical entropy of a large dataset is computationally expensive and requires a large amount of memory. This is particularly important in highspeed network traffic analysis, where computing the entropy of a data flow in real time requires using hardware accelerators with restricted on-chip memory and arithmetic resources. In this work, we propose a method to estimate the entropy using a streaming algorithm with sublinear space requirements. Our approach uses a sketch to estimate the frequency of the elements in the stream, and a priority queue to store the top-k most frequent elements. We show that our method can provide a good approximation of the entropy of the dataset, and present the design of a hardware accelerator that can compute the entropy of the stream with a throughput of one packet per clock cycle. Implemented on a Xilinx Zynq UltraScale+ MPSoC ZCU102 FPGA, our accelerator can operate at line rates above 181 Gbps, consuming 511 mW and using less than 24% of the resources available on the device.

关键词： Entropy estimation heavy hitters sketch priority queue hardware acceleration field-programmable gate arrays

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Flexible and low-cost FPGA-based multichannel analyzer for handheld measurement devices

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NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT 2021年 1018卷 165808-165808页

作者： Van Hiep Cao Tien Hung Dinh Thi Thoa Nguyen Khanh Hung Nguyen Dinh Khang Pham Xuan Hai Nguyen Ngoc Anh Nguyen Tien-Anh Nguyen Mil Inst Chem & Environm Engn MICEE Hanoi 100000 Vietnam Hanoi Univ Sci & Technol Hanoi 100000 Vietnam Dalat Nucl Res Inst 01 Nguyen Tu Luc Dalat City Vietnam Le Quy Don Tech Univ Dept Phys Hanoi 11917 Vietnam

This study proposes a flexible, low-cost digital multichannel analyzer (DMCA) based on a field-programmable gate array (FPGA). Digital signal processing modules, including a digital Sallen-Key filter, an energy reconstruction (trapezoidal) filter, a baseline restorer, a timing trigger, and a pulse pile-up rejector, are implemented on FPGA. The proposed DMCA is coupled directly to the detector pre-amplifier without any analog signal conditioning circuit for a simple, compact, and cost-effective hardware design. The parameters of the filtering modules were optimized using MATLAB/Simulink and pulse data digitized using a high-speed analog-to-digital converter. The proposed DMCA also includes a digital gain compensation module to stabilize measured gamma spectra against temperature variation. In addition, software with a user-friendly graphical user interface has been developed for gamma spectrum acquisition and analysis. This prototype DMCA is highly promising for developing handheld radiation measurement devices in terms of performance, cost, and size.

关键词： Digital signal processing field-programmable gate arrays Digital multichannel analyzer

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A Janus compatible software-defined underwater acoustic multiple-input multiple-output modem

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INTERNATIONAL JOURNAL OF DISTRIBUTED SENSOR NETWORKS 2021年第4期17卷 p1-13页

作者： Singh, Surinder Crispo, Mark Bousquet, Jean-Francois Aljendi, Shadi Dalhousie Univ Dept Elect & Comp Engn UW STREAM Halifax NS B4N 4R2 Canada

This article describes the implementation of a multiple-input multiple-output acoustic communication link in shallow water conditions to enable a software-defined acoustic modem with a maximum transmission rate of 20 kbps in a 5-kHz bandwidth. The reliability improvement of a low-complexity Alamouti space-time block code is evaluated to improve the diversity in a high-rate transmission mode using single carrier modulation, as well as in a low-rate transmission mode relying on continuous-phase frequency-shift keying. Using measurements in realistic subsea conditions, the effect of the spatial channel correlation is demonstrated. It is found that for the space-time block code/continuous-phase frequency-shift keying, the spatial diversity is significantly degraded due to the high spatial correlation. In contrast, for the high-mode transmission rate, space-time block code with single carrier modulation offers a bit error rate improvement by a factor over hundred, in comparison to a single transmit element, demonstrating that the multiple-input multiple-output optimal code depends on the software-defined acoustic modem transmission mode.

关键词： Software-defined modem underwater communications multiple-input multiple-output channel characterization field-programmable gate arrays

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A RRAM-based FPGA for Energy-efficient Edge Computing

A RRAM-based FPGA for Energy-efficient Edge Computing

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Tang, Xifan Giacomin, Edouard Cadareanu, Patsy Gore, Ganesh Gaillardon, Pierre-Emmanuel Univ Utah Elect & Comp Engn Salt Lake City UT 84112 USA

ISBN: (纸本)9783981926347

The shift from centralized cloud to edge computing demands hardware systems with data processing capability at ultra-low power. Reconfigurable solutions such as field-programmable gate arrays (FPGAs) offer a high flexibility in terms of hardware implementation and are thus popular for use in many edge computing systems. However, breaking through the energy wall of FPGAs is a challenge, as low-power operation often requires compromising performances. In this paper, we study a low-power high-performance FPGA architecture exploiting Resistive Random Access Memory (RRAM) technology. To perform a comprehensive analysis, we introduce a novel design flow which can rapidly prototype FPGA fabrics from which accurate area, delay, and power results can be obtained. Based on full-chip layouts and SPICE simulations, we show that RRAM-based FPGAs can improve up to 8%/22%/16% in area/delay/power compared to SRAM-based counterparts at nominal voltage. Even when operated at a near-V-t supply, the proposed RRAM-based FPGA can improve the Energy-Delay Product by about 2 x without any delay overhead, when compared to an SRAM-based FPGA. In addition, Monte Carlo simulations showed that the proposed RRAM-based FPGA architecture stays robust under different CMOS process corners as well as under a 30% RRAM resistance standard deviation.

关键词： field-programmable gate arrays Resistive memories Low-power design

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Real-time quantum-accurate voltage waveform synthesis

Real-time quantum-accurate voltage waveform synthesis

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Joint Conference of Conference on Precision Electromagnetic Measurements (CPEM) and Conference of NCSL-International (NCSLI)

作者： Ireland, Jane Protheroe, Stephen Williams, Jonathan Belcher, Allan Dekker, Ronald Schaapman, Kars Iuzzolino, Ricardo Melo, Rodrigo Valinoti, Bruno Bierzychudek, Marcos Sira, Martin Herick, Jonas Kieler, Oliver Behr, Ralf Natl Phys Lab Queens Rd Teddington TW11 0LW Middx England Signal Convers Swansea W Glam Wales Applicos Zwolle Netherlands INTI Buenos Aires DF Argentina CMI Brno Czech Republic Phys Tech Bundesanstalt Braunschweig Germany

ISBN: (纸本)9781728158983

A pulse drive system capable of converting an arbitrary input signal into a delta sigma encoded pulse code stream in real time has been demonstrated. This system is based on the use of analog and digital hardware controlled by a field programmable gate Array (FPGA) rather than using software to produce the delta sigma code and then loading it into the memory of a commercial Pulse Pattern Generator (PPG). The results of using the system to drive a Josephson junction array to synthesize quantum-accurate voltage waveforms are presented. The advantage of such a system includes the significant reduction in time required to change waveform parameters. This provides an easily tunable source of high-fidelity stable voltage waveforms at low temperature for future applications including validation of components for use in quantum technologies.

关键词： field-programmable gate arrays Josephson arbitrary waveform synthesizer Josephson arrays metrology optoelectronics voltage measurement

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A hardware architecture for Multiscale Retinex with Chromacity Preservation on an FPGA 23

A hardware architecture for Multiscale Retinex with Chromaci...

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23rd Euromicro Conference on Digital System Design (DSD)

作者： Palacios, Jorge Andres Caro, Vincenzo Duran, Miguel Figueroa, Miguel Univ Concepcion Dept Elect Engn Concepcion Chile

ISBN: (纸本)9781728195353

Image-processing algorithms based on Retinex theory aim to model human color perception to enhance images with low contrast or poor illumination. In particular, the Multiscale Retinex with Chromacity Preservation (MSRCP) algorithm improves on the original Retinex by processing the image at multiple scales and adding a color balance step in postprocessing. Despite their advantages, multiscale Retinex algorithms are computationally intensive, and real-time video processing is not generally possible with general-purpose processor architectures. In this paper, we present a special-purpose hardware accelerator for the MSRCP algorithm. The accelerator introduces tradeoffs to the original formulation of MSRCP by reducing the magnitude of the scales and using a cumulative histogram in the colorbalance stage. Despite these modifications, we show that the accelerator produces images that are visually almost identical to a software implementation of the original MSRCP algorithm. We implement our design on a Xilinx XC7A200T-1SBG484C FPGA, which is capable of processing 1280 x 720-pixel video at up to 94 frames per second, a speedup of 123x compared to a desktop computer running a software version of the algorithm.

关键词： Image processing multiscale Retinex hardware acceleration field-programmable gate arrays

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Implementation of Massive Artificial Neural Networks with field-programmable gate arrays

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IFAC Proceedings Volumes 2012年第4期45卷 133-138页

作者： Verber Domen Bračič Simon University of Maribor Faculty of Electrical Engineering and Computer Science Maribor Slovenia

This paper presents a novel method for implementing massive artificial neural networks (ANN) with field-programmable gate arrays (FPGA). Because of the sequential nature of programs, the execution of large ANNs in software is inefficient. On the other hand, in FPGA devices that consist of a large number of programmable circuits, the nodes of ANN may be executed in parallel. This provides for higher computational rates and a greater degree of robustness or fault tolerance than in conventional computers. The main goal of these studies was to implement as many neurons as possible on a single FPGA device, without giving up the minimal execution times. In the proposed solution, each neuron is implemented by a single multiplier. For the nonlinear behaviour of a neuron, the activation function is approximated using several linear segments. In order to overcome the limited memory capacity of FPGA, external memory is employed Execution of ANN is controlled by an embedded soft processor.

关键词： Computational intelligence artificial neural networks field-programmable gate arrays parallel computation

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Real-time architecture for channel estimation and equalization in broadband PLC

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MICROPROCESSORS AND MICROSYSTEMS 2019年 65卷 121-135页

作者： Nombela, Francisco Garcia, Enrique Mateos, Raid Hernandez, Alvaro Univ Alcala Dept Elect E-28805 Madrid Spain

Broadband Power Line Communications (PLC) is an attractive area for providing broadband access in facilities where mains are already deployed, such as factories, buildings, houses, etc. In such systems, the design of efficient algorithms for synchronization, channel estimation and equalization is of great importance for reliable communications. Although there is a large amount of research done in channel estimation and equalization for wireless communication systems, the PLC channel has particular features that prevent from directly applying the techniques often used in wireless systems. In this way, PLC channels commonly present frequency selective fading, impulsive noise and coloured noise. Furthermore, some previous algorithms have effectively dealt with undesired channel effects but they imply a high computational complexity and cost, thus limiting their practical applicability. This work proposes real-time FPGA-based (field-programmable gate Array) architecture, designed to implement channel estimation and equalization in broadband PLC. The approach is based on a Wavelet-OFDM (Orthogonal Frequency Division Multiplexing) modulation, also known as FBMC (Filter Bank Multi-Carrier), where cross-correlation techniques have been applied on the Zadoff-Chu sequences used as pilot signals or preambles. The architecture has been implemented in a Xilinx XC7K325T FPGA, and experimental tests in a lab environment successfully show that the proposal can effectively recover the transmitted signals. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Power line communications Wavelet-OFDM Channel estimation and equalization field-programmable gate arrays

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